1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
11 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/serial_8250.h>
15 #include <linux/serial_reg.h>
16 #include <linux/tty_flip.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/console.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/dma-mapping.h>
32 #define DEFAULT_CLK_SPEED 48000000
34 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
35 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
36 #define OMAP_DMA_TX_KICK (1 << 2)
38 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
39 * The same errata is applicable to AM335x and DRA7x processors too.
41 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
43 #define OMAP_UART_FCR_RX_TRIG 6
44 #define OMAP_UART_FCR_TX_TRIG 4
46 /* SCR register bitmasks */
47 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
48 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
49 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
50 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
51 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
52 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
54 /* MVR register bitmasks */
55 #define OMAP_UART_MVR_SCHEME_SHIFT 30
56 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
57 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
58 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
59 #define OMAP_UART_MVR_MAJ_MASK 0x700
60 #define OMAP_UART_MVR_MAJ_SHIFT 8
61 #define OMAP_UART_MVR_MIN_MASK 0x3f
63 /* SYSC register bitmasks */
64 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
66 /* SYSS register bitmasks */
67 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
69 #define UART_TI752_TLR_TX 0
70 #define UART_TI752_TLR_RX 4
72 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
73 #define TRIGGER_FCR_MASK(x) (x & 3)
75 /* Enable XON/XOFF flow control on output */
76 #define OMAP_UART_SW_TX 0x08
77 /* Enable XON/XOFF flow control on input */
78 #define OMAP_UART_SW_RX 0x02
80 #define OMAP_UART_WER_MOD_WKUP 0x7f
81 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
86 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
87 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
89 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
91 #define OMAP_UART_REV_46 0x0406
92 #define OMAP_UART_REV_52 0x0502
93 #define OMAP_UART_REV_63 0x0603
95 struct omap8250_priv {
112 struct pm_qos_request pm_qos_request;
113 struct work_struct qos_work;
114 struct uart_8250_dma omap8250_dma;
115 spinlock_t rx_dma_lock;
120 #ifdef CONFIG_SERIAL_8250_DMA
121 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
123 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
126 static u32 uart_read(struct uart_8250_port *up, u32 reg)
128 return readl(up->port.membase + (reg << up->port.regshift));
131 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
133 struct uart_8250_port *up = up_to_u8250p(port);
134 struct omap8250_priv *priv = up->port.private_data;
137 serial8250_do_set_mctrl(port, mctrl);
140 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
143 lcr = serial_in(up, UART_LCR);
144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
145 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
146 priv->efr |= UART_EFR_RTS;
148 priv->efr &= ~UART_EFR_RTS;
149 serial_out(up, UART_EFR, priv->efr);
150 serial_out(up, UART_LCR, lcr);
154 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
155 * The access to uart register after MDR1 Access
156 * causes UART to corrupt data.
159 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
160 * give 10 times as much
162 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
163 struct omap8250_priv *priv)
165 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
167 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
168 UART_FCR_CLEAR_RCVR);
171 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
172 struct omap8250_priv *priv)
174 unsigned int uartclk = port->uartclk;
175 unsigned int div_13, div_16;
176 unsigned int abs_d13, abs_d16;
179 * Old custom speed handling.
181 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
182 priv->quot = port->custom_divisor & UART_DIV_MAX;
184 * I assume that nobody is using this. But hey, if somebody
185 * would like to specify the divisor _and_ the mode then the
186 * driver is ready and waiting for it.
188 if (port->custom_divisor & (1 << 16))
189 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
191 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
194 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
195 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
202 abs_d13 = abs(baud - uartclk / 13 / div_13);
203 abs_d16 = abs(baud - uartclk / 16 / div_16);
205 if (abs_d13 >= abs_d16) {
206 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
209 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
214 static void omap8250_update_scr(struct uart_8250_port *up,
215 struct omap8250_priv *priv)
219 old_scr = serial_in(up, UART_OMAP_SCR);
220 if (old_scr == priv->scr)
224 * The manual recommends not to enable the DMA mode selector in the SCR
225 * (instead of the FCR) register _and_ selecting the DMA mode as one
226 * register write because this may lead to malfunction.
228 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
229 serial_out(up, UART_OMAP_SCR,
230 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
231 serial_out(up, UART_OMAP_SCR, priv->scr);
234 static void omap8250_update_mdr1(struct uart_8250_port *up,
235 struct omap8250_priv *priv)
237 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
238 omap_8250_mdr1_errataset(up, priv);
240 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
243 static void omap8250_restore_regs(struct uart_8250_port *up)
245 struct omap8250_priv *priv = up->port.private_data;
246 struct uart_8250_dma *dma = up->dma;
247 u8 mcr = serial8250_in_MCR(up);
249 if (dma && dma->tx_running) {
251 * TCSANOW requests the change to occur immediately however if
252 * we have a TX-DMA operation in progress then it has been
253 * observed that it might stall and never complete. Therefore we
254 * delay DMA completes to prevent this hang from happen.
256 priv->delayed_restore = 1;
260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
261 serial_out(up, UART_EFR, UART_EFR_ECB);
263 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
264 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
265 serial_out(up, UART_FCR, up->fcr);
267 omap8250_update_scr(up, priv);
269 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
271 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
272 OMAP_UART_TCR_HALT(52));
273 serial_out(up, UART_TI752_TLR,
274 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
275 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
277 serial_out(up, UART_LCR, 0);
279 /* drop TCR + TLR access, we setup XON/XOFF later */
280 serial8250_out_MCR(up, mcr);
282 serial_out(up, UART_IER, up->ier);
284 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
285 serial_dl_write(up, priv->quot);
287 serial_out(up, UART_EFR, priv->efr);
289 /* Configure flow control */
290 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
291 serial_out(up, UART_XON1, priv->xon);
292 serial_out(up, UART_XOFF1, priv->xoff);
294 serial_out(up, UART_LCR, up->lcr);
296 omap8250_update_mdr1(up, priv);
298 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
302 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
303 * some differences in how we want to handle flow control.
305 static void omap_8250_set_termios(struct uart_port *port,
306 struct ktermios *termios,
307 struct ktermios *old)
309 struct uart_8250_port *up = up_to_u8250p(port);
310 struct omap8250_priv *priv = up->port.private_data;
311 unsigned char cval = 0;
314 switch (termios->c_cflag & CSIZE) {
316 cval = UART_LCR_WLEN5;
319 cval = UART_LCR_WLEN6;
322 cval = UART_LCR_WLEN7;
326 cval = UART_LCR_WLEN8;
330 if (termios->c_cflag & CSTOPB)
331 cval |= UART_LCR_STOP;
332 if (termios->c_cflag & PARENB)
333 cval |= UART_LCR_PARITY;
334 if (!(termios->c_cflag & PARODD))
335 cval |= UART_LCR_EPAR;
336 if (termios->c_cflag & CMSPAR)
337 cval |= UART_LCR_SPAR;
340 * Ask the core to calculate the divisor for us.
342 baud = uart_get_baud_rate(port, termios, old,
343 port->uartclk / 16 / UART_DIV_MAX,
345 omap_8250_get_divisor(port, baud, priv);
348 * Ok, we're now changing the port state. Do it with
349 * interrupts disabled.
351 pm_runtime_get_sync(port->dev);
352 spin_lock_irq(&port->lock);
355 * Update the per-port timeout.
357 uart_update_timeout(port, termios->c_cflag, baud);
359 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
360 if (termios->c_iflag & INPCK)
361 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
362 if (termios->c_iflag & (IGNBRK | PARMRK))
363 up->port.read_status_mask |= UART_LSR_BI;
366 * Characters to ignore
368 up->port.ignore_status_mask = 0;
369 if (termios->c_iflag & IGNPAR)
370 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
371 if (termios->c_iflag & IGNBRK) {
372 up->port.ignore_status_mask |= UART_LSR_BI;
374 * If we're ignoring parity and break indicators,
375 * ignore overruns too (for real raw support).
377 if (termios->c_iflag & IGNPAR)
378 up->port.ignore_status_mask |= UART_LSR_OE;
382 * ignore all characters if CREAD is not set
384 if ((termios->c_cflag & CREAD) == 0)
385 up->port.ignore_status_mask |= UART_LSR_DR;
388 * Modem status interrupts
390 up->ier &= ~UART_IER_MSI;
391 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
392 up->ier |= UART_IER_MSI;
395 /* Up to here it was mostly serial8250_do_set_termios() */
398 * We enable TRIG_GRANU for RX and TX and additionally we set
399 * SCR_TX_EMPTY bit. The result is the following:
400 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
401 * - less than RX_TRIGGER number of bytes will also cause an interrupt
402 * once the UART decides that there no new bytes arriving.
403 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
404 * empty - the trigger level is ignored here.
406 * Once DMA is enabled:
407 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
408 * bytes in the TX FIFO. On each assert the DMA engine will move
409 * TX_TRIGGER bytes into the FIFO.
410 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
411 * the FIFO and move RX_TRIGGER bytes.
412 * This is because threshold and trigger values are the same.
414 up->fcr = UART_FCR_ENABLE_FIFO;
415 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
416 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
418 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
419 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
422 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
423 OMAP_UART_SCR_DMAMODE_CTL;
425 priv->xon = termios->c_cc[VSTART];
426 priv->xoff = termios->c_cc[VSTOP];
429 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
431 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
432 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
433 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
434 priv->efr |= UART_EFR_CTS;
435 } else if (up->port.flags & UPF_SOFT_FLOW) {
437 * OMAP rx s/w flow control is borked; the transmitter remains
438 * stuck off even if rx flow control is subsequently disabled
443 * Enable XON/XOFF flow control on output.
444 * Transmit XON1, XOFF1
446 if (termios->c_iflag & IXOFF) {
447 up->port.status |= UPSTAT_AUTOXOFF;
448 priv->efr |= OMAP_UART_SW_TX;
451 omap8250_restore_regs(up);
453 spin_unlock_irq(&up->port.lock);
454 pm_runtime_mark_last_busy(port->dev);
455 pm_runtime_put_autosuspend(port->dev);
457 /* calculate wakeup latency constraint */
458 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
459 priv->latency = priv->calc_latency;
461 schedule_work(&priv->qos_work);
463 /* Don't rewrite B0 */
464 if (tty_termios_baud_rate(termios))
465 tty_termios_encode_baud_rate(termios, baud, baud);
468 /* same as 8250 except that we may have extra flow bits set in EFR */
469 static void omap_8250_pm(struct uart_port *port, unsigned int state,
470 unsigned int oldstate)
472 struct uart_8250_port *up = up_to_u8250p(port);
475 pm_runtime_get_sync(port->dev);
476 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
477 efr = serial_in(up, UART_EFR);
478 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
479 serial_out(up, UART_LCR, 0);
481 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
482 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
483 serial_out(up, UART_EFR, efr);
484 serial_out(up, UART_LCR, 0);
486 pm_runtime_mark_last_busy(port->dev);
487 pm_runtime_put_autosuspend(port->dev);
490 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
491 struct omap8250_priv *priv)
494 u16 revision, major, minor;
496 mvr = uart_read(up, UART_OMAP_MVER);
498 /* Check revision register scheme */
499 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
502 case 0: /* Legacy Scheme: OMAP2/3 */
503 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
504 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
505 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
506 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
509 /* New Scheme: OMAP4+ */
510 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
511 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
512 OMAP_UART_MVR_MAJ_SHIFT;
513 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
516 dev_warn(up->port.dev,
517 "Unknown revision, defaulting to highest\n");
518 /* highest possible revision */
522 /* normalize revision for the driver */
523 revision = UART_BUILD_REVISION(major, minor);
526 case OMAP_UART_REV_46:
527 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
529 case OMAP_UART_REV_52:
530 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
531 OMAP_UART_WER_HAS_TX_WAKEUP;
533 case OMAP_UART_REV_63:
534 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
535 OMAP_UART_WER_HAS_TX_WAKEUP;
542 static void omap8250_uart_qos_work(struct work_struct *work)
544 struct omap8250_priv *priv;
546 priv = container_of(work, struct omap8250_priv, qos_work);
547 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
550 #ifdef CONFIG_SERIAL_8250_DMA
551 static int omap_8250_dma_handle_irq(struct uart_port *port);
554 static irqreturn_t omap8250_irq(int irq, void *dev_id)
556 struct uart_port *port = dev_id;
557 struct uart_8250_port *up = up_to_u8250p(port);
561 #ifdef CONFIG_SERIAL_8250_DMA
563 ret = omap_8250_dma_handle_irq(port);
564 return IRQ_RETVAL(ret);
568 serial8250_rpm_get(up);
569 iir = serial_port_in(port, UART_IIR);
570 ret = serial8250_handle_irq(port, iir);
571 serial8250_rpm_put(up);
573 return IRQ_RETVAL(ret);
576 static int omap_8250_startup(struct uart_port *port)
578 struct uart_8250_port *up = up_to_u8250p(port);
579 struct omap8250_priv *priv = port->private_data;
583 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
588 pm_runtime_get_sync(port->dev);
590 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
592 serial_out(up, UART_LCR, UART_LCR_WLEN8);
594 up->lsr_saved_flags = 0;
595 up->msr_saved_flags = 0;
597 /* Disable DMA for console UART */
598 if (uart_console(port))
602 ret = serial8250_request_dma(up);
604 dev_warn_ratelimited(port->dev,
605 "failed to request DMA\n");
610 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
611 dev_name(port->dev), port);
615 up->ier = UART_IER_RLSI | UART_IER_RDI;
616 serial_out(up, UART_IER, up->ier);
619 up->capabilities |= UART_CAP_RPM;
622 /* Enable module level wake up */
623 priv->wer = OMAP_UART_WER_MOD_WKUP;
624 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
625 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
626 serial_out(up, UART_OMAP_WER, priv->wer);
631 pm_runtime_mark_last_busy(port->dev);
632 pm_runtime_put_autosuspend(port->dev);
635 pm_runtime_mark_last_busy(port->dev);
636 pm_runtime_put_autosuspend(port->dev);
637 dev_pm_clear_wake_irq(port->dev);
641 static void omap_8250_shutdown(struct uart_port *port)
643 struct uart_8250_port *up = up_to_u8250p(port);
644 struct omap8250_priv *priv = port->private_data;
646 flush_work(&priv->qos_work);
648 omap_8250_rx_dma_flush(up);
650 pm_runtime_get_sync(port->dev);
652 serial_out(up, UART_OMAP_WER, 0);
655 serial_out(up, UART_IER, 0);
658 serial8250_release_dma(up);
661 * Disable break condition and FIFOs
663 if (up->lcr & UART_LCR_SBC)
664 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
665 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
667 pm_runtime_mark_last_busy(port->dev);
668 pm_runtime_put_autosuspend(port->dev);
669 free_irq(port->irq, port);
670 dev_pm_clear_wake_irq(port->dev);
673 static void omap_8250_throttle(struct uart_port *port)
675 struct omap8250_priv *priv = port->private_data;
676 struct uart_8250_port *up = up_to_u8250p(port);
679 pm_runtime_get_sync(port->dev);
681 spin_lock_irqsave(&port->lock, flags);
682 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
683 serial_out(up, UART_IER, up->ier);
684 priv->throttled = true;
685 spin_unlock_irqrestore(&port->lock, flags);
687 pm_runtime_mark_last_busy(port->dev);
688 pm_runtime_put_autosuspend(port->dev);
691 static int omap_8250_rs485_config(struct uart_port *port,
692 struct serial_rs485 *rs485)
694 struct uart_8250_port *up = up_to_u8250p(port);
696 /* Clamp the delays to [0, 100ms] */
697 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
698 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
700 port->rs485 = *rs485;
703 * Both serial8250_em485_init and serial8250_em485_destroy
706 if (rs485->flags & SER_RS485_ENABLED) {
707 int ret = serial8250_em485_init(up);
710 rs485->flags &= ~SER_RS485_ENABLED;
711 port->rs485.flags &= ~SER_RS485_ENABLED;
716 serial8250_em485_destroy(up);
721 static void omap_8250_unthrottle(struct uart_port *port)
723 struct omap8250_priv *priv = port->private_data;
724 struct uart_8250_port *up = up_to_u8250p(port);
727 pm_runtime_get_sync(port->dev);
729 spin_lock_irqsave(&port->lock, flags);
730 priv->throttled = false;
733 up->ier |= UART_IER_RLSI | UART_IER_RDI;
734 serial_out(up, UART_IER, up->ier);
735 spin_unlock_irqrestore(&port->lock, flags);
737 pm_runtime_mark_last_busy(port->dev);
738 pm_runtime_put_autosuspend(port->dev);
741 #ifdef CONFIG_SERIAL_8250_DMA
742 static int omap_8250_rx_dma(struct uart_8250_port *p);
744 static void __dma_rx_do_complete(struct uart_8250_port *p)
746 struct omap8250_priv *priv = p->port.private_data;
747 struct uart_8250_dma *dma = p->dma;
748 struct tty_port *tty_port = &p->port.state->port;
749 struct dma_tx_state state;
754 spin_lock_irqsave(&priv->rx_dma_lock, flags);
756 if (!dma->rx_running)
760 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
762 count = dma->rx_size - state.residue;
763 if (count < dma->rx_size)
764 dmaengine_terminate_async(dma->rxchan);
767 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
769 p->port.icount.rx += ret;
770 p->port.icount.buf_overrun += count - ret;
772 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
774 tty_flip_buffer_push(tty_port);
777 static void __dma_rx_complete(void *param)
779 struct uart_8250_port *p = param;
780 struct omap8250_priv *priv = p->port.private_data;
781 struct uart_8250_dma *dma = p->dma;
782 struct dma_tx_state state;
785 spin_lock_irqsave(&p->port.lock, flags);
788 * If the tx status is not DMA_COMPLETE, then this is a delayed
789 * completion callback. A previous RX timeout flush would have
790 * already pushed the data, so exit.
792 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
794 spin_unlock_irqrestore(&p->port.lock, flags);
797 __dma_rx_do_complete(p);
798 if (!priv->throttled)
801 spin_unlock_irqrestore(&p->port.lock, flags);
804 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
806 struct omap8250_priv *priv = p->port.private_data;
807 struct uart_8250_dma *dma = p->dma;
808 struct dma_tx_state state;
812 spin_lock_irqsave(&priv->rx_dma_lock, flags);
814 if (!dma->rx_running) {
815 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
819 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
820 if (ret == DMA_IN_PROGRESS) {
821 ret = dmaengine_pause(dma->rxchan);
822 if (WARN_ON_ONCE(ret))
823 priv->rx_dma_broken = true;
825 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
827 __dma_rx_do_complete(p);
830 static int omap_8250_rx_dma(struct uart_8250_port *p)
832 struct omap8250_priv *priv = p->port.private_data;
833 struct uart_8250_dma *dma = p->dma;
835 struct dma_async_tx_descriptor *desc;
838 if (priv->rx_dma_broken)
841 spin_lock_irqsave(&priv->rx_dma_lock, flags);
846 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
847 dma->rx_size, DMA_DEV_TO_MEM,
848 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
855 desc->callback = __dma_rx_complete;
856 desc->callback_param = p;
858 dma->rx_cookie = dmaengine_submit(desc);
860 dma_async_issue_pending(dma->rxchan);
862 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
866 static int omap_8250_tx_dma(struct uart_8250_port *p);
868 static void omap_8250_dma_tx_complete(void *param)
870 struct uart_8250_port *p = param;
871 struct uart_8250_dma *dma = p->dma;
872 struct circ_buf *xmit = &p->port.state->xmit;
874 bool en_thri = false;
875 struct omap8250_priv *priv = p->port.private_data;
877 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
878 UART_XMIT_SIZE, DMA_TO_DEVICE);
880 spin_lock_irqsave(&p->port.lock, flags);
884 xmit->tail += dma->tx_size;
885 xmit->tail &= UART_XMIT_SIZE - 1;
886 p->port.icount.tx += dma->tx_size;
888 if (priv->delayed_restore) {
889 priv->delayed_restore = 0;
890 omap8250_restore_regs(p);
893 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
894 uart_write_wakeup(&p->port);
896 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
899 ret = omap_8250_tx_dma(p);
903 } else if (p->capabilities & UART_CAP_RPM) {
909 p->ier |= UART_IER_THRI;
910 serial_port_out(&p->port, UART_IER, p->ier);
913 spin_unlock_irqrestore(&p->port.lock, flags);
916 static int omap_8250_tx_dma(struct uart_8250_port *p)
918 struct uart_8250_dma *dma = p->dma;
919 struct omap8250_priv *priv = p->port.private_data;
920 struct circ_buf *xmit = &p->port.state->xmit;
921 struct dma_async_tx_descriptor *desc;
922 unsigned int skip_byte = 0;
927 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
930 * Even if no data, we need to return an error for the two cases
931 * below so serial8250_tx_chars() is invoked and properly clears
932 * THRI and/or runtime suspend.
934 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
938 if (p->ier & UART_IER_THRI) {
939 p->ier &= ~UART_IER_THRI;
940 serial_out(p, UART_IER, p->ier);
945 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
946 if (priv->habit & OMAP_DMA_TX_KICK) {
950 * We need to put the first byte into the FIFO in order to start
951 * the DMA transfer. For transfers smaller than four bytes we
952 * don't bother doing DMA at all. It seem not matter if there
953 * are still bytes in the FIFO from the last transfer (in case
954 * we got here directly from omap_8250_dma_tx_complete()). Bytes
955 * leaving the FIFO seem not to trigger the DMA transfer. It is
956 * really the byte that we put into the FIFO.
957 * If the FIFO is already full then we most likely got here from
958 * omap_8250_dma_tx_complete(). And this means the DMA engine
959 * just completed its work. We don't have to wait the complete
960 * 86us at 115200,8n1 but around 60us (not to mention lower
961 * baudrates). So in that case we take the interrupt and try
962 * again with an empty FIFO.
964 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
965 if (tx_lvl == p->tx_loadsz) {
969 if (dma->tx_size < 4) {
976 desc = dmaengine_prep_slave_single(dma->txchan,
977 dma->tx_addr + xmit->tail + skip_byte,
978 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
979 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
987 desc->callback = omap_8250_dma_tx_complete;
988 desc->callback_param = p;
990 dma->tx_cookie = dmaengine_submit(desc);
992 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
993 UART_XMIT_SIZE, DMA_TO_DEVICE);
995 dma_async_issue_pending(dma->txchan);
999 if (p->ier & UART_IER_THRI) {
1000 p->ier &= ~UART_IER_THRI;
1001 serial_out(p, UART_IER, p->ier);
1004 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1011 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1013 switch (iir & 0x3f) {
1015 case UART_IIR_RX_TIMEOUT:
1017 omap_8250_rx_dma_flush(up);
1020 return omap_8250_rx_dma(up);
1024 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1025 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1026 * use the default routine in the non-DMA case and this one for with DMA.
1028 static int omap_8250_dma_handle_irq(struct uart_port *port)
1030 struct uart_8250_port *up = up_to_u8250p(port);
1031 unsigned char status;
1032 unsigned long flags;
1035 serial8250_rpm_get(up);
1037 iir = serial_port_in(port, UART_IIR);
1038 if (iir & UART_IIR_NO_INT) {
1039 serial8250_rpm_put(up);
1043 spin_lock_irqsave(&port->lock, flags);
1045 status = serial_port_in(port, UART_LSR);
1047 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1048 if (handle_rx_dma(up, iir)) {
1049 status = serial8250_rx_chars(up, status);
1050 omap_8250_rx_dma(up);
1053 serial8250_modem_status(up);
1054 if (status & UART_LSR_THRE && up->dma->tx_err) {
1055 if (uart_tx_stopped(&up->port) ||
1056 uart_circ_empty(&up->port.state->xmit)) {
1057 up->dma->tx_err = 0;
1058 serial8250_tx_chars(up);
1061 * try again due to an earlier failer which
1062 * might have been resolved by now.
1064 if (omap_8250_tx_dma(up))
1065 serial8250_tx_chars(up);
1069 spin_unlock_irqrestore(&port->lock, flags);
1070 serial8250_rpm_put(up);
1074 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1081 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1087 static int omap8250_no_handle_irq(struct uart_port *port)
1089 /* IRQ has not been requested but handling irq? */
1090 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1094 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1095 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1096 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1098 static const struct of_device_id omap8250_dt_ids[] = {
1099 { .compatible = "ti,am654-uart" },
1100 { .compatible = "ti,omap2-uart" },
1101 { .compatible = "ti,omap3-uart" },
1102 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1103 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1104 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1105 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1108 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1110 static int omap8250_probe(struct platform_device *pdev)
1112 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1113 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1114 struct omap8250_priv *priv;
1115 struct uart_8250_port up;
1117 void __iomem *membase;
1119 if (!regs || !irq) {
1120 dev_err(&pdev->dev, "missing registers or irq\n");
1124 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1128 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1129 resource_size(regs));
1133 memset(&up, 0, sizeof(up));
1134 up.port.dev = &pdev->dev;
1135 up.port.mapbase = regs->start;
1136 up.port.membase = membase;
1137 up.port.irq = irq->start;
1139 * It claims to be 16C750 compatible however it is a little different.
1140 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1141 * have) is enabled via EFR instead of MCR. The type is set here 8250
1142 * just to get things going. UNKNOWN does not work for a few reasons and
1143 * we don't need our own type since we don't use 8250's set_termios()
1146 up.port.type = PORT_8250;
1147 up.port.iotype = UPIO_MEM;
1148 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1150 up.port.private_data = priv;
1152 up.port.regshift = 2;
1153 up.port.fifosize = 64;
1155 up.capabilities = UART_CAP_FIFO;
1158 * Runtime PM is mostly transparent. However to do it right we need to a
1159 * TX empty interrupt before we can put the device to auto idle. So if
1160 * PM is not enabled we don't add that flag and can spare that one extra
1161 * interrupt in the TX path.
1163 up.capabilities |= UART_CAP_RPM;
1165 up.port.set_termios = omap_8250_set_termios;
1166 up.port.set_mctrl = omap8250_set_mctrl;
1167 up.port.pm = omap_8250_pm;
1168 up.port.startup = omap_8250_startup;
1169 up.port.shutdown = omap_8250_shutdown;
1170 up.port.throttle = omap_8250_throttle;
1171 up.port.unthrottle = omap_8250_unthrottle;
1172 up.port.rs485_config = omap_8250_rs485_config;
1174 if (pdev->dev.of_node) {
1175 const struct of_device_id *id;
1177 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1179 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1181 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1183 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1185 priv->habit |= *(u8 *)id->data;
1190 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1195 if (!up.port.uartclk) {
1196 up.port.uartclk = DEFAULT_CLK_SPEED;
1197 dev_warn(&pdev->dev,
1198 "No clock speed specified: using default: %d\n",
1202 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1203 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1204 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1206 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1208 spin_lock_init(&priv->rx_dma_lock);
1210 device_init_wakeup(&pdev->dev, true);
1211 pm_runtime_enable(&pdev->dev);
1212 pm_runtime_use_autosuspend(&pdev->dev);
1213 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1215 pm_runtime_irq_safe(&pdev->dev);
1217 pm_runtime_get_sync(&pdev->dev);
1219 omap_serial_fill_features_erratas(&up, priv);
1220 up.port.handle_irq = omap8250_no_handle_irq;
1221 #ifdef CONFIG_SERIAL_8250_DMA
1222 if (pdev->dev.of_node) {
1224 * Oh DMA support. If there are no DMA properties in the DT then
1225 * we will fall back to a generic DMA channel which does not
1226 * really work here. To ensure that we do not get a generic DMA
1227 * channel assigned, we have the the_no_dma_filter_fn() here.
1228 * To avoid "failed to request DMA" messages we check for DMA
1231 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1233 up.dma = &priv->omap8250_dma;
1234 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1235 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1236 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1237 priv->omap8250_dma.rx_size = RX_TRIGGER;
1238 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1239 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1243 ret = serial8250_register_8250_port(&up);
1245 dev_err(&pdev->dev, "unable to register 8250 port\n");
1249 platform_set_drvdata(pdev, priv);
1250 pm_runtime_mark_last_busy(&pdev->dev);
1251 pm_runtime_put_autosuspend(&pdev->dev);
1254 pm_runtime_dont_use_autosuspend(&pdev->dev);
1255 pm_runtime_put_sync(&pdev->dev);
1256 pm_runtime_disable(&pdev->dev);
1260 static int omap8250_remove(struct platform_device *pdev)
1262 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1264 pm_runtime_dont_use_autosuspend(&pdev->dev);
1265 pm_runtime_put_sync(&pdev->dev);
1266 flush_work(&priv->qos_work);
1267 pm_runtime_disable(&pdev->dev);
1268 serial8250_unregister_port(priv->line);
1269 pm_qos_remove_request(&priv->pm_qos_request);
1270 device_init_wakeup(&pdev->dev, false);
1274 #ifdef CONFIG_PM_SLEEP
1275 static int omap8250_prepare(struct device *dev)
1277 struct omap8250_priv *priv = dev_get_drvdata(dev);
1281 priv->is_suspending = true;
1285 static void omap8250_complete(struct device *dev)
1287 struct omap8250_priv *priv = dev_get_drvdata(dev);
1291 priv->is_suspending = false;
1294 static int omap8250_suspend(struct device *dev)
1296 struct omap8250_priv *priv = dev_get_drvdata(dev);
1297 struct uart_8250_port *up = serial8250_get_port(priv->line);
1299 serial8250_suspend_port(priv->line);
1301 pm_runtime_get_sync(dev);
1302 if (!device_may_wakeup(dev))
1304 serial_out(up, UART_OMAP_WER, priv->wer);
1305 pm_runtime_mark_last_busy(dev);
1306 pm_runtime_put_autosuspend(dev);
1308 flush_work(&priv->qos_work);
1312 static int omap8250_resume(struct device *dev)
1314 struct omap8250_priv *priv = dev_get_drvdata(dev);
1316 serial8250_resume_port(priv->line);
1320 #define omap8250_prepare NULL
1321 #define omap8250_complete NULL
1325 static int omap8250_lost_context(struct uart_8250_port *up)
1329 val = serial_in(up, UART_OMAP_SCR);
1331 * If we lose context, then SCR is set to its reset value of zero.
1332 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1333 * among other bits, to never set the register back to zero again.
1340 /* TODO: in future, this should happen via API in drivers/reset/ */
1341 static int omap8250_soft_reset(struct device *dev)
1343 struct omap8250_priv *priv = dev_get_drvdata(dev);
1344 struct uart_8250_port *up = serial8250_get_port(priv->line);
1350 * At least on omap4, unused uarts may not idle after reset without
1351 * a basic scr dma configuration even with no dma in use. The
1352 * module clkctrl status bits will be 1 instead of 3 blocking idle
1353 * for the whole clockdomain. The softreset below will clear scr,
1354 * and we restore it on resume so this is safe to do on all SoCs
1355 * needing omap8250_soft_reset() quirk. Do it in two writes as
1356 * recommended in the comment for omap8250_update_scr().
1358 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1359 serial_out(up, UART_OMAP_SCR,
1360 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1362 sysc = serial_in(up, UART_OMAP_SYSC);
1364 /* softreset the UART */
1365 sysc |= OMAP_UART_SYSC_SOFTRESET;
1366 serial_out(up, UART_OMAP_SYSC, sysc);
1368 /* By experiments, 1us enough for reset complete on AM335x */
1371 syss = serial_in(up, UART_OMAP_SYSS);
1372 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1375 dev_err(dev, "timed out waiting for reset done\n");
1382 static int omap8250_runtime_suspend(struct device *dev)
1384 struct omap8250_priv *priv = dev_get_drvdata(dev);
1385 struct uart_8250_port *up;
1387 /* In case runtime-pm tries this before we are setup */
1391 up = serial8250_get_port(priv->line);
1393 * When using 'no_console_suspend', the console UART must not be
1394 * suspended. Since driver suspend is managed by runtime suspend,
1395 * preventing runtime suspend (by returning error) will keep device
1396 * active during suspend.
1398 if (priv->is_suspending && !console_suspend_enabled) {
1399 if (uart_console(&up->port))
1403 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1406 ret = omap8250_soft_reset(dev);
1410 /* Restore to UART mode after reset (for wakeup) */
1411 omap8250_update_mdr1(up, priv);
1412 /* Restore wakeup enable register */
1413 serial_out(up, UART_OMAP_WER, priv->wer);
1416 if (up->dma && up->dma->rxchan)
1417 omap_8250_rx_dma_flush(up);
1419 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1420 schedule_work(&priv->qos_work);
1425 static int omap8250_runtime_resume(struct device *dev)
1427 struct omap8250_priv *priv = dev_get_drvdata(dev);
1428 struct uart_8250_port *up;
1430 /* In case runtime-pm tries this before we are setup */
1434 up = serial8250_get_port(priv->line);
1436 if (omap8250_lost_context(up))
1437 omap8250_restore_regs(up);
1439 if (up->dma && up->dma->rxchan)
1440 omap_8250_rx_dma(up);
1442 priv->latency = priv->calc_latency;
1443 schedule_work(&priv->qos_work);
1448 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1449 static int __init omap8250_console_fixup(void)
1455 if (strstr(boot_command_line, "console=ttyS"))
1456 /* user set a ttyS based name for the console */
1459 omap_str = strstr(boot_command_line, "console=ttyO");
1461 /* user did not set ttyO based console, so we don't care */
1465 if ('0' <= *omap_str && *omap_str <= '9')
1466 idx = *omap_str - '0';
1471 if (omap_str[0] == ',') {
1478 add_preferred_console("ttyS", idx, options);
1479 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1481 pr_err("This ensures that you still see kernel messages. Please\n");
1482 pr_err("update your kernel commandline.\n");
1485 console_initcall(omap8250_console_fixup);
1488 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1489 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1490 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1491 omap8250_runtime_resume, NULL)
1492 .prepare = omap8250_prepare,
1493 .complete = omap8250_complete,
1496 static struct platform_driver omap8250_platform_driver = {
1499 .pm = &omap8250_dev_pm_ops,
1500 .of_match_table = omap8250_dt_ids,
1502 .probe = omap8250_probe,
1503 .remove = omap8250_remove,
1505 module_platform_driver(omap8250_platform_driver);
1507 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1508 MODULE_DESCRIPTION("OMAP 8250 Driver");
1509 MODULE_LICENSE("GPL v2");