2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_irq.h>
22 #include <linux/delay.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/console.h>
25 #include <linux/pm_qos.h>
26 #include <linux/pm_wakeirq.h>
27 #include <linux/dma-mapping.h>
31 #define DEFAULT_CLK_SPEED 48000000
33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
35 #define OMAP_DMA_TX_KICK (1 << 2)
37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
38 * The same errata is applicable to AM335x and DRA7x processors too.
40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
42 #define OMAP_UART_FCR_RX_TRIG 6
43 #define OMAP_UART_FCR_TX_TRIG 4
45 /* SCR register bitmasks */
46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
53 /* MVR register bitmasks */
54 #define OMAP_UART_MVR_SCHEME_SHIFT 30
55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
58 #define OMAP_UART_MVR_MAJ_MASK 0x700
59 #define OMAP_UART_MVR_MAJ_SHIFT 8
60 #define OMAP_UART_MVR_MIN_MASK 0x3f
62 /* SYSC register bitmasks */
63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
65 /* SYSS register bitmasks */
66 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
68 #define UART_TI752_TLR_TX 0
69 #define UART_TI752_TLR_RX 4
71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
72 #define TRIGGER_FCR_MASK(x) (x & 3)
74 /* Enable XON/XOFF flow control on output */
75 #define OMAP_UART_SW_TX 0x08
76 /* Enable XON/XOFF flow control on input */
77 #define OMAP_UART_SW_RX 0x02
79 #define OMAP_UART_WER_MOD_WKUP 0x7f
80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
90 #define OMAP_UART_REV_46 0x0406
91 #define OMAP_UART_REV_52 0x0502
92 #define OMAP_UART_REV_63 0x0603
94 struct omap8250_priv {
111 struct pm_qos_request pm_qos_request;
112 struct work_struct qos_work;
113 struct uart_8250_dma omap8250_dma;
114 spinlock_t rx_dma_lock;
118 static u32 uart_read(struct uart_8250_port *up, u32 reg)
120 return readl(up->port.membase + (reg << up->port.regshift));
123 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
125 struct uart_8250_port *up = up_to_u8250p(port);
126 struct omap8250_priv *priv = up->port.private_data;
129 serial8250_do_set_mctrl(port, mctrl);
132 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
135 lcr = serial_in(up, UART_LCR);
136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
137 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
138 priv->efr |= UART_EFR_RTS;
140 priv->efr &= ~UART_EFR_RTS;
141 serial_out(up, UART_EFR, priv->efr);
142 serial_out(up, UART_LCR, lcr);
146 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
147 * The access to uart register after MDR1 Access
148 * causes UART to corrupt data.
151 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
152 * give 10 times as much
154 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
155 struct omap8250_priv *priv)
159 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
161 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
162 UART_FCR_CLEAR_RCVR);
164 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
165 * TX_FIFO_E bit is 1.
167 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
168 (UART_LSR_THRE | UART_LSR_DR))) {
171 /* Should *never* happen. we warn and carry on */
172 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
173 serial_in(up, UART_LSR));
180 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
181 struct omap8250_priv *priv)
183 unsigned int uartclk = port->uartclk;
184 unsigned int div_13, div_16;
185 unsigned int abs_d13, abs_d16;
188 * Old custom speed handling.
190 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
191 priv->quot = port->custom_divisor & 0xffff;
193 * I assume that nobody is using this. But hey, if somebody
194 * would like to specify the divisor _and_ the mode then the
195 * driver is ready and waiting for it.
197 if (port->custom_divisor & (1 << 16))
198 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
200 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
203 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
204 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
211 abs_d13 = abs(baud - uartclk / 13 / div_13);
212 abs_d16 = abs(baud - uartclk / 16 / div_16);
214 if (abs_d13 >= abs_d16) {
215 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
218 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
223 static void omap8250_update_scr(struct uart_8250_port *up,
224 struct omap8250_priv *priv)
228 old_scr = serial_in(up, UART_OMAP_SCR);
229 if (old_scr == priv->scr)
233 * The manual recommends not to enable the DMA mode selector in the SCR
234 * (instead of the FCR) register _and_ selecting the DMA mode as one
235 * register write because this may lead to malfunction.
237 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
238 serial_out(up, UART_OMAP_SCR,
239 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
240 serial_out(up, UART_OMAP_SCR, priv->scr);
243 static void omap8250_update_mdr1(struct uart_8250_port *up,
244 struct omap8250_priv *priv)
246 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
247 omap_8250_mdr1_errataset(up, priv);
249 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
252 static void omap8250_restore_regs(struct uart_8250_port *up)
254 struct omap8250_priv *priv = up->port.private_data;
255 struct uart_8250_dma *dma = up->dma;
257 if (dma && dma->tx_running) {
259 * TCSANOW requests the change to occur immediately however if
260 * we have a TX-DMA operation in progress then it has been
261 * observed that it might stall and never complete. Therefore we
262 * delay DMA completes to prevent this hang from happen.
264 priv->delayed_restore = 1;
268 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
269 serial_out(up, UART_EFR, UART_EFR_ECB);
271 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
272 serial_out(up, UART_MCR, UART_MCR_TCRTLR);
273 serial_out(up, UART_FCR, up->fcr);
275 omap8250_update_scr(up, priv);
277 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
279 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
280 OMAP_UART_TCR_HALT(52));
281 serial_out(up, UART_TI752_TLR,
282 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
283 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
285 serial_out(up, UART_LCR, 0);
287 /* drop TCR + TLR access, we setup XON/XOFF later */
288 serial_out(up, UART_MCR, up->mcr);
289 serial_out(up, UART_IER, up->ier);
291 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
292 serial_dl_write(up, priv->quot);
294 serial_out(up, UART_EFR, priv->efr);
296 /* Configure flow control */
297 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
298 serial_out(up, UART_XON1, priv->xon);
299 serial_out(up, UART_XOFF1, priv->xoff);
301 serial_out(up, UART_LCR, up->lcr);
303 omap8250_update_mdr1(up, priv);
305 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
309 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
310 * some differences in how we want to handle flow control.
312 static void omap_8250_set_termios(struct uart_port *port,
313 struct ktermios *termios,
314 struct ktermios *old)
316 struct uart_8250_port *up =
317 container_of(port, struct uart_8250_port, port);
318 struct omap8250_priv *priv = up->port.private_data;
319 unsigned char cval = 0;
322 switch (termios->c_cflag & CSIZE) {
324 cval = UART_LCR_WLEN5;
327 cval = UART_LCR_WLEN6;
330 cval = UART_LCR_WLEN7;
334 cval = UART_LCR_WLEN8;
338 if (termios->c_cflag & CSTOPB)
339 cval |= UART_LCR_STOP;
340 if (termios->c_cflag & PARENB)
341 cval |= UART_LCR_PARITY;
342 if (!(termios->c_cflag & PARODD))
343 cval |= UART_LCR_EPAR;
344 if (termios->c_cflag & CMSPAR)
345 cval |= UART_LCR_SPAR;
348 * Ask the core to calculate the divisor for us.
350 baud = uart_get_baud_rate(port, termios, old,
351 port->uartclk / 16 / 0xffff,
353 omap_8250_get_divisor(port, baud, priv);
356 * Ok, we're now changing the port state. Do it with
357 * interrupts disabled.
359 pm_runtime_get_sync(port->dev);
360 spin_lock_irq(&port->lock);
363 * Update the per-port timeout.
365 uart_update_timeout(port, termios->c_cflag, baud);
367 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
368 if (termios->c_iflag & INPCK)
369 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
370 if (termios->c_iflag & (IGNBRK | PARMRK))
371 up->port.read_status_mask |= UART_LSR_BI;
374 * Characters to ignore
376 up->port.ignore_status_mask = 0;
377 if (termios->c_iflag & IGNPAR)
378 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
379 if (termios->c_iflag & IGNBRK) {
380 up->port.ignore_status_mask |= UART_LSR_BI;
382 * If we're ignoring parity and break indicators,
383 * ignore overruns too (for real raw support).
385 if (termios->c_iflag & IGNPAR)
386 up->port.ignore_status_mask |= UART_LSR_OE;
390 * ignore all characters if CREAD is not set
392 if ((termios->c_cflag & CREAD) == 0)
393 up->port.ignore_status_mask |= UART_LSR_DR;
396 * Modem status interrupts
398 up->ier &= ~UART_IER_MSI;
399 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
400 up->ier |= UART_IER_MSI;
403 /* Up to here it was mostly serial8250_do_set_termios() */
406 * We enable TRIG_GRANU for RX and TX and additionaly we set
407 * SCR_TX_EMPTY bit. The result is the following:
408 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
409 * - less than RX_TRIGGER number of bytes will also cause an interrupt
410 * once the UART decides that there no new bytes arriving.
411 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
412 * empty - the trigger level is ignored here.
414 * Once DMA is enabled:
415 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
416 * bytes in the TX FIFO. On each assert the DMA engine will move
417 * TX_TRIGGER bytes into the FIFO.
418 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
419 * the FIFO and move RX_TRIGGER bytes.
420 * This is because threshold and trigger values are the same.
422 up->fcr = UART_FCR_ENABLE_FIFO;
423 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
424 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
426 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
427 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
430 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
431 OMAP_UART_SCR_DMAMODE_CTL;
433 priv->xon = termios->c_cc[VSTART];
434 priv->xoff = termios->c_cc[VSTOP];
437 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
439 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
440 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
441 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
442 priv->efr |= UART_EFR_CTS;
443 } else if (up->port.flags & UPF_SOFT_FLOW) {
445 * OMAP rx s/w flow control is borked; the transmitter remains
446 * stuck off even if rx flow control is subsequently disabled
451 * Enable XON/XOFF flow control on output.
452 * Transmit XON1, XOFF1
454 if (termios->c_iflag & IXOFF) {
455 up->port.status |= UPSTAT_AUTOXOFF;
456 priv->efr |= OMAP_UART_SW_TX;
459 omap8250_restore_regs(up);
461 spin_unlock_irq(&up->port.lock);
462 pm_runtime_mark_last_busy(port->dev);
463 pm_runtime_put_autosuspend(port->dev);
465 /* calculate wakeup latency constraint */
466 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
467 priv->latency = priv->calc_latency;
469 schedule_work(&priv->qos_work);
471 /* Don't rewrite B0 */
472 if (tty_termios_baud_rate(termios))
473 tty_termios_encode_baud_rate(termios, baud, baud);
476 /* same as 8250 except that we may have extra flow bits set in EFR */
477 static void omap_8250_pm(struct uart_port *port, unsigned int state,
478 unsigned int oldstate)
480 struct uart_8250_port *up = up_to_u8250p(port);
483 pm_runtime_get_sync(port->dev);
484 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
485 efr = serial_in(up, UART_EFR);
486 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
487 serial_out(up, UART_LCR, 0);
489 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
490 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
491 serial_out(up, UART_EFR, efr);
492 serial_out(up, UART_LCR, 0);
494 pm_runtime_mark_last_busy(port->dev);
495 pm_runtime_put_autosuspend(port->dev);
498 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
499 struct omap8250_priv *priv)
502 u16 revision, major, minor;
504 mvr = uart_read(up, UART_OMAP_MVER);
506 /* Check revision register scheme */
507 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
510 case 0: /* Legacy Scheme: OMAP2/3 */
511 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
512 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
513 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
514 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
517 /* New Scheme: OMAP4+ */
518 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
519 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
520 OMAP_UART_MVR_MAJ_SHIFT;
521 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
524 dev_warn(up->port.dev,
525 "Unknown revision, defaulting to highest\n");
526 /* highest possible revision */
530 /* normalize revision for the driver */
531 revision = UART_BUILD_REVISION(major, minor);
534 case OMAP_UART_REV_46:
535 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
537 case OMAP_UART_REV_52:
538 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
539 OMAP_UART_WER_HAS_TX_WAKEUP;
541 case OMAP_UART_REV_63:
542 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
543 OMAP_UART_WER_HAS_TX_WAKEUP;
550 static void omap8250_uart_qos_work(struct work_struct *work)
552 struct omap8250_priv *priv;
554 priv = container_of(work, struct omap8250_priv, qos_work);
555 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
558 #ifdef CONFIG_SERIAL_8250_DMA
559 static int omap_8250_dma_handle_irq(struct uart_port *port);
562 static irqreturn_t omap8250_irq(int irq, void *dev_id)
564 struct uart_port *port = dev_id;
565 struct uart_8250_port *up = up_to_u8250p(port);
569 #ifdef CONFIG_SERIAL_8250_DMA
571 ret = omap_8250_dma_handle_irq(port);
572 return IRQ_RETVAL(ret);
576 serial8250_rpm_get(up);
577 iir = serial_port_in(port, UART_IIR);
578 ret = serial8250_handle_irq(port, iir);
579 serial8250_rpm_put(up);
581 return IRQ_RETVAL(ret);
584 static int omap_8250_startup(struct uart_port *port)
586 struct uart_8250_port *up = up_to_u8250p(port);
587 struct omap8250_priv *priv = port->private_data;
591 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
596 pm_runtime_get_sync(port->dev);
599 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
601 serial_out(up, UART_LCR, UART_LCR_WLEN8);
603 up->lsr_saved_flags = 0;
604 up->msr_saved_flags = 0;
606 /* Disable DMA for console UART */
607 if (uart_console(port))
611 ret = serial8250_request_dma(up);
613 dev_warn_ratelimited(port->dev,
614 "failed to request DMA\n");
619 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
620 dev_name(port->dev), port);
624 up->ier = UART_IER_RLSI | UART_IER_RDI;
625 serial_out(up, UART_IER, up->ier);
628 up->capabilities |= UART_CAP_RPM;
631 /* Enable module level wake up */
632 priv->wer = OMAP_UART_WER_MOD_WKUP;
633 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
634 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
635 serial_out(up, UART_OMAP_WER, priv->wer);
638 up->dma->rx_dma(up, 0);
640 pm_runtime_mark_last_busy(port->dev);
641 pm_runtime_put_autosuspend(port->dev);
644 pm_runtime_mark_last_busy(port->dev);
645 pm_runtime_put_autosuspend(port->dev);
646 dev_pm_clear_wake_irq(port->dev);
650 static void omap_8250_shutdown(struct uart_port *port)
652 struct uart_8250_port *up = up_to_u8250p(port);
653 struct omap8250_priv *priv = port->private_data;
655 flush_work(&priv->qos_work);
657 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT);
659 pm_runtime_get_sync(port->dev);
661 serial_out(up, UART_OMAP_WER, 0);
664 serial_out(up, UART_IER, 0);
667 serial8250_release_dma(up);
670 * Disable break condition and FIFOs
672 if (up->lcr & UART_LCR_SBC)
673 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
674 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
676 pm_runtime_mark_last_busy(port->dev);
677 pm_runtime_put_autosuspend(port->dev);
678 free_irq(port->irq, port);
679 dev_pm_clear_wake_irq(port->dev);
682 static void omap_8250_throttle(struct uart_port *port)
685 struct uart_8250_port *up =
686 container_of(port, struct uart_8250_port, port);
688 pm_runtime_get_sync(port->dev);
690 spin_lock_irqsave(&port->lock, flags);
691 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
692 serial_out(up, UART_IER, up->ier);
693 spin_unlock_irqrestore(&port->lock, flags);
695 pm_runtime_mark_last_busy(port->dev);
696 pm_runtime_put_autosuspend(port->dev);
699 static void omap_8250_unthrottle(struct uart_port *port)
702 struct uart_8250_port *up =
703 container_of(port, struct uart_8250_port, port);
705 pm_runtime_get_sync(port->dev);
707 spin_lock_irqsave(&port->lock, flags);
708 up->ier |= UART_IER_RLSI | UART_IER_RDI;
709 serial_out(up, UART_IER, up->ier);
710 spin_unlock_irqrestore(&port->lock, flags);
712 pm_runtime_mark_last_busy(port->dev);
713 pm_runtime_put_autosuspend(port->dev);
716 #ifdef CONFIG_SERIAL_8250_DMA
717 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
719 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
721 struct omap8250_priv *priv = p->port.private_data;
722 struct uart_8250_dma *dma = p->dma;
723 struct tty_port *tty_port = &p->port.state->port;
724 struct dma_tx_state state;
729 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
730 dma->rx_size, DMA_FROM_DEVICE);
732 spin_lock_irqsave(&priv->rx_dma_lock, flags);
734 if (!dma->rx_running)
738 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
739 dmaengine_terminate_all(dma->rxchan);
741 count = dma->rx_size - state.residue;
743 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
745 p->port.icount.rx += ret;
746 p->port.icount.buf_overrun += count - ret;
748 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
751 omap_8250_rx_dma(p, 0);
753 tty_flip_buffer_push(tty_port);
756 static void __dma_rx_complete(void *param)
758 __dma_rx_do_complete(param, false);
761 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
763 struct omap8250_priv *priv = p->port.private_data;
764 struct uart_8250_dma *dma = p->dma;
768 spin_lock_irqsave(&priv->rx_dma_lock, flags);
770 if (!dma->rx_running) {
771 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
775 ret = dmaengine_pause(dma->rxchan);
776 if (WARN_ON_ONCE(ret))
777 priv->rx_dma_broken = true;
779 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
781 __dma_rx_do_complete(p, true);
784 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
786 struct omap8250_priv *priv = p->port.private_data;
787 struct uart_8250_dma *dma = p->dma;
789 struct dma_async_tx_descriptor *desc;
792 switch (iir & 0x3f) {
794 /* 8250_core handles errors and break interrupts */
795 omap_8250_rx_dma_flush(p);
797 case UART_IIR_RX_TIMEOUT:
799 * If RCVR FIFO trigger level was not reached, complete the
800 * transfer and let 8250_core copy the remaining data.
802 omap_8250_rx_dma_flush(p);
806 * The OMAP UART is a special BEAST. If we receive RDI we _have_
807 * a DMA transfer programmed but it didn't work. One reason is
808 * that we were too slow and there were too many bytes in the
809 * FIFO, the UART counted wrong and never kicked the DMA engine
810 * to do anything. That means once we receive RDI on OMAP then
811 * the DMA won't do anything soon so we have to cancel the DMA
812 * transfer and purge the FIFO manually.
814 omap_8250_rx_dma_flush(p);
821 if (priv->rx_dma_broken)
824 spin_lock_irqsave(&priv->rx_dma_lock, flags);
829 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
830 dma->rx_size, DMA_DEV_TO_MEM,
831 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
838 desc->callback = __dma_rx_complete;
839 desc->callback_param = p;
841 dma->rx_cookie = dmaengine_submit(desc);
843 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
844 dma->rx_size, DMA_FROM_DEVICE);
846 dma_async_issue_pending(dma->rxchan);
848 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
852 static int omap_8250_tx_dma(struct uart_8250_port *p);
854 static void omap_8250_dma_tx_complete(void *param)
856 struct uart_8250_port *p = param;
857 struct uart_8250_dma *dma = p->dma;
858 struct circ_buf *xmit = &p->port.state->xmit;
860 bool en_thri = false;
861 struct omap8250_priv *priv = p->port.private_data;
863 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
864 UART_XMIT_SIZE, DMA_TO_DEVICE);
866 spin_lock_irqsave(&p->port.lock, flags);
870 xmit->tail += dma->tx_size;
871 xmit->tail &= UART_XMIT_SIZE - 1;
872 p->port.icount.tx += dma->tx_size;
874 if (priv->delayed_restore) {
875 priv->delayed_restore = 0;
876 omap8250_restore_regs(p);
879 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
880 uart_write_wakeup(&p->port);
882 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
885 ret = omap_8250_tx_dma(p);
889 } else if (p->capabilities & UART_CAP_RPM) {
895 p->ier |= UART_IER_THRI;
896 serial_port_out(&p->port, UART_IER, p->ier);
899 spin_unlock_irqrestore(&p->port.lock, flags);
902 static int omap_8250_tx_dma(struct uart_8250_port *p)
904 struct uart_8250_dma *dma = p->dma;
905 struct omap8250_priv *priv = p->port.private_data;
906 struct circ_buf *xmit = &p->port.state->xmit;
907 struct dma_async_tx_descriptor *desc;
908 unsigned int skip_byte = 0;
913 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
916 * Even if no data, we need to return an error for the two cases
917 * below so serial8250_tx_chars() is invoked and properly clears
918 * THRI and/or runtime suspend.
920 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
924 if (p->ier & UART_IER_THRI) {
925 p->ier &= ~UART_IER_THRI;
926 serial_out(p, UART_IER, p->ier);
931 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
932 if (priv->habit & OMAP_DMA_TX_KICK) {
936 * We need to put the first byte into the FIFO in order to start
937 * the DMA transfer. For transfers smaller than four bytes we
938 * don't bother doing DMA at all. It seem not matter if there
939 * are still bytes in the FIFO from the last transfer (in case
940 * we got here directly from omap_8250_dma_tx_complete()). Bytes
941 * leaving the FIFO seem not to trigger the DMA transfer. It is
942 * really the byte that we put into the FIFO.
943 * If the FIFO is already full then we most likely got here from
944 * omap_8250_dma_tx_complete(). And this means the DMA engine
945 * just completed its work. We don't have to wait the complete
946 * 86us at 115200,8n1 but around 60us (not to mention lower
947 * baudrates). So in that case we take the interrupt and try
948 * again with an empty FIFO.
950 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
951 if (tx_lvl == p->tx_loadsz) {
955 if (dma->tx_size < 4) {
962 desc = dmaengine_prep_slave_single(dma->txchan,
963 dma->tx_addr + xmit->tail + skip_byte,
964 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
965 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
973 desc->callback = omap_8250_dma_tx_complete;
974 desc->callback_param = p;
976 dma->tx_cookie = dmaengine_submit(desc);
978 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
979 UART_XMIT_SIZE, DMA_TO_DEVICE);
981 dma_async_issue_pending(dma->txchan);
985 if (p->ier & UART_IER_THRI) {
986 p->ier &= ~UART_IER_THRI;
987 serial_out(p, UART_IER, p->ier);
990 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
998 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
999 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1000 * use the default routine in the non-DMA case and this one for with DMA.
1002 static int omap_8250_dma_handle_irq(struct uart_port *port)
1004 struct uart_8250_port *up = up_to_u8250p(port);
1005 unsigned char status;
1006 unsigned long flags;
1010 serial8250_rpm_get(up);
1012 iir = serial_port_in(port, UART_IIR);
1013 if (iir & UART_IIR_NO_INT) {
1014 serial8250_rpm_put(up);
1018 spin_lock_irqsave(&port->lock, flags);
1020 status = serial_port_in(port, UART_LSR);
1022 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1024 dma_err = omap_8250_rx_dma(up, iir);
1026 status = serial8250_rx_chars(up, status);
1027 omap_8250_rx_dma(up, 0);
1030 serial8250_modem_status(up);
1031 if (status & UART_LSR_THRE && up->dma->tx_err) {
1032 if (uart_tx_stopped(&up->port) ||
1033 uart_circ_empty(&up->port.state->xmit)) {
1034 up->dma->tx_err = 0;
1035 serial8250_tx_chars(up);
1038 * try again due to an earlier failer which
1039 * might have been resolved by now.
1041 dma_err = omap_8250_tx_dma(up);
1043 serial8250_tx_chars(up);
1047 spin_unlock_irqrestore(&port->lock, flags);
1048 serial8250_rpm_put(up);
1052 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1059 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
1065 static int omap8250_no_handle_irq(struct uart_port *port)
1067 /* IRQ has not been requested but handling irq? */
1068 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1072 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1073 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
1075 static const struct of_device_id omap8250_dt_ids[] = {
1076 { .compatible = "ti,omap2-uart" },
1077 { .compatible = "ti,omap3-uart" },
1078 { .compatible = "ti,omap4-uart" },
1079 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1080 { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
1081 { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
1084 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1086 static int omap8250_probe(struct platform_device *pdev)
1088 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1090 struct omap8250_priv *priv;
1091 struct uart_8250_port up;
1093 void __iomem *membase;
1095 if (!regs || !irq) {
1096 dev_err(&pdev->dev, "missing registers or irq\n");
1100 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1104 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1105 resource_size(regs));
1109 memset(&up, 0, sizeof(up));
1110 up.port.dev = &pdev->dev;
1111 up.port.mapbase = regs->start;
1112 up.port.membase = membase;
1113 up.port.irq = irq->start;
1115 * It claims to be 16C750 compatible however it is a little different.
1116 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1117 * have) is enabled via EFR instead of MCR. The type is set here 8250
1118 * just to get things going. UNKNOWN does not work for a few reasons and
1119 * we don't need our own type since we don't use 8250's set_termios()
1122 up.port.type = PORT_8250;
1123 up.port.iotype = UPIO_MEM;
1124 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1126 up.port.private_data = priv;
1128 up.port.regshift = 2;
1129 up.port.fifosize = 64;
1131 up.capabilities = UART_CAP_FIFO;
1134 * Runtime PM is mostly transparent. However to do it right we need to a
1135 * TX empty interrupt before we can put the device to auto idle. So if
1136 * PM is not enabled we don't add that flag and can spare that one extra
1137 * interrupt in the TX path.
1139 up.capabilities |= UART_CAP_RPM;
1141 up.port.set_termios = omap_8250_set_termios;
1142 up.port.set_mctrl = omap8250_set_mctrl;
1143 up.port.pm = omap_8250_pm;
1144 up.port.startup = omap_8250_startup;
1145 up.port.shutdown = omap_8250_shutdown;
1146 up.port.throttle = omap_8250_throttle;
1147 up.port.unthrottle = omap_8250_unthrottle;
1149 if (pdev->dev.of_node) {
1150 const struct of_device_id *id;
1152 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1154 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1156 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1158 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1160 priv->habit |= *(u8 *)id->data;
1165 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1170 if (!up.port.uartclk) {
1171 up.port.uartclk = DEFAULT_CLK_SPEED;
1172 dev_warn(&pdev->dev,
1173 "No clock speed specified: using default: %d\n",
1177 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1178 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1179 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1181 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1183 spin_lock_init(&priv->rx_dma_lock);
1185 device_init_wakeup(&pdev->dev, true);
1186 pm_runtime_enable(&pdev->dev);
1187 pm_runtime_use_autosuspend(&pdev->dev);
1188 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1190 pm_runtime_irq_safe(&pdev->dev);
1192 pm_runtime_get_sync(&pdev->dev);
1194 omap_serial_fill_features_erratas(&up, priv);
1195 up.port.handle_irq = omap8250_no_handle_irq;
1196 #ifdef CONFIG_SERIAL_8250_DMA
1197 if (pdev->dev.of_node) {
1199 * Oh DMA support. If there are no DMA properties in the DT then
1200 * we will fall back to a generic DMA channel which does not
1201 * really work here. To ensure that we do not get a generic DMA
1202 * channel assigned, we have the the_no_dma_filter_fn() here.
1203 * To avoid "failed to request DMA" messages we check for DMA
1206 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1208 up.dma = &priv->omap8250_dma;
1209 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1210 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1211 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1212 priv->omap8250_dma.rx_size = RX_TRIGGER;
1213 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1214 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1216 if (of_machine_is_compatible("ti,am33xx"))
1217 priv->habit |= OMAP_DMA_TX_KICK;
1219 * pause is currently not supported atleast on omap-sdma
1220 * and edma on most earlier kernels.
1222 priv->rx_dma_broken = true;
1226 ret = serial8250_register_8250_port(&up);
1228 dev_err(&pdev->dev, "unable to register 8250 port\n");
1232 platform_set_drvdata(pdev, priv);
1233 pm_runtime_mark_last_busy(&pdev->dev);
1234 pm_runtime_put_autosuspend(&pdev->dev);
1237 pm_runtime_dont_use_autosuspend(&pdev->dev);
1238 pm_runtime_put_sync(&pdev->dev);
1239 pm_runtime_disable(&pdev->dev);
1243 static int omap8250_remove(struct platform_device *pdev)
1245 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1247 pm_runtime_dont_use_autosuspend(&pdev->dev);
1248 pm_runtime_put_sync(&pdev->dev);
1249 pm_runtime_disable(&pdev->dev);
1250 serial8250_unregister_port(priv->line);
1251 pm_qos_remove_request(&priv->pm_qos_request);
1252 device_init_wakeup(&pdev->dev, false);
1256 #ifdef CONFIG_PM_SLEEP
1257 static int omap8250_prepare(struct device *dev)
1259 struct omap8250_priv *priv = dev_get_drvdata(dev);
1263 priv->is_suspending = true;
1267 static void omap8250_complete(struct device *dev)
1269 struct omap8250_priv *priv = dev_get_drvdata(dev);
1273 priv->is_suspending = false;
1276 static int omap8250_suspend(struct device *dev)
1278 struct omap8250_priv *priv = dev_get_drvdata(dev);
1280 serial8250_suspend_port(priv->line);
1281 flush_work(&priv->qos_work);
1285 static int omap8250_resume(struct device *dev)
1287 struct omap8250_priv *priv = dev_get_drvdata(dev);
1289 serial8250_resume_port(priv->line);
1293 #define omap8250_prepare NULL
1294 #define omap8250_complete NULL
1298 static int omap8250_lost_context(struct uart_8250_port *up)
1302 val = serial_in(up, UART_OMAP_SCR);
1304 * If we lose context, then SCR is set to its reset value of zero.
1305 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1306 * among other bits, to never set the register back to zero again.
1313 /* TODO: in future, this should happen via API in drivers/reset/ */
1314 static int omap8250_soft_reset(struct device *dev)
1316 struct omap8250_priv *priv = dev_get_drvdata(dev);
1317 struct uart_8250_port *up = serial8250_get_port(priv->line);
1322 sysc = serial_in(up, UART_OMAP_SYSC);
1324 /* softreset the UART */
1325 sysc |= OMAP_UART_SYSC_SOFTRESET;
1326 serial_out(up, UART_OMAP_SYSC, sysc);
1328 /* By experiments, 1us enough for reset complete on AM335x */
1331 syss = serial_in(up, UART_OMAP_SYSS);
1332 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1335 dev_err(dev, "timed out waiting for reset done\n");
1342 static int omap8250_runtime_suspend(struct device *dev)
1344 struct omap8250_priv *priv = dev_get_drvdata(dev);
1345 struct uart_8250_port *up;
1347 /* In case runtime-pm tries this before we are setup */
1351 up = serial8250_get_port(priv->line);
1353 * When using 'no_console_suspend', the console UART must not be
1354 * suspended. Since driver suspend is managed by runtime suspend,
1355 * preventing runtime suspend (by returning error) will keep device
1356 * active during suspend.
1358 if (priv->is_suspending && !console_suspend_enabled) {
1359 if (uart_console(&up->port))
1363 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1366 ret = omap8250_soft_reset(dev);
1370 /* Restore to UART mode after reset (for wakeup) */
1371 omap8250_update_mdr1(up, priv);
1374 if (up->dma && up->dma->rxchan)
1375 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
1377 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1378 schedule_work(&priv->qos_work);
1383 static int omap8250_runtime_resume(struct device *dev)
1385 struct omap8250_priv *priv = dev_get_drvdata(dev);
1386 struct uart_8250_port *up;
1389 /* In case runtime-pm tries this before we are setup */
1393 up = serial8250_get_port(priv->line);
1394 loss_cntx = omap8250_lost_context(up);
1397 omap8250_restore_regs(up);
1399 if (up->dma && up->dma->rxchan)
1400 omap_8250_rx_dma(up, 0);
1402 priv->latency = priv->calc_latency;
1403 schedule_work(&priv->qos_work);
1408 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1409 static int __init omap8250_console_fixup(void)
1415 if (strstr(boot_command_line, "console=ttyS"))
1416 /* user set a ttyS based name for the console */
1419 omap_str = strstr(boot_command_line, "console=ttyO");
1421 /* user did not set ttyO based console, so we don't care */
1425 if ('0' <= *omap_str && *omap_str <= '9')
1426 idx = *omap_str - '0';
1431 if (omap_str[0] == ',') {
1438 add_preferred_console("ttyS", idx, options);
1439 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1441 pr_err("This ensures that you still see kernel messages. Please\n");
1442 pr_err("update your kernel commandline.\n");
1445 console_initcall(omap8250_console_fixup);
1448 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1449 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1450 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1451 omap8250_runtime_resume, NULL)
1452 .prepare = omap8250_prepare,
1453 .complete = omap8250_complete,
1456 static struct platform_driver omap8250_platform_driver = {
1459 .pm = &omap8250_dev_pm_ops,
1460 .of_match_table = omap8250_dt_ids,
1462 .probe = omap8250_probe,
1463 .remove = omap8250_remove,
1465 module_platform_driver(omap8250_platform_driver);
1467 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1468 MODULE_DESCRIPTION("OMAP 8250 Driver");
1469 MODULE_LICENSE("GPL v2");