drivers/tty/serial/8250/8250_of.c

   1 /*
   2  *  Serial Port driver for Open Firmware platform devices
   3  *
   4  *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  */
  12 #include <linux/console.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <linux/delay.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/clk.h>
  23 #include <linux/reset.h>
  24
  25 #include "8250.h"
  26
  27 struct of_serial_info {
  28         struct clk *clk;
  29         struct reset_control *rst;
  30         int type;
  31         int line;
  32 };
  33
  34 #ifdef CONFIG_ARCH_TEGRA
  35 static void tegra_serial_handle_break(struct uart_port *p)
  36 {
  37         unsigned int status, tmout = 10000;
  38
  39         do {
  40                 status = p->serial_in(p, UART_LSR);
  41                 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
  42                         status = p->serial_in(p, UART_RX);
  43                 else
  44                         break;
  45                 if (--tmout == 0)
  46                         break;
  47                 udelay(1);
  48         } while (1);
  49 }
  50 #else
  51 static inline void tegra_serial_handle_break(struct uart_port *port)
  52 {
  53 }
  54 #endif
  55
  56 /*
  57  * Fill a struct uart_port for a given device node
  58  */
  59 static int of_platform_serial_setup(struct platform_device *ofdev,
  60                         int type, struct uart_port *port,
  61                         struct of_serial_info *info)
  62 {
  63         struct resource resource;
  64         struct device_node *np = ofdev->dev.of_node;
  65         u32 clk, spd, prop;
  66         int ret;
  67
  68         memset(port, 0, sizeof *port);
  69
  70         pm_runtime_enable(&ofdev->dev);
  71         pm_runtime_get_sync(&ofdev->dev);
  72
  73         if (of_property_read_u32(np, "clock-frequency", &clk)) {
  74
  75                 /* Get clk rate through clk driver if present */
  76                 info->clk = devm_clk_get(&ofdev->dev, NULL);
  77                 if (IS_ERR(info->clk)) {
  78                         dev_warn(&ofdev->dev,
  79                                 "clk or clock-frequency not defined\n");
  80                         ret = PTR_ERR(info->clk);
  81                         goto err_pmruntime;
  82                 }
  83
  84                 ret = clk_prepare_enable(info->clk);
  85                 if (ret < 0)
  86                         goto err_pmruntime;
  87
  88                 clk = clk_get_rate(info->clk);
  89         }
  90         /* If current-speed was set, then try not to change it. */
  91         if (of_property_read_u32(np, "current-speed", &spd) == 0)
  92                 port->custom_divisor = clk / (16 * spd);
  93
  94         ret = of_address_to_resource(np, 0, &resource);
  95         if (ret) {
  96                 dev_warn(&ofdev->dev, "invalid address\n");
  97                 goto err_unprepare;
  98         }
  99
 100         spin_lock_init(&port->lock);
 101         port->mapbase = resource.start;
 102         port->mapsize = resource_size(&resource);
 103
 104         /* Check for shifted address mapping */
 105         if (of_property_read_u32(np, "reg-offset", &prop) == 0)
 106                 port->mapbase += prop;
 107
 108         /* Compatibility with the deprecated pxa driver and 8250_pxa drivers. */
 109         if (of_device_is_compatible(np, "mrvl,mmp-uart"))
 110                 port->regshift = 2;
 111
 112         /* Check for registers offset within the devices address range */
 113         if (of_property_read_u32(np, "reg-shift", &prop) == 0)
 114                 port->regshift = prop;
 115
 116         /* Check for fifo size */
 117         if (of_property_read_u32(np, "fifo-size", &prop) == 0)
 118                 port->fifosize = prop;
 119
 120         /* Check for a fixed line number */
 121         ret = of_alias_get_id(np, "serial");
 122         if (ret >= 0)
 123                 port->line = ret;
 124
 125         port->irq = irq_of_parse_and_map(np, 0);
 126         port->iotype = UPIO_MEM;
 127         if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
 128                 switch (prop) {
 129                 case 1:
 130                         port->iotype = UPIO_MEM;
 131                         break;
 132                 case 2:
 133                         port->iotype = UPIO_MEM16;
 134                         break;
 135                 case 4:
 136                         port->iotype = of_device_is_big_endian(np) ?
 137                                        UPIO_MEM32BE : UPIO_MEM32;
 138                         break;
 139                 default:
 140                         dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
 141                                  prop);
 142                         ret = -EINVAL;
 143                         goto err_dispose;
 144                 }
 145         }
 146
 147         info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
 148         if (IS_ERR(info->rst)) {
 149                 ret = PTR_ERR(info->rst);
 150                 goto err_dispose;
 151         }
 152
 153         ret = reset_control_deassert(info->rst);
 154         if (ret)
 155                 goto err_dispose;
 156
 157         port->type = type;
 158         port->uartclk = clk;
 159         port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
 160                 | UPF_FIXED_PORT | UPF_FIXED_TYPE;
 161
 162         if (of_property_read_bool(np, "no-loopback-test"))
 163                 port->flags |= UPF_SKIP_TEST;
 164
 165         port->dev = &ofdev->dev;
 166
 167         switch (type) {
 168         case PORT_TEGRA:
 169                 port->handle_break = tegra_serial_handle_break;
 170                 break;
 171
 172         case PORT_RT2880:
 173                 port->iotype = UPIO_AU;
 174                 break;
 175         }
 176
 177         if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
 178             (of_device_is_compatible(np, "fsl,ns16550") ||
 179              of_device_is_compatible(np, "fsl,16550-FIFO64")))
 180                 port->handle_irq = fsl8250_handle_irq;
 181
 182         return 0;
 183 err_dispose:
 184         irq_dispose_mapping(port->irq);
 185 err_unprepare:
 186         clk_disable_unprepare(info->clk);
 187 err_pmruntime:
 188         pm_runtime_put_sync(&ofdev->dev);
 189         pm_runtime_disable(&ofdev->dev);
 190         return ret;
 191 }
 192
 193 /*
 194  * Try to register a serial port
 195  */
 196 static const struct of_device_id of_platform_serial_table[];
 197 static int of_platform_serial_probe(struct platform_device *ofdev)
 198 {
 199         const struct of_device_id *match;
 200         struct of_serial_info *info;
 201         struct uart_8250_port port8250;
 202         u32 tx_threshold;
 203         int port_type;
 204         int ret;
 205
 206         match = of_match_device(of_platform_serial_table, &ofdev->dev);
 207         if (!match)
 208                 return -EINVAL;
 209
 210         if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
 211                 return -EBUSY;
 212
 213         info = kzalloc(sizeof(*info), GFP_KERNEL);
 214         if (info == NULL)
 215                 return -ENOMEM;
 216
 217         port_type = (unsigned long)match->data;
 218         memset(&port8250, 0, sizeof(port8250));
 219         ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
 220         if (ret)
 221                 goto err_free;
 222
 223         if (port8250.port.fifosize)
 224                 port8250.capabilities = UART_CAP_FIFO;
 225
 226         /* Check for TX FIFO threshold & set tx_loadsz */
 227         if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
 228                                   &tx_threshold) == 0) &&
 229             (tx_threshold < port8250.port.fifosize))
 230                 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
 231
 232         if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
 233                 port8250.capabilities |= UART_CAP_AFE;
 234
 235         if (of_property_read_u32(ofdev->dev.of_node,
 236                         "overrun-throttle-ms",
 237                         &port8250.overrun_backoff_time_ms) != 0)
 238                 port8250.overrun_backoff_time_ms = 0;
 239
 240         ret = serial8250_register_8250_port(&port8250);
 241         if (ret < 0)
 242                 goto err_dispose;
 243
 244         info->type = port_type;
 245         info->line = ret;
 246         platform_set_drvdata(ofdev, info);
 247         return 0;
 248 err_dispose:
 249         irq_dispose_mapping(port8250.port.irq);
 250         pm_runtime_put_sync(&ofdev->dev);
 251         pm_runtime_disable(&ofdev->dev);
 252         clk_disable_unprepare(info->clk);
 253 err_free:
 254         kfree(info);
 255         return ret;
 256 }
 257
 258 /*
 259  * Release a line
 260  */
 261 static int of_platform_serial_remove(struct platform_device *ofdev)
 262 {
 263         struct of_serial_info *info = platform_get_drvdata(ofdev);
 264
 265         serial8250_unregister_port(info->line);
 266
 267         reset_control_assert(info->rst);
 268         pm_runtime_put_sync(&ofdev->dev);
 269         pm_runtime_disable(&ofdev->dev);
 270         clk_disable_unprepare(info->clk);
 271         kfree(info);
 272         return 0;
 273 }
 274
 275 #ifdef CONFIG_PM_SLEEP
 276 static int of_serial_suspend(struct device *dev)
 277 {
 278         struct of_serial_info *info = dev_get_drvdata(dev);
 279         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 280         struct uart_port *port = &port8250->port;
 281
 282         serial8250_suspend_port(info->line);
 283
 284         if (!uart_console(port) || console_suspend_enabled) {
 285                 pm_runtime_put_sync(dev);
 286                 clk_disable_unprepare(info->clk);
 287         }
 288         return 0;
 289 }
 290
 291 static int of_serial_resume(struct device *dev)
 292 {
 293         struct of_serial_info *info = dev_get_drvdata(dev);
 294         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 295         struct uart_port *port = &port8250->port;
 296
 297         if (!uart_console(port) || console_suspend_enabled) {
 298                 pm_runtime_get_sync(dev);
 299                 clk_prepare_enable(info->clk);
 300         }
 301
 302         serial8250_resume_port(info->line);
 303
 304         return 0;
 305 }
 306 #endif
 307 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
 308
 309 /*
 310  * A few common types, add more as needed.
 311  */
 312 static const struct of_device_id of_platform_serial_table[] = {
 313         { .compatible = "ns8250",   .data = (void *)PORT_8250, },
 314         { .compatible = "ns16450",  .data = (void *)PORT_16450, },
 315         { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
 316         { .compatible = "ns16550",  .data = (void *)PORT_16550, },
 317         { .compatible = "ns16750",  .data = (void *)PORT_16750, },
 318         { .compatible = "ns16850",  .data = (void *)PORT_16850, },
 319         { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
 320         { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
 321         { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
 322         { .compatible = "altr,16550-FIFO32",
 323                 .data = (void *)PORT_ALTR_16550_F32, },
 324         { .compatible = "altr,16550-FIFO64",
 325                 .data = (void *)PORT_ALTR_16550_F64, },
 326         { .compatible = "altr,16550-FIFO128",
 327                 .data = (void *)PORT_ALTR_16550_F128, },
 328         { .compatible = "mediatek,mtk-btif",
 329                 .data = (void *)PORT_MTK_BTIF, },
 330         { .compatible = "mrvl,mmp-uart",
 331                 .data = (void *)PORT_XSCALE, },
 332         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
 333         { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
 334         { /* end of list */ },
 335 };
 336 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
 337
 338 static struct platform_driver of_platform_serial_driver = {
 339         .driver = {
 340                 .name = "of_serial",
 341                 .of_match_table = of_platform_serial_table,
 342                 .pm = &of_serial_pm_ops,
 343         },
 344         .probe = of_platform_serial_probe,
 345         .remove = of_platform_serial_remove,
 346 };
 347
 348 module_platform_driver(of_platform_serial_driver);
 349
 350 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
 351 MODULE_LICENSE("GPL");
 352 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");