2 * Mediatek 8250 driver.
4 * Copyright (c) 2014 MundoReader S.L.
5 * Author: Matthias Brugger <matthias.bgg@gmail.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #include <linux/clk.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/serial_8250.h>
25 #include <linux/serial_reg.h>
29 #define UART_MTK_HIGHS 0x09 /* Highspeed register */
30 #define UART_MTK_SAMPLE_COUNT 0x0a /* Sample count register */
31 #define UART_MTK_SAMPLE_POINT 0x0b /* Sample point register */
32 #define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */
41 mtk8250_set_termios(struct uart_port *port, struct ktermios *termios,
45 unsigned int baud, quot;
47 struct uart_8250_port *up =
48 container_of(port, struct uart_8250_port, port);
51 * Store the requested baud rate before calling the generic 8250
52 * set_termios method. Standard 8250 port expects bauds to be
53 * no higher than (uartclk / 16) so the baud will be clamped if it
54 * gets out of that bound. Mediatek 8250 port supports speed
55 * higher than that, therefore we'll get original baud rate back
56 * after calling the generic set_termios method and recalculate
57 * the speed later in this method.
59 baud = tty_termios_baud_rate(termios);
61 serial8250_do_set_termios(port, termios, NULL);
63 tty_termios_encode_baud_rate(termios, baud, baud);
66 * Mediatek UARTs use an extra highspeed register (UART_MTK_HIGHS)
68 * We need to recalcualte the quot register, as the claculation depends
69 * on the vaule in the highspeed register.
71 * Some baudrates are not supported by the chip, so we use the next
72 * lower rate supported and update termios c_flag.
74 * If highspeed register is set to 3, we need to specify sample count
75 * and sample point to increase accuracy. If not, we reset the
76 * registers to their default values.
78 baud = uart_get_baud_rate(port, termios, old,
79 port->uartclk / 16 / 0xffff,
83 serial_port_out(port, UART_MTK_HIGHS, 0x0);
84 quot = uart_get_divisor(port, baud);
85 } else if (baud <= 576000) {
86 serial_port_out(port, UART_MTK_HIGHS, 0x2);
88 /* Set to next lower baudrate supported */
89 if ((baud == 500000) || (baud == 576000))
91 quot = DIV_ROUND_UP(port->uartclk, 4 * baud);
93 serial_port_out(port, UART_MTK_HIGHS, 0x3);
95 /* Set to highest baudrate supported */
98 quot = DIV_ROUND_UP(port->uartclk, 256 * baud);
102 * Ok, we're now changing the port state. Do it with
103 * interrupts disabled.
105 spin_lock_irqsave(&port->lock, flags);
108 * Update the per-port timeout.
110 uart_update_timeout(port, termios->c_cflag, baud);
112 /* set DLAB we have cval saved in up->lcr from the call to the core */
113 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
114 serial_dl_write(up, quot);
117 serial_port_out(port, UART_LCR, up->lcr);
122 tmp = DIV_ROUND_CLOSEST(port->uartclk, quot * baud);
123 serial_port_out(port, UART_MTK_SAMPLE_COUNT, tmp - 1);
124 serial_port_out(port, UART_MTK_SAMPLE_POINT,
127 serial_port_out(port, UART_MTK_SAMPLE_COUNT, 0x00);
128 serial_port_out(port, UART_MTK_SAMPLE_POINT, 0xff);
131 spin_unlock_irqrestore(&port->lock, flags);
132 /* Don't rewrite B0 */
133 if (tty_termios_baud_rate(termios))
134 tty_termios_encode_baud_rate(termios, baud, baud);
137 static int mtk8250_runtime_suspend(struct device *dev)
139 struct mtk8250_data *data = dev_get_drvdata(dev);
141 clk_disable_unprepare(data->uart_clk);
142 clk_disable_unprepare(data->bus_clk);
147 static int mtk8250_runtime_resume(struct device *dev)
149 struct mtk8250_data *data = dev_get_drvdata(dev);
152 err = clk_prepare_enable(data->uart_clk);
154 dev_warn(dev, "Can't enable clock\n");
158 err = clk_prepare_enable(data->bus_clk);
160 dev_warn(dev, "Can't enable bus clock\n");
168 mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
171 pm_runtime_get_sync(port->dev);
173 serial8250_do_pm(port, state, old);
176 pm_runtime_put_sync_suspend(port->dev);
179 static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p,
180 struct mtk8250_data *data)
182 data->uart_clk = devm_clk_get(&pdev->dev, "baud");
183 if (IS_ERR(data->uart_clk)) {
185 * For compatibility with older device trees try unnamed
186 * clk when no baud clk can be found.
188 data->uart_clk = devm_clk_get(&pdev->dev, NULL);
189 if (IS_ERR(data->uart_clk)) {
190 dev_warn(&pdev->dev, "Can't get uart clock\n");
191 return PTR_ERR(data->uart_clk);
197 data->bus_clk = devm_clk_get(&pdev->dev, "bus");
198 if (IS_ERR(data->bus_clk))
199 return PTR_ERR(data->bus_clk);
204 static int mtk8250_probe(struct platform_device *pdev)
206 struct uart_8250_port uart = {};
207 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
209 struct mtk8250_data *data;
213 dev_err(&pdev->dev, "no registers/irq defined\n");
217 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
218 resource_size(regs));
219 if (!uart.port.membase)
222 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
226 if (pdev->dev.of_node) {
227 err = mtk8250_probe_of(pdev, &uart.port, data);
233 spin_lock_init(&uart.port.lock);
234 uart.port.mapbase = regs->start;
235 uart.port.irq = irq->start;
236 uart.port.pm = mtk8250_do_pm;
237 uart.port.type = PORT_16550;
238 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
239 uart.port.dev = &pdev->dev;
240 uart.port.iotype = UPIO_MEM32;
241 uart.port.regshift = 2;
242 uart.port.private_data = data;
243 uart.port.set_termios = mtk8250_set_termios;
244 uart.port.uartclk = clk_get_rate(data->uart_clk);
246 /* Disable Rate Fix function */
247 writel(0x0, uart.port.membase +
248 (MTK_UART_RATE_FIX << uart.port.regshift));
250 platform_set_drvdata(pdev, data);
252 err = mtk8250_runtime_resume(&pdev->dev);
256 data->line = serial8250_register_8250_port(&uart);
260 pm_runtime_set_active(&pdev->dev);
261 pm_runtime_enable(&pdev->dev);
266 static int mtk8250_remove(struct platform_device *pdev)
268 struct mtk8250_data *data = platform_get_drvdata(pdev);
270 pm_runtime_get_sync(&pdev->dev);
272 serial8250_unregister_port(data->line);
273 mtk8250_runtime_suspend(&pdev->dev);
275 pm_runtime_disable(&pdev->dev);
276 pm_runtime_put_noidle(&pdev->dev);
281 #ifdef CONFIG_PM_SLEEP
282 static int mtk8250_suspend(struct device *dev)
284 struct mtk8250_data *data = dev_get_drvdata(dev);
286 serial8250_suspend_port(data->line);
291 static int mtk8250_resume(struct device *dev)
293 struct mtk8250_data *data = dev_get_drvdata(dev);
295 serial8250_resume_port(data->line);
299 #endif /* CONFIG_PM_SLEEP */
301 static const struct dev_pm_ops mtk8250_pm_ops = {
302 SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume)
303 SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume,
307 static const struct of_device_id mtk8250_of_match[] = {
308 { .compatible = "mediatek,mt6577-uart" },
311 MODULE_DEVICE_TABLE(of, mtk8250_of_match);
313 static struct platform_driver mtk8250_platform_driver = {
315 .name = "mt6577-uart",
316 .pm = &mtk8250_pm_ops,
317 .of_match_table = mtk8250_of_match,
319 .probe = mtk8250_probe,
320 .remove = mtk8250_remove,
322 module_platform_driver(mtk8250_platform_driver);
324 #ifdef CONFIG_SERIAL_8250_CONSOLE
325 static int __init early_mtk8250_setup(struct earlycon_device *device,
328 if (!device->port.membase)
331 device->port.iotype = UPIO_MEM32;
333 return early_serial8250_setup(device, NULL);
336 OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);
339 MODULE_AUTHOR("Matthias Brugger");
340 MODULE_LICENSE("GPL");
341 MODULE_DESCRIPTION("Mediatek 8250 serial port driver");