1 // SPDX-License-Identifier: GPL-2.0
3 * 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
5 * Copyright (C) 2016 Intel Corporation
6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
9 #include <linux/bitops.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/rational.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma/dw.h>
17 #include "8250_dwlib.h"
19 #define PCI_DEVICE_ID_INTEL_QRK_UARTx 0x0936
21 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
22 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
24 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
25 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
27 #define PCI_DEVICE_ID_INTEL_EHL_UART0 0x4b96
28 #define PCI_DEVICE_ID_INTEL_EHL_UART1 0x4b97
29 #define PCI_DEVICE_ID_INTEL_EHL_UART2 0x4b98
30 #define PCI_DEVICE_ID_INTEL_EHL_UART3 0x4b99
31 #define PCI_DEVICE_ID_INTEL_EHL_UART4 0x4b9a
32 #define PCI_DEVICE_ID_INTEL_EHL_UART5 0x4b9b
34 #define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
35 #define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
37 /* Intel LPSS specific registers */
39 #define BYT_PRV_CLK 0x800
40 #define BYT_PRV_CLK_EN BIT(0)
41 #define BYT_PRV_CLK_M_VAL_SHIFT 1
42 #define BYT_PRV_CLK_N_VAL_SHIFT 16
43 #define BYT_PRV_CLK_UPDATE BIT(31)
45 #define BYT_TX_OVF_INT 0x820
46 #define BYT_TX_OVF_INT_MASK BIT(1)
50 struct lpss8250_board {
52 unsigned int base_baud;
53 int (*setup)(struct lpss8250 *, struct uart_port *p);
54 void (*exit)(struct lpss8250 *);
58 struct dw8250_port_data data;
59 struct lpss8250_board *board;
62 struct dw_dma_chip dma_chip;
63 struct dw_dma_slave dma_param;
67 static inline struct lpss8250 *to_lpss8250(struct dw8250_port_data *data)
69 return container_of(data, struct lpss8250, data);
72 static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
75 unsigned int baud = tty_termios_baud_rate(termios);
76 struct lpss8250 *lpss = to_lpss8250(p->private_data);
77 unsigned long fref = lpss->board->freq, fuart = baud * 16;
78 unsigned long w = BIT(15) - 1;
82 /* Gracefully handle the B0 case: fall back to B9600 */
83 fuart = fuart ? fuart : 9600 * 16;
85 /* Get Fuart closer to Fref */
86 fuart *= rounddown_pow_of_two(fref / fuart);
89 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
90 * dividers must be adjusted.
92 * uartclk = (m / n) * 100 MHz, where m <= n
94 rational_best_approximation(fuart, fref, w, w, &m, &n);
98 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
99 writel(reg, p->membase + BYT_PRV_CLK);
100 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
101 writel(reg, p->membase + BYT_PRV_CLK);
103 p->status &= ~UPSTAT_AUTOCTS;
104 if (termios->c_cflag & CRTSCTS)
105 p->status |= UPSTAT_AUTOCTS;
107 serial8250_do_set_termios(p, termios, old);
110 static unsigned int byt_get_mctrl(struct uart_port *port)
112 unsigned int ret = serial8250_do_get_mctrl(port);
114 /* Force DCD and DSR signals to permanently be reported as active */
115 ret |= TIOCM_CAR | TIOCM_DSR;
120 static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
122 struct dw_dma_slave *param = &lpss->dma_param;
123 struct pci_dev *pdev = to_pci_dev(port->dev);
124 struct pci_dev *dma_dev;
126 switch (pdev->device) {
127 case PCI_DEVICE_ID_INTEL_BYT_UART1:
128 case PCI_DEVICE_ID_INTEL_BSW_UART1:
129 case PCI_DEVICE_ID_INTEL_BDW_UART1:
133 case PCI_DEVICE_ID_INTEL_BYT_UART2:
134 case PCI_DEVICE_ID_INTEL_BSW_UART2:
135 case PCI_DEVICE_ID_INTEL_BDW_UART2:
143 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
145 param->dma_dev = &dma_dev->dev;
149 lpss->dma_maxburst = 16;
151 port->set_termios = byt_set_termios;
152 port->get_mctrl = byt_get_mctrl;
154 /* Disable TX counter interrupts */
155 writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
160 static void byt_serial_exit(struct lpss8250 *lpss)
162 struct dw_dma_slave *param = &lpss->dma_param;
164 /* Paired with pci_get_slot() in the byt_serial_setup() above */
165 put_device(param->dma_dev);
168 static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
173 static void ehl_serial_exit(struct lpss8250 *lpss)
175 struct uart_8250_port *up = serial8250_get_port(lpss->data.line);
180 #ifdef CONFIG_SERIAL_8250_DMA
181 static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
183 .chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
184 .chan_priority = CHAN_PRIORITY_ASCENDING,
191 static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
193 struct uart_8250_dma *dma = &lpss->data.dma;
194 struct dw_dma_chip *chip = &lpss->dma_chip;
195 struct dw_dma_slave *param = &lpss->dma_param;
196 struct pci_dev *pdev = to_pci_dev(port->dev);
199 chip->pdata = &qrk_serial_dma_pdata;
200 chip->dev = &pdev->dev;
201 chip->id = pdev->devfn;
202 chip->irq = pci_irq_vector(pdev, 0);
203 chip->regs = pci_ioremap_bar(pdev, 1);
207 /* Falling back to PIO mode if DMA probing fails */
208 ret = dw_dma_probe(chip);
212 pci_try_set_mwi(pdev);
214 /* Special DMA address for UART */
215 dma->rx_dma_addr = 0xfffff000;
216 dma->tx_dma_addr = 0xfffff000;
218 param->dma_dev = &pdev->dev;
221 param->hs_polarity = true;
223 lpss->dma_maxburst = 8;
226 static void qrk_serial_exit_dma(struct lpss8250 *lpss)
228 struct dw_dma_chip *chip = &lpss->dma_chip;
229 struct dw_dma_slave *param = &lpss->dma_param;
236 pci_iounmap(to_pci_dev(chip->dev), chip->regs);
238 #else /* CONFIG_SERIAL_8250_DMA */
239 static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port) {}
240 static void qrk_serial_exit_dma(struct lpss8250 *lpss) {}
241 #endif /* !CONFIG_SERIAL_8250_DMA */
243 static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
245 qrk_serial_setup_dma(lpss, port);
249 static void qrk_serial_exit(struct lpss8250 *lpss)
251 qrk_serial_exit_dma(lpss);
254 static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
256 struct dw_dma_slave *dws = param;
258 if (dws->dma_dev != chan->device->dev)
265 static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
267 struct uart_8250_dma *dma = &lpss->data.dma;
268 struct dw_dma_slave *rx_param, *tx_param;
269 struct device *dev = port->port.dev;
271 if (!lpss->dma_param.dma_dev)
274 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
278 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
282 *rx_param = lpss->dma_param;
283 dma->rxconf.src_maxburst = lpss->dma_maxburst;
285 *tx_param = lpss->dma_param;
286 dma->txconf.dst_maxburst = lpss->dma_maxburst;
288 dma->fn = lpss8250_dma_filter;
289 dma->rx_param = rx_param;
290 dma->tx_param = tx_param;
296 static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
298 struct uart_8250_port uart;
299 struct lpss8250 *lpss;
302 ret = pcim_enable_device(pdev);
306 pci_set_master(pdev);
308 lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
312 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
316 lpss->board = (struct lpss8250_board *)id->driver_data;
318 memset(&uart, 0, sizeof(struct uart_8250_port));
320 uart.port.dev = &pdev->dev;
321 uart.port.irq = pci_irq_vector(pdev, 0);
322 uart.port.private_data = &lpss->data;
323 uart.port.type = PORT_16550A;
324 uart.port.iotype = UPIO_MEM;
325 uart.port.regshift = 2;
326 uart.port.uartclk = lpss->board->base_baud * 16;
327 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
328 uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
329 uart.port.mapbase = pci_resource_start(pdev, 0);
330 uart.port.membase = pcim_iomap(pdev, 0, 0);
331 if (!uart.port.membase)
334 ret = lpss->board->setup(lpss, &uart.port);
338 dw8250_setup_port(&uart.port);
340 ret = lpss8250_dma_setup(lpss, &uart);
344 ret = serial8250_register_8250_port(&uart);
348 lpss->data.line = ret;
350 pci_set_drvdata(pdev, lpss);
354 lpss->board->exit(lpss);
355 pci_free_irq_vectors(pdev);
359 static void lpss8250_remove(struct pci_dev *pdev)
361 struct lpss8250 *lpss = pci_get_drvdata(pdev);
363 serial8250_unregister_port(lpss->data.line);
365 lpss->board->exit(lpss);
366 pci_free_irq_vectors(pdev);
369 static const struct lpss8250_board byt_board = {
371 .base_baud = 2764800,
372 .setup = byt_serial_setup,
373 .exit = byt_serial_exit,
376 static const struct lpss8250_board ehl_board = {
378 .base_baud = 12500000,
379 .setup = ehl_serial_setup,
380 .exit = ehl_serial_exit,
383 static const struct lpss8250_board qrk_board = {
385 .base_baud = 2764800,
386 .setup = qrk_serial_setup,
387 .exit = qrk_serial_exit,
390 static const struct pci_device_id pci_ids[] = {
391 { PCI_DEVICE_DATA(INTEL, QRK_UARTx, &qrk_board) },
392 { PCI_DEVICE_DATA(INTEL, EHL_UART0, &ehl_board) },
393 { PCI_DEVICE_DATA(INTEL, EHL_UART1, &ehl_board) },
394 { PCI_DEVICE_DATA(INTEL, EHL_UART2, &ehl_board) },
395 { PCI_DEVICE_DATA(INTEL, EHL_UART3, &ehl_board) },
396 { PCI_DEVICE_DATA(INTEL, EHL_UART4, &ehl_board) },
397 { PCI_DEVICE_DATA(INTEL, EHL_UART5, &ehl_board) },
398 { PCI_DEVICE_DATA(INTEL, BYT_UART1, &byt_board) },
399 { PCI_DEVICE_DATA(INTEL, BYT_UART2, &byt_board) },
400 { PCI_DEVICE_DATA(INTEL, BSW_UART1, &byt_board) },
401 { PCI_DEVICE_DATA(INTEL, BSW_UART2, &byt_board) },
402 { PCI_DEVICE_DATA(INTEL, BDW_UART1, &byt_board) },
403 { PCI_DEVICE_DATA(INTEL, BDW_UART2, &byt_board) },
406 MODULE_DEVICE_TABLE(pci, pci_ids);
408 static struct pci_driver lpss8250_pci_driver = {
411 .probe = lpss8250_probe,
412 .remove = lpss8250_remove,
415 module_pci_driver(lpss8250_pci_driver);
417 MODULE_AUTHOR("Intel Corporation");
418 MODULE_LICENSE("GPL v2");
419 MODULE_DESCRIPTION("Intel LPSS UART driver");