1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2015 Imagination Technologies
6 * Ingenic SoC UART support
10 #include <linux/console.h>
12 #include <linux/libfdt.h>
13 #include <linux/module.h>
15 #include <linux/of_fdt.h>
16 #include <linux/platform_device.h>
17 #include <linux/serial_8250.h>
18 #include <linux/serial_core.h>
19 #include <linux/serial_reg.h>
23 /** ingenic_uart_config: SOC specific config data. */
24 struct ingenic_uart_config {
29 struct ingenic_uart_data {
30 struct clk *clk_module;
35 static const struct of_device_id of_match[];
37 #define UART_FCR_UME BIT(4)
39 #define UART_MCR_MDCE BIT(7)
40 #define UART_MCR_FCM BIT(6)
42 static struct earlycon_device *early_device;
44 static uint8_t early_in(struct uart_port *port, int offset)
46 return readl(port->membase + (offset << 2));
49 static void early_out(struct uart_port *port, int offset, uint8_t value)
51 writel(value, port->membase + (offset << 2));
54 static void ingenic_early_console_putc(struct uart_port *port, unsigned char c)
59 lsr = early_in(port, UART_LSR);
60 } while ((lsr & UART_LSR_TEMT) == 0);
62 early_out(port, UART_TX, c);
65 static void ingenic_early_console_write(struct console *console,
66 const char *s, unsigned int count)
68 uart_console_write(&early_device->port, s, count,
69 ingenic_early_console_putc);
72 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
74 void *fdt = initial_boot_params;
78 offset = fdt_path_offset(fdt, "/ext");
82 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
86 dev->port.uartclk = be32_to_cpup(prop);
89 static int __init ingenic_earlycon_setup_tail(struct earlycon_device *dev,
92 struct uart_port *port = &dev->port;
96 if (!dev->port.membase)
100 unsigned int parity, bits, flow; /* unused for now */
102 uart_parse_options(opt, &baud, &parity, &bits, &flow);
107 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
109 early_out(port, UART_IER, 0);
110 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
111 early_out(port, UART_DLL, 0);
112 early_out(port, UART_DLM, 0);
113 early_out(port, UART_LCR, UART_LCR_WLEN8);
114 early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
115 UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
116 early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
118 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
119 early_out(port, UART_DLL, divisor & 0xff);
120 early_out(port, UART_DLM, (divisor >> 8) & 0xff);
121 early_out(port, UART_LCR, UART_LCR_WLEN8);
124 dev->con->write = ingenic_early_console_write;
129 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
132 ingenic_early_console_setup_clock(dev);
134 return ingenic_earlycon_setup_tail(dev, opt);
137 static int __init jz4750_early_console_setup(struct earlycon_device *dev,
141 * JZ4750/55/60 have an optional /2 divider between the EXT
142 * oscillator and some peripherals including UART, which will
143 * be enabled if using a 24 MHz oscillator, and disabled when
144 * using a 12 MHz oscillator.
146 ingenic_early_console_setup_clock(dev);
147 if (dev->port.uartclk >= 16000000)
148 dev->port.uartclk /= 2;
150 return ingenic_earlycon_setup_tail(dev, opt);
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
154 ingenic_early_console_setup);
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
157 jz4750_early_console_setup);
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
160 ingenic_early_console_setup);
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
163 ingenic_early_console_setup);
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
166 ingenic_early_console_setup);
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
169 ingenic_early_console_setup);
171 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
177 /* UART module enable */
178 value |= UART_FCR_UME;
183 * Enable receive timeout interrupt with the receive line
186 value |= (value & 0x4) << 2;
191 * If we have enabled modem status IRQs we should enable
194 ier = p->serial_in(p, UART_IER);
196 if (ier & UART_IER_MSI)
197 value |= UART_MCR_MDCE | UART_MCR_FCM;
199 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
206 writeb(value, p->membase + (offset << p->regshift));
209 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
213 value = readb(p->membase + (offset << p->regshift));
215 /* Hide non-16550 compliant bits from higher levels */
218 value &= ~UART_FCR_UME;
222 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
231 static int ingenic_uart_probe(struct platform_device *pdev)
233 struct uart_8250_port uart = {};
234 struct ingenic_uart_data *data;
235 const struct ingenic_uart_config *cdata;
236 struct resource *regs;
239 cdata = of_device_get_match_data(&pdev->dev);
241 dev_err(&pdev->dev, "Error: No device match found\n");
245 irq = platform_get_irq(pdev, 0);
249 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
251 dev_err(&pdev->dev, "no registers defined\n");
255 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
259 spin_lock_init(&uart.port.lock);
260 uart.port.type = PORT_16550A;
261 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
262 uart.port.iotype = UPIO_MEM;
263 uart.port.mapbase = regs->start;
264 uart.port.regshift = 2;
265 uart.port.serial_out = ingenic_uart_serial_out;
266 uart.port.serial_in = ingenic_uart_serial_in;
268 uart.port.dev = &pdev->dev;
269 uart.port.fifosize = cdata->fifosize;
270 uart.tx_loadsz = cdata->tx_loadsz;
271 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
273 /* Check for a fixed line number */
274 line = of_alias_get_id(pdev->dev.of_node, "serial");
276 uart.port.line = line;
278 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
279 resource_size(regs));
280 if (!uart.port.membase)
283 data->clk_module = devm_clk_get(&pdev->dev, "module");
284 if (IS_ERR(data->clk_module))
285 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
286 "unable to get module clock\n");
288 data->clk_baud = devm_clk_get(&pdev->dev, "baud");
289 if (IS_ERR(data->clk_baud))
290 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
291 "unable to get baud clock\n");
293 err = clk_prepare_enable(data->clk_module);
295 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
299 err = clk_prepare_enable(data->clk_baud);
301 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
302 goto out_disable_moduleclk;
304 uart.port.uartclk = clk_get_rate(data->clk_baud);
306 data->line = serial8250_register_8250_port(&uart);
307 if (data->line < 0) {
309 goto out_disable_baudclk;
312 platform_set_drvdata(pdev, data);
316 clk_disable_unprepare(data->clk_baud);
317 out_disable_moduleclk:
318 clk_disable_unprepare(data->clk_module);
323 static void ingenic_uart_remove(struct platform_device *pdev)
325 struct ingenic_uart_data *data = platform_get_drvdata(pdev);
327 serial8250_unregister_port(data->line);
328 clk_disable_unprepare(data->clk_module);
329 clk_disable_unprepare(data->clk_baud);
332 static const struct ingenic_uart_config jz4740_uart_config = {
337 static const struct ingenic_uart_config jz4760_uart_config = {
342 static const struct ingenic_uart_config jz4780_uart_config = {
347 static const struct ingenic_uart_config x1000_uart_config = {
352 static const struct of_device_id of_match[] = {
353 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
354 { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config },
355 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
356 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
357 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
358 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
359 { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
362 MODULE_DEVICE_TABLE(of, of_match);
364 static struct platform_driver ingenic_uart_platform_driver = {
366 .name = "ingenic-uart",
367 .of_match_table = of_match,
369 .probe = ingenic_uart_probe,
370 .remove_new = ingenic_uart_remove,
373 module_platform_driver(ingenic_uart_platform_driver);
375 MODULE_AUTHOR("Paul Burton");
376 MODULE_LICENSE("GPL");
377 MODULE_DESCRIPTION("Ingenic SoC UART driver");