1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2015 Imagination Technologies
6 * Ingenic SoC UART support
10 #include <linux/console.h>
12 #include <linux/libfdt.h>
13 #include <linux/module.h>
15 #include <linux/of_fdt.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial_8250.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
24 /** ingenic_uart_config: SOC specific config data. */
25 struct ingenic_uart_config {
30 struct ingenic_uart_data {
31 struct clk *clk_module;
36 static const struct of_device_id of_match[];
38 #define UART_FCR_UME BIT(4)
40 #define UART_MCR_MDCE BIT(7)
41 #define UART_MCR_FCM BIT(6)
43 static struct earlycon_device *early_device;
45 static uint8_t early_in(struct uart_port *port, int offset)
47 return readl(port->membase + (offset << 2));
50 static void early_out(struct uart_port *port, int offset, uint8_t value)
52 writel(value, port->membase + (offset << 2));
55 static void ingenic_early_console_putc(struct uart_port *port, int c)
60 lsr = early_in(port, UART_LSR);
61 } while ((lsr & UART_LSR_TEMT) == 0);
63 early_out(port, UART_TX, c);
66 static void ingenic_early_console_write(struct console *console,
67 const char *s, unsigned int count)
69 uart_console_write(&early_device->port, s, count,
70 ingenic_early_console_putc);
73 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
75 void *fdt = initial_boot_params;
79 offset = fdt_path_offset(fdt, "/ext");
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
87 dev->port.uartclk = be32_to_cpup(prop);
90 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
93 struct uart_port *port = &dev->port;
97 if (!dev->port.membase)
101 unsigned int parity, bits, flow; /* unused for now */
103 uart_parse_options(opt, &baud, &parity, &bits, &flow);
106 ingenic_early_console_setup_clock(dev);
110 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
112 early_out(port, UART_IER, 0);
113 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
114 early_out(port, UART_DLL, 0);
115 early_out(port, UART_DLM, 0);
116 early_out(port, UART_LCR, UART_LCR_WLEN8);
117 early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
118 UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
119 early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
121 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
122 early_out(port, UART_DLL, divisor & 0xff);
123 early_out(port, UART_DLM, (divisor >> 8) & 0xff);
124 early_out(port, UART_LCR, UART_LCR_WLEN8);
127 dev->con->write = ingenic_early_console_write;
132 EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup);
133 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
134 ingenic_early_console_setup);
136 EARLYCON_DECLARE(jz4770_uart, ingenic_early_console_setup);
137 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
138 ingenic_early_console_setup);
140 EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup);
141 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
142 ingenic_early_console_setup);
144 EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup);
145 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
146 ingenic_early_console_setup);
148 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
154 /* UART module enable */
155 value |= UART_FCR_UME;
160 * Enable receive timeout interrupt with the receive line
163 value |= (value & 0x4) << 2;
168 * If we have enabled modem status IRQs we should enable
171 ier = p->serial_in(p, UART_IER);
173 if (ier & UART_IER_MSI)
174 value |= UART_MCR_MDCE | UART_MCR_FCM;
176 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
183 writeb(value, p->membase + (offset << p->regshift));
186 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
190 value = readb(p->membase + (offset << p->regshift));
192 /* Hide non-16550 compliant bits from higher levels */
195 value &= ~UART_FCR_UME;
199 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
208 static int ingenic_uart_probe(struct platform_device *pdev)
210 struct uart_8250_port uart = {};
211 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
212 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
213 struct ingenic_uart_data *data;
214 const struct ingenic_uart_config *cdata;
215 const struct of_device_id *match;
218 match = of_match_device(of_match, &pdev->dev);
220 dev_err(&pdev->dev, "Error: No device match found\n");
226 dev_err(&pdev->dev, "no registers/irq defined\n");
230 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
234 spin_lock_init(&uart.port.lock);
235 uart.port.type = PORT_16550A;
236 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
237 uart.port.iotype = UPIO_MEM;
238 uart.port.mapbase = regs->start;
239 uart.port.regshift = 2;
240 uart.port.serial_out = ingenic_uart_serial_out;
241 uart.port.serial_in = ingenic_uart_serial_in;
242 uart.port.irq = irq->start;
243 uart.port.dev = &pdev->dev;
244 uart.port.fifosize = cdata->fifosize;
245 uart.tx_loadsz = cdata->tx_loadsz;
246 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
248 /* Check for a fixed line number */
249 line = of_alias_get_id(pdev->dev.of_node, "serial");
251 uart.port.line = line;
253 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
254 resource_size(regs));
255 if (!uart.port.membase)
258 data->clk_module = devm_clk_get(&pdev->dev, "module");
259 if (IS_ERR(data->clk_module)) {
260 err = PTR_ERR(data->clk_module);
261 if (err != -EPROBE_DEFER)
263 "unable to get module clock: %d\n", err);
267 data->clk_baud = devm_clk_get(&pdev->dev, "baud");
268 if (IS_ERR(data->clk_baud)) {
269 err = PTR_ERR(data->clk_baud);
270 if (err != -EPROBE_DEFER)
272 "unable to get baud clock: %d\n", err);
276 err = clk_prepare_enable(data->clk_module);
278 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
282 err = clk_prepare_enable(data->clk_baud);
284 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
285 goto out_disable_moduleclk;
287 uart.port.uartclk = clk_get_rate(data->clk_baud);
289 data->line = serial8250_register_8250_port(&uart);
290 if (data->line < 0) {
292 goto out_disable_baudclk;
295 platform_set_drvdata(pdev, data);
299 clk_disable_unprepare(data->clk_baud);
300 out_disable_moduleclk:
301 clk_disable_unprepare(data->clk_module);
306 static int ingenic_uart_remove(struct platform_device *pdev)
308 struct ingenic_uart_data *data = platform_get_drvdata(pdev);
310 serial8250_unregister_port(data->line);
311 clk_disable_unprepare(data->clk_module);
312 clk_disable_unprepare(data->clk_baud);
316 static const struct ingenic_uart_config jz4740_uart_config = {
321 static const struct ingenic_uart_config jz4760_uart_config = {
326 static const struct ingenic_uart_config jz4780_uart_config = {
331 static const struct of_device_id of_match[] = {
332 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
333 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
334 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
335 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
336 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
339 MODULE_DEVICE_TABLE(of, of_match);
341 static struct platform_driver ingenic_uart_platform_driver = {
343 .name = "ingenic-uart",
344 .of_match_table = of_match,
346 .probe = ingenic_uart_probe,
347 .remove = ingenic_uart_remove,
350 module_platform_driver(ingenic_uart_platform_driver);
352 MODULE_AUTHOR("Paul Burton");
353 MODULE_LICENSE("GPL");
354 MODULE_DESCRIPTION("Ingenic SoC UART driver");