2 * Probe module for 8250/16550-type Exar chips PCI serial ports.
4 * Based on drivers/tty/serial/8250/8250_pci.c,
6 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/acpi.h>
13 #include <linux/dmi.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/property.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/tty.h>
24 #include <linux/8250_pci.h>
26 #include <asm/byteorder.h>
30 #define PCI_DEVICE_ID_ACCES_COM_2S 0x1052
31 #define PCI_DEVICE_ID_ACCES_COM_4S 0x105d
32 #define PCI_DEVICE_ID_ACCES_COM_8S 0x106c
33 #define PCI_DEVICE_ID_ACCES_COM232_8 0x10a8
34 #define PCI_DEVICE_ID_ACCES_COM_2SM 0x10d2
35 #define PCI_DEVICE_ID_ACCES_COM_4SM 0x10db
36 #define PCI_DEVICE_ID_ACCES_COM_8SM 0x10ea
38 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
39 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
40 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
41 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
42 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
43 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
44 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
45 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
46 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
48 #define UART_EXAR_INT0 0x80
49 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
51 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */
52 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */
53 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */
54 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
55 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
56 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
57 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
59 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
62 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */
63 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */
64 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */
65 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */
66 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */
67 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */
68 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */
69 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */
70 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */
71 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */
72 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */
73 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */
75 #define UART_EXAR_RS485_DLY(x) ((x) << 4)
78 * IOT2040 MPIO wiring semantics:
96 /* IOT2040 MPIOs 0..7 */
97 #define IOT2040_UART_MODE_RS232 0x01
98 #define IOT2040_UART_MODE_RS485 0x02
99 #define IOT2040_UART_MODE_RS422 0x03
100 #define IOT2040_UART_TERMINATE_BUS 0x04
102 #define IOT2040_UART1_MASK 0x0f
103 #define IOT2040_UART2_SHIFT 4
105 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */
106 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */
108 /* IOT2040 MPIOs 8..15 */
109 #define IOT2040_UARTS_ENABLE 0x03
110 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */
114 struct exar8250_platform {
115 int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
116 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
120 * struct exar8250_board - board information
121 * @num_ports: number of serial ports
122 * @reg_shift: describes UART register mapping in PCI memory
124 struct exar8250_board {
125 unsigned int num_ports;
126 unsigned int reg_shift;
128 int (*setup)(struct exar8250 *, struct pci_dev *,
129 struct uart_8250_port *, int);
130 void (*exit)(struct pci_dev *pcidev);
135 struct exar8250_board *board;
140 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
141 int idx, unsigned int offset,
142 struct uart_8250_port *port)
144 const struct exar8250_board *board = priv->board;
145 unsigned int bar = 0;
147 port->port.iotype = UPIO_MEM;
148 port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
149 port->port.membase = priv->virt + offset;
150 port->port.regshift = board->reg_shift;
156 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
157 struct uart_8250_port *port, int idx)
159 unsigned int offset = idx * 0x200;
160 unsigned int baud = 1843200;
164 port->port.uartclk = baud * 16;
166 err = default_setup(priv, pcidev, idx, offset, port);
170 p = port->port.membase;
172 writeb(0x00, p + UART_EXAR_8XMODE);
173 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
174 writeb(32, p + UART_EXAR_TXTRG);
175 writeb(32, p + UART_EXAR_RXTRG);
178 * Setup Multipurpose Input/Output pins.
181 switch (pcidev->device) {
182 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
183 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
184 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
185 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
186 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
188 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
189 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
190 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
191 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
192 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
195 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
196 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
197 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
204 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
205 struct uart_8250_port *port, int idx)
207 unsigned int offset = idx * 0x200;
208 unsigned int baud = 1843200;
210 port->port.uartclk = baud * 16;
211 return default_setup(priv, pcidev, idx, offset, port);
215 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
216 struct uart_8250_port *port, int idx)
218 unsigned int offset = idx * 0x200;
219 unsigned int baud = 921600;
221 port->port.uartclk = baud * 16;
222 return default_setup(priv, pcidev, idx, offset, port);
225 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
228 * The Commtech adapters required the MPIOs to be driven low. The Exar
229 * devices will export them as GPIOs, so we pre-configure them safely
235 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
236 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
237 // Configure GPIO as inputs for Commtech adapters
240 // Configure GPIO as outputs for SeaLevel adapters
244 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
245 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
246 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
247 writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
248 writeb(dir, p + UART_EXAR_MPIOSEL_7_0);
249 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
250 writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
251 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
252 writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
253 writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
254 writeb(dir, p + UART_EXAR_MPIOSEL_15_8);
255 writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
259 __xr17v35x_register_gpio(struct pci_dev *pcidev,
260 const struct property_entry *properties)
262 struct platform_device *pdev;
264 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
268 pdev->dev.parent = &pcidev->dev;
269 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
271 if (platform_device_add_properties(pdev, properties) < 0 ||
272 platform_device_add(pdev) < 0) {
273 platform_device_put(pdev);
280 static const struct property_entry exar_gpio_properties[] = {
281 PROPERTY_ENTRY_U32("exar,first-pin", 0),
282 PROPERTY_ENTRY_U32("ngpios", 16),
286 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
287 struct uart_8250_port *port)
289 if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
290 port->port.private_data =
291 __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
296 static const struct exar8250_platform exar8250_default_platform = {
297 .register_gpio = xr17v35x_register_gpio,
300 static int iot2040_rs485_config(struct uart_port *port,
301 struct serial_rs485 *rs485)
303 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
304 u8 __iomem *p = port->membase;
305 u8 mask = IOT2040_UART1_MASK;
309 if (rs485->flags & SER_RS485_RX_DURING_TX)
310 mode = IOT2040_UART_MODE_RS422;
312 mode = IOT2040_UART_MODE_RS485;
314 if (rs485->flags & SER_RS485_TERMINATE_BUS)
315 mode |= IOT2040_UART_TERMINATE_BUS;
317 mode = IOT2040_UART_MODE_RS232;
320 if (port->line == 3) {
321 mask <<= IOT2040_UART2_SHIFT;
322 mode <<= IOT2040_UART2_SHIFT;
325 value = readb(p + UART_EXAR_MPIOLVL_7_0);
328 writeb(value, p + UART_EXAR_MPIOLVL_7_0);
330 value = readb(p + UART_EXAR_FCTR);
332 value |= UART_FCTR_EXAR_485;
334 value &= ~UART_FCTR_EXAR_485;
335 writeb(value, p + UART_EXAR_FCTR);
338 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
340 port->rs485 = *rs485;
345 static const struct property_entry iot2040_gpio_properties[] = {
346 PROPERTY_ENTRY_U32("exar,first-pin", 10),
347 PROPERTY_ENTRY_U32("ngpios", 1),
351 static int iot2040_register_gpio(struct pci_dev *pcidev,
352 struct uart_8250_port *port)
354 u8 __iomem *p = port->port.membase;
356 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
357 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
358 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
359 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
361 port->port.private_data =
362 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
367 static const struct exar8250_platform iot2040_platform = {
368 .rs485_config = iot2040_rs485_config,
369 .register_gpio = iot2040_register_gpio,
372 static const struct dmi_system_id exar_platforms[] = {
375 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
376 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
377 "6ES7647-0AA00-1YA2"),
379 .driver_data = (void *)&iot2040_platform,
385 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
386 struct uart_8250_port *port, int idx)
388 const struct exar8250_board *board = priv->board;
389 const struct exar8250_platform *platform;
390 const struct dmi_system_id *dmi_match;
391 unsigned int offset = idx * 0x400;
392 unsigned int baud = 7812500;
396 dmi_match = dmi_first_match(exar_platforms);
398 platform = dmi_match->driver_data;
400 platform = &exar8250_default_platform;
402 port->port.uartclk = baud * 16;
403 port->port.rs485_config = platform->rs485_config;
406 * Setup the uart clock for the devices on expansion slot to
407 * half the clock speed of the main chip (which is 125MHz)
409 if (board->has_slave && idx >= 8)
410 port->port.uartclk /= 2;
412 ret = default_setup(priv, pcidev, idx, offset, port);
416 p = port->port.membase;
418 writeb(0x00, p + UART_EXAR_8XMODE);
419 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
420 writeb(128, p + UART_EXAR_TXTRG);
421 writeb(128, p + UART_EXAR_RXTRG);
424 /* Setup Multipurpose Input/Output pins. */
425 setup_gpio(pcidev, p);
427 ret = platform->register_gpio(pcidev, port);
433 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
435 struct exar8250 *priv = pci_get_drvdata(pcidev);
436 struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
437 struct platform_device *pdev = port->port.private_data;
439 platform_device_unregister(pdev);
440 port->port.private_data = NULL;
444 * These Exar UARTs have an extra interrupt indicator that could fire for a
445 * few interrupts that are not presented/cleared through IIR. One of which is
446 * a wakeup interrupt when coming out of sleep. These interrupts are only
447 * cleared by reading global INT0 or INT1 registers as interrupts are
448 * associated with channel 0. The INT[3:0] registers _are_ accessible from each
449 * channel's address space, but for the sake of bus efficiency we register a
450 * dedicated handler at the PCI device level to handle them.
452 static irqreturn_t exar_misc_handler(int irq, void *data)
454 struct exar8250 *priv = data;
456 /* Clear all PCI interrupts by reading INT0. No effect on IIR */
457 readb(priv->virt + UART_EXAR_INT0);
459 /* Clear INT0 for Expansion Interface slave ports, too */
460 if (priv->board->num_ports > 8)
461 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
467 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
469 unsigned int nr_ports, i, bar = 0, maxnr;
470 struct exar8250_board *board;
471 struct uart_8250_port uart;
472 struct exar8250 *priv;
475 board = (struct exar8250_board *)ent->driver_data;
479 rc = pcim_enable_device(pcidev);
483 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
485 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
487 priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
488 sizeof(unsigned int) * nr_ports,
494 priv->virt = pcim_iomap(pcidev, bar, 0);
498 pci_set_master(pcidev);
500 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
504 memset(&uart, 0, sizeof(uart));
505 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
507 uart.port.irq = pci_irq_vector(pcidev, 0);
508 uart.port.dev = &pcidev->dev;
510 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
511 IRQF_SHARED, "exar_uart", priv);
515 for (i = 0; i < nr_ports && i < maxnr; i++) {
516 rc = board->setup(priv, pcidev, &uart, i);
518 dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
522 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
523 uart.port.iobase, uart.port.irq, uart.port.iotype);
525 priv->line[i] = serial8250_register_8250_port(&uart);
526 if (priv->line[i] < 0) {
527 dev_err(&pcidev->dev,
528 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
529 uart.port.iobase, uart.port.irq,
530 uart.port.iotype, priv->line[i]);
535 pci_set_drvdata(pcidev, priv);
539 static void exar_pci_remove(struct pci_dev *pcidev)
541 struct exar8250 *priv = pci_get_drvdata(pcidev);
544 for (i = 0; i < priv->nr; i++)
545 serial8250_unregister_port(priv->line[i]);
547 if (priv->board->exit)
548 priv->board->exit(pcidev);
551 static int __maybe_unused exar_suspend(struct device *dev)
553 struct pci_dev *pcidev = to_pci_dev(dev);
554 struct exar8250 *priv = pci_get_drvdata(pcidev);
557 for (i = 0; i < priv->nr; i++)
558 if (priv->line[i] >= 0)
559 serial8250_suspend_port(priv->line[i]);
561 /* Ensure that every init quirk is properly torn down */
562 if (priv->board->exit)
563 priv->board->exit(pcidev);
568 static int __maybe_unused exar_resume(struct device *dev)
570 struct pci_dev *pcidev = to_pci_dev(dev);
571 struct exar8250 *priv = pci_get_drvdata(pcidev);
574 for (i = 0; i < priv->nr; i++)
575 if (priv->line[i] >= 0)
576 serial8250_resume_port(priv->line[i]);
581 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
583 static const struct exar8250_board acces_com_2x = {
585 .setup = pci_xr17c154_setup,
588 static const struct exar8250_board acces_com_4x = {
590 .setup = pci_xr17c154_setup,
593 static const struct exar8250_board acces_com_8x = {
595 .setup = pci_xr17c154_setup,
599 static const struct exar8250_board pbn_fastcom335_2 = {
601 .setup = pci_fastcom335_setup,
604 static const struct exar8250_board pbn_fastcom335_4 = {
606 .setup = pci_fastcom335_setup,
609 static const struct exar8250_board pbn_fastcom335_8 = {
611 .setup = pci_fastcom335_setup,
614 static const struct exar8250_board pbn_connect = {
615 .setup = pci_connect_tech_setup,
618 static const struct exar8250_board pbn_exar_ibm_saturn = {
620 .setup = pci_xr17c154_setup,
623 static const struct exar8250_board pbn_exar_XR17C15x = {
624 .setup = pci_xr17c154_setup,
627 static const struct exar8250_board pbn_exar_XR17V35x = {
628 .setup = pci_xr17v35x_setup,
629 .exit = pci_xr17v35x_exit,
632 static const struct exar8250_board pbn_fastcom35x_2 = {
634 .setup = pci_xr17v35x_setup,
635 .exit = pci_xr17v35x_exit,
638 static const struct exar8250_board pbn_fastcom35x_4 = {
640 .setup = pci_xr17v35x_setup,
641 .exit = pci_xr17v35x_exit,
644 static const struct exar8250_board pbn_fastcom35x_8 = {
646 .setup = pci_xr17v35x_setup,
647 .exit = pci_xr17v35x_exit,
650 static const struct exar8250_board pbn_exar_XR17V4358 = {
653 .setup = pci_xr17v35x_setup,
654 .exit = pci_xr17v35x_exit,
657 static const struct exar8250_board pbn_exar_XR17V8358 = {
660 .setup = pci_xr17v35x_setup,
661 .exit = pci_xr17v35x_exit,
664 #define CONNECT_DEVICE(devid, sdevid, bd) { \
666 PCI_VENDOR_ID_EXAR, \
667 PCI_DEVICE_ID_EXAR_##devid, \
668 PCI_SUBVENDOR_ID_CONNECT_TECH, \
669 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \
670 (kernel_ulong_t)&bd \
673 #define EXAR_DEVICE(vend, devid, bd) { \
674 PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \
677 #define IBM_DEVICE(devid, sdevid, bd) { \
679 PCI_VENDOR_ID_EXAR, \
680 PCI_DEVICE_ID_EXAR_##devid, \
682 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \
683 (kernel_ulong_t)&bd \
686 static const struct pci_device_id exar_pci_tbl[] = {
687 EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
688 EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
689 EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
690 EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
691 EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
692 EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
693 EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
696 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
697 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
698 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
699 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
700 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
701 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
702 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
703 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
704 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
705 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
706 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
707 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
709 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
711 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
712 EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
713 EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
714 EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
716 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
717 EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
718 EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
719 EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
720 EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
721 EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
722 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_fastcom35x_2),
723 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_fastcom35x_4),
724 EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_fastcom35x_8),
726 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
727 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
728 EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
729 EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
732 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
734 static struct pci_driver exar_pci_driver = {
735 .name = "exar_serial",
736 .probe = exar_pci_probe,
737 .remove = exar_pci_remove,
741 .id_table = exar_pci_tbl,
743 module_pci_driver(exar_pci_driver);
745 MODULE_LICENSE("GPL");
746 MODULE_DESCRIPTION("Exar Serial Driver");
747 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");