2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
162 static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
183 static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
199 static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
210 static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
214 static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
218 static int sClockPrescale = 0x14;
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
228 /***** RocketPort Static Prototypes *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param_hw(board1, ulong, ioport, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param_hw(board2, ulong, ioport, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param_hw(board3, ulong, ioport, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param_hw(board4, ulong, ioport, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param_hw(controller, ulong, ioport, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
282 static int __init rp_init(void);
283 static void rp_cleanup_module(void);
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
289 MODULE_LICENSE("Dual BSD/GPL");
291 /*************************************************************************/
292 /* Module code starts here */
294 static inline int rocket_paranoia_check(struct r_port *info,
297 #ifdef ROCKET_PARANOIA_CHECK
300 if (info->magic != RPORT_MAGIC) {
301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
310 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
317 unsigned int CharNStat;
318 int ToRecv, wRecv, space;
321 ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Entering STATMODE...\n");
338 ChanStatus |= STATMODE;
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
348 if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
356 CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358 printk(KERN_INFO "%x...\n", CharNStat);
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
369 else if (CharNStat & STMPARITYH)
371 else if (CharNStat & STMFRAMEH)
373 else if (CharNStat & STMRCVROVRH)
377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
386 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
390 sDisRxStatusMode(cp);
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
413 /* Push the data up to the tty layer */
414 tty_flip_buffer_push(&info->port);
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
423 static void rp_do_transmit(struct r_port *info)
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
430 #ifdef ROCKET_DEBUG_INTR
431 printk(KERN_DEBUG "%s\n", __func__);
435 tty = tty_port_tty_get(&info->port);
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
443 spin_lock_irqsave(&info->slock, flags);
444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
446 /* Loop sending data to FIFO until done or FIFO full */
450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452 if (c <= 0 || info->xmit_fifo_room <= 0)
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
460 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
469 if (info->xmit_cnt < WAKEUP_CHARS) {
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
476 spin_unlock_irqrestore(&info->slock, flags);
479 #ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
490 static void rp_handle_port(struct r_port *info)
493 unsigned int IntMask, ChanStatus;
498 if (!tty_port_initialized(&info->port)) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
506 IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
512 rp_do_receive(info, cp, ChanStatus);
514 if (IntMask & DELTA_CD) { /* CD change */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517 (ChanStatus & CD_ACT) ? "on" : "off");
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
523 tty_port_tty_hangup(&info->port, false);
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526 wake_up_interruptible(&info->port.open_wait);
528 #ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
541 static void rp_do_poll(unsigned long dummy)
544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
546 unsigned int CtlMask;
547 unsigned char AiopMask;
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
558 /* Get the interrupt status from the board */
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
564 CtlMask = sGetControllerIntStatus(ctlp);
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
586 xmitmask = xmit_flags[ctrl];
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
607 * Reset the timer so we get called at the next clock tick (10ms).
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
614 * Initializes the r_port structure for a port, as well as enabling the port on
616 * Inputs: board, aiop, chan numbers
619 init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
626 /* Get the next available line number */
627 line = SetLineNumber(board, aiop, chan);
629 ctlp = sCtlNumToCtlPtr(board);
631 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
632 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
634 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
639 info->magic = RPORT_MAGIC;
645 tty_port_init(&info->port);
646 info->port.ops = &rocket_port_ops;
647 info->flags &= ~ROCKET_MODE_MASK;
648 if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
649 switch (pc104[board][line]) {
651 info->flags |= ROCKET_MODE_RS422;
654 info->flags |= ROCKET_MODE_RS485;
658 info->flags |= ROCKET_MODE_RS232;
662 info->flags |= ROCKET_MODE_RS232;
664 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
665 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
666 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
668 tty_port_destroy(&info->port);
673 rocketMode = info->flags & ROCKET_MODE_MASK;
675 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
676 sEnRTSToggle(&info->channel);
678 sDisRTSToggle(&info->channel);
680 if (ctlp->boardType == ROCKET_TYPE_PC104) {
681 switch (rocketMode) {
682 case ROCKET_MODE_RS485:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
685 case ROCKET_MODE_RS422:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
688 case ROCKET_MODE_RS232:
690 if (info->flags & ROCKET_RTS_TOGGLE)
691 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
693 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
697 spin_lock_init(&info->slock);
698 mutex_init(&info->write_mtx);
699 rp_table[line] = info;
700 tty_port_register_device(&info->port, rocket_driver, line,
701 pci_dev ? &pci_dev->dev : NULL);
705 * Configures a rocketport port according to its termio settings. Called from
706 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
708 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
709 struct ktermios *old_termios)
714 int bits, baud, divisor;
716 struct ktermios *t = &tty->termios;
721 /* Byte size and parity */
722 if ((cflag & CSIZE) == CS8) {
729 if (cflag & CSTOPB) {
736 if (cflag & PARENB) {
739 if (cflag & PARODD) {
749 baud = tty_get_baud_rate(tty);
752 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
753 if ((divisor >= 8192 || divisor < 0) && old_termios) {
754 baud = tty_termios_baud_rate(old_termios);
757 divisor = (rp_baud_base[info->board] / baud) - 1;
759 if (divisor >= 8192 || divisor < 0) {
761 divisor = (rp_baud_base[info->board] / baud) - 1;
763 info->cps = baud / bits;
764 sSetBaud(cp, divisor);
766 /* FIXME: Should really back compute a baud rate from the divisor */
767 tty_encode_baud_rate(tty, baud, baud);
769 if (cflag & CRTSCTS) {
770 info->intmask |= DELTA_CTS;
773 info->intmask &= ~DELTA_CTS;
776 if (cflag & CLOCAL) {
777 info->intmask &= ~DELTA_CD;
779 spin_lock_irqsave(&info->slock, flags);
780 if (sGetChanStatus(cp) & CD_ACT)
784 info->intmask |= DELTA_CD;
785 spin_unlock_irqrestore(&info->slock, flags);
789 * Handle software flow control in the board
791 #ifdef ROCKET_SOFT_FLOW
793 sEnTxSoftFlowCtl(cp);
799 sSetTxXONChar(cp, START_CHAR(tty));
800 sSetTxXOFFChar(cp, STOP_CHAR(tty));
802 sDisTxSoftFlowCtl(cp);
809 * Set up ignore/read mask words
811 info->read_status_mask = STMRCVROVRH | 0xFF;
813 info->read_status_mask |= STMFRAMEH | STMPARITYH;
814 if (I_BRKINT(tty) || I_PARMRK(tty))
815 info->read_status_mask |= STMBREAKH;
818 * Characters to ignore
820 info->ignore_status_mask = 0;
822 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
824 info->ignore_status_mask |= STMBREAKH;
826 * If we're ignoring parity and break indicators,
827 * ignore overruns too. (For real raw support).
830 info->ignore_status_mask |= STMRCVROVRH;
833 rocketMode = info->flags & ROCKET_MODE_MASK;
835 if ((info->flags & ROCKET_RTS_TOGGLE)
836 || (rocketMode == ROCKET_MODE_RS485))
841 sSetRTS(&info->channel);
843 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
844 switch (rocketMode) {
845 case ROCKET_MODE_RS485:
846 sSetInterfaceMode(cp, InterfaceModeRS485);
848 case ROCKET_MODE_RS422:
849 sSetInterfaceMode(cp, InterfaceModeRS422);
851 case ROCKET_MODE_RS232:
853 if (info->flags & ROCKET_RTS_TOGGLE)
854 sSetInterfaceMode(cp, InterfaceModeRS232T);
856 sSetInterfaceMode(cp, InterfaceModeRS232);
862 static int carrier_raised(struct tty_port *port)
864 struct r_port *info = container_of(port, struct r_port, port);
865 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
868 static void dtr_rts(struct tty_port *port, int on)
870 struct r_port *info = container_of(port, struct r_port, port);
872 sSetDTR(&info->channel);
873 sSetRTS(&info->channel);
875 sClrDTR(&info->channel);
876 sClrRTS(&info->channel);
881 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
882 * port's r_port struct. Initializes the port hardware.
884 static int rp_open(struct tty_struct *tty, struct file *filp)
887 struct tty_port *port;
892 info = rp_table[tty->index];
897 page = __get_free_page(GFP_KERNEL);
902 * We must not sleep from here until the port is marked fully in use.
907 info->xmit_buf = (unsigned char *) page;
909 tty->driver_data = info;
910 tty_port_tty_set(port, tty);
912 if (port->count++ == 0) {
913 atomic_inc(&rp_num_ports_open);
915 #ifdef ROCKET_DEBUG_OPEN
916 printk(KERN_INFO "rocket mod++ = %d...\n",
917 atomic_read(&rp_num_ports_open));
920 #ifdef ROCKET_DEBUG_OPEN
921 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
925 * Info->count is now 1; so it's safe to sleep now.
927 if (!tty_port_initialized(port)) {
929 sSetRxTrigger(cp, TRIG_1);
930 if (sGetChanStatus(cp) & CD_ACT)
934 sDisRxStatusMode(cp);
938 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
939 sSetRxTrigger(cp, TRIG_1);
942 sDisRxStatusMode(cp);
946 sDisTxSoftFlowCtl(cp);
951 tty_port_set_initialized(&info->port, 1);
953 configure_r_port(tty, info, NULL);
959 /* Starts (or resets) the maint polling loop */
960 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
962 retval = tty_port_block_til_ready(port, tty, filp);
964 #ifdef ROCKET_DEBUG_OPEN
965 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
973 * Exception handler that closes a serial port. info->port.count is considered critical.
975 static void rp_close(struct tty_struct *tty, struct file *filp)
977 struct r_port *info = tty->driver_data;
978 struct tty_port *port = &info->port;
982 if (rocket_paranoia_check(info, "rp_close"))
985 #ifdef ROCKET_DEBUG_OPEN
986 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
989 if (tty_port_close_start(port, tty, filp) == 0)
992 mutex_lock(&port->mutex);
995 * Before we drop DTR, make sure the UART transmitter
996 * has completely drained; this is especially
997 * important if there is a transmit FIFO!
999 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1002 rp_wait_until_sent(tty, timeout);
1003 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1006 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1008 sDisTxSoftFlowCtl(cp);
1016 rp_flush_buffer(tty);
1018 tty_ldisc_flush(tty);
1020 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1022 /* We can't yet use tty_port_close_end as the buffer handling in this
1023 driver is a bit different to the usual */
1025 if (port->blocked_open) {
1026 if (port->close_delay) {
1027 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1029 wake_up_interruptible(&port->open_wait);
1031 if (info->xmit_buf) {
1032 free_page((unsigned long) info->xmit_buf);
1033 info->xmit_buf = NULL;
1036 spin_lock_irq(&port->lock);
1038 spin_unlock_irq(&port->lock);
1039 tty_port_set_initialized(port, 0);
1040 tty_port_set_active(port, 0);
1041 mutex_unlock(&port->mutex);
1042 tty_port_tty_set(port, NULL);
1044 atomic_dec(&rp_num_ports_open);
1046 #ifdef ROCKET_DEBUG_OPEN
1047 printk(KERN_INFO "rocket mod-- = %d...\n",
1048 atomic_read(&rp_num_ports_open));
1049 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1054 static void rp_set_termios(struct tty_struct *tty,
1055 struct ktermios *old_termios)
1057 struct r_port *info = tty->driver_data;
1061 if (rocket_paranoia_check(info, "rp_set_termios"))
1064 cflag = tty->termios.c_cflag;
1067 * This driver doesn't support CS5 or CS6
1069 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1070 tty->termios.c_cflag =
1071 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1073 tty->termios.c_cflag &= ~CMSPAR;
1075 configure_r_port(tty, info, old_termios);
1077 cp = &info->channel;
1079 /* Handle transition to B0 status */
1080 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1085 /* Handle transition away from B0 status */
1086 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1091 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1095 static int rp_break(struct tty_struct *tty, int break_state)
1097 struct r_port *info = tty->driver_data;
1098 unsigned long flags;
1100 if (rocket_paranoia_check(info, "rp_break"))
1103 spin_lock_irqsave(&info->slock, flags);
1104 if (break_state == -1)
1105 sSendBreak(&info->channel);
1107 sClrBreak(&info->channel);
1108 spin_unlock_irqrestore(&info->slock, flags);
1113 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1114 * the UPCI boards was added, it was decided to make this a function because
1115 * the macro was getting too complicated. All cases except the first one
1116 * (UPCIRingInd) are taken directly from the original macro.
1118 static int sGetChanRI(CHANNEL_T * ChP)
1120 CONTROLLER_t *CtlP = ChP->CtlP;
1121 int ChanNum = ChP->ChanNum;
1124 if (CtlP->UPCIRingInd)
1125 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1126 else if (CtlP->AltChanRingIndicator)
1127 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1128 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1129 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1134 /********************************************************************************************/
1135 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1138 * Returns the state of the serial modem control lines. These next 2 functions
1139 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1141 static int rp_tiocmget(struct tty_struct *tty)
1143 struct r_port *info = tty->driver_data;
1144 unsigned int control, result, ChanStatus;
1146 ChanStatus = sGetChanStatusLo(&info->channel);
1147 control = info->channel.TxControl[3];
1148 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1149 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1150 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1151 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1152 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1153 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1159 * Sets the modem control lines
1161 static int rp_tiocmset(struct tty_struct *tty,
1162 unsigned int set, unsigned int clear)
1164 struct r_port *info = tty->driver_data;
1166 if (set & TIOCM_RTS)
1167 info->channel.TxControl[3] |= SET_RTS;
1168 if (set & TIOCM_DTR)
1169 info->channel.TxControl[3] |= SET_DTR;
1170 if (clear & TIOCM_RTS)
1171 info->channel.TxControl[3] &= ~SET_RTS;
1172 if (clear & TIOCM_DTR)
1173 info->channel.TxControl[3] &= ~SET_DTR;
1175 out32(info->channel.IndexAddr, info->channel.TxControl);
1179 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1181 struct rocket_config tmp;
1183 memset(&tmp, 0, sizeof (tmp));
1184 mutex_lock(&info->port.mutex);
1185 tmp.line = info->line;
1186 tmp.flags = info->flags;
1187 tmp.close_delay = info->port.close_delay;
1188 tmp.closing_wait = info->port.closing_wait;
1189 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1190 mutex_unlock(&info->port.mutex);
1192 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1197 static int set_config(struct tty_struct *tty, struct r_port *info,
1198 struct rocket_config __user *new_info)
1200 struct rocket_config new_serial;
1202 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1205 mutex_lock(&info->port.mutex);
1206 if (!capable(CAP_SYS_ADMIN))
1208 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1209 mutex_unlock(&info->port.mutex);
1212 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1213 mutex_unlock(&info->port.mutex);
1217 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1218 /* warn about deprecation, unless clearing */
1219 if (new_serial.flags & ROCKET_SPD_MASK)
1220 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1223 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1224 info->port.close_delay = new_serial.close_delay;
1225 info->port.closing_wait = new_serial.closing_wait;
1227 mutex_unlock(&info->port.mutex);
1229 configure_r_port(tty, info, NULL);
1234 * This function fills in a rocket_ports struct with information
1235 * about what boards/ports are in the system. This info is passed
1236 * to user space. See setrocket.c where the info is used to create
1237 * the /dev/ttyRx ports.
1239 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1241 struct rocket_ports tmp;
1244 memset(&tmp, 0, sizeof (tmp));
1245 tmp.tty_major = rocket_driver->major;
1247 for (board = 0; board < 4; board++) {
1248 tmp.rocketModel[board].model = rocketModel[board].model;
1249 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1250 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1251 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1252 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1254 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1259 static int reset_rm2(struct r_port *info, void __user *arg)
1263 if (!capable(CAP_SYS_ADMIN))
1266 if (copy_from_user(&reset, arg, sizeof (int)))
1271 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1272 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1275 if (info->ctlp->BusType == isISA)
1276 sModemReset(info->ctlp, info->chan, reset);
1278 sPCIModemReset(info->ctlp, info->chan, reset);
1283 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1285 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1290 /* IOCTL call handler into the driver */
1291 static int rp_ioctl(struct tty_struct *tty,
1292 unsigned int cmd, unsigned long arg)
1294 struct r_port *info = tty->driver_data;
1295 void __user *argp = (void __user *)arg;
1298 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1302 case RCKP_GET_STRUCT:
1303 if (copy_to_user(argp, info, sizeof (struct r_port)))
1306 case RCKP_GET_CONFIG:
1307 ret = get_config(info, argp);
1309 case RCKP_SET_CONFIG:
1310 ret = set_config(tty, info, argp);
1312 case RCKP_GET_PORTS:
1313 ret = get_ports(info, argp);
1315 case RCKP_RESET_RM2:
1316 ret = reset_rm2(info, argp);
1318 case RCKP_GET_VERSION:
1319 ret = get_version(info, argp);
1327 static void rp_send_xchar(struct tty_struct *tty, char ch)
1329 struct r_port *info = tty->driver_data;
1332 if (rocket_paranoia_check(info, "rp_send_xchar"))
1335 cp = &info->channel;
1337 sWriteTxPrioByte(cp, ch);
1339 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1342 static void rp_throttle(struct tty_struct *tty)
1344 struct r_port *info = tty->driver_data;
1346 #ifdef ROCKET_DEBUG_THROTTLE
1347 printk(KERN_INFO "throttle %s ....\n", tty->name);
1350 if (rocket_paranoia_check(info, "rp_throttle"))
1354 rp_send_xchar(tty, STOP_CHAR(tty));
1356 sClrRTS(&info->channel);
1359 static void rp_unthrottle(struct tty_struct *tty)
1361 struct r_port *info = tty->driver_data;
1362 #ifdef ROCKET_DEBUG_THROTTLE
1363 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1366 if (rocket_paranoia_check(info, "rp_unthrottle"))
1370 rp_send_xchar(tty, START_CHAR(tty));
1372 sSetRTS(&info->channel);
1376 * ------------------------------------------------------------
1377 * rp_stop() and rp_start()
1379 * This routines are called before setting or resetting tty->stopped.
1380 * They enable or disable transmitter interrupts, as necessary.
1381 * ------------------------------------------------------------
1383 static void rp_stop(struct tty_struct *tty)
1385 struct r_port *info = tty->driver_data;
1387 #ifdef ROCKET_DEBUG_FLOW
1388 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1389 info->xmit_cnt, info->xmit_fifo_room);
1392 if (rocket_paranoia_check(info, "rp_stop"))
1395 if (sGetTxCnt(&info->channel))
1396 sDisTransmit(&info->channel);
1399 static void rp_start(struct tty_struct *tty)
1401 struct r_port *info = tty->driver_data;
1403 #ifdef ROCKET_DEBUG_FLOW
1404 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1405 info->xmit_cnt, info->xmit_fifo_room);
1408 if (rocket_paranoia_check(info, "rp_stop"))
1411 sEnTransmit(&info->channel);
1412 set_bit((info->aiop * 8) + info->chan,
1413 (void *) &xmit_flags[info->board]);
1417 * rp_wait_until_sent() --- wait until the transmitter is empty
1419 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1421 struct r_port *info = tty->driver_data;
1423 unsigned long orig_jiffies;
1424 int check_time, exit_time;
1427 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1430 cp = &info->channel;
1432 orig_jiffies = jiffies;
1433 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1434 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1436 printk(KERN_INFO "cps=%d...\n", info->cps);
1439 txcnt = sGetTxCnt(cp);
1441 if (sGetChanStatusLo(cp) & TXSHRMT)
1443 check_time = (HZ / info->cps) / 5;
1445 check_time = HZ * txcnt / info->cps;
1448 exit_time = orig_jiffies + timeout - jiffies;
1451 if (exit_time < check_time)
1452 check_time = exit_time;
1454 if (check_time == 0)
1456 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1457 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1458 jiffies, check_time);
1460 msleep_interruptible(jiffies_to_msecs(check_time));
1461 if (signal_pending(current))
1464 __set_current_state(TASK_RUNNING);
1465 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1466 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1471 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1473 static void rp_hangup(struct tty_struct *tty)
1476 struct r_port *info = tty->driver_data;
1477 unsigned long flags;
1479 if (rocket_paranoia_check(info, "rp_hangup"))
1482 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1483 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1485 rp_flush_buffer(tty);
1486 spin_lock_irqsave(&info->port.lock, flags);
1487 if (info->port.count)
1488 atomic_dec(&rp_num_ports_open);
1489 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1490 spin_unlock_irqrestore(&info->port.lock, flags);
1492 tty_port_hangup(&info->port);
1494 cp = &info->channel;
1497 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1499 sDisTxSoftFlowCtl(cp);
1501 tty_port_set_initialized(&info->port, 0);
1503 wake_up_interruptible(&info->port.open_wait);
1507 * Exception handler - write char routine. The RocketPort driver uses a
1508 * double-buffering strategy, with the twist that if the in-memory CPU
1509 * buffer is empty, and there's space in the transmit FIFO, the
1510 * writing routines will write directly to transmit FIFO.
1511 * Write buffer and counters protected by spinlocks
1513 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1515 struct r_port *info = tty->driver_data;
1517 unsigned long flags;
1519 if (rocket_paranoia_check(info, "rp_put_char"))
1523 * Grab the port write mutex, locking out other processes that try to
1524 * write to this port
1526 mutex_lock(&info->write_mtx);
1528 #ifdef ROCKET_DEBUG_WRITE
1529 printk(KERN_INFO "rp_put_char %c...\n", ch);
1532 spin_lock_irqsave(&info->slock, flags);
1533 cp = &info->channel;
1535 if (!tty->stopped && info->xmit_fifo_room == 0)
1536 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1538 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1539 info->xmit_buf[info->xmit_head++] = ch;
1540 info->xmit_head &= XMIT_BUF_SIZE - 1;
1542 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1544 sOutB(sGetTxRxDataIO(cp), ch);
1545 info->xmit_fifo_room--;
1547 spin_unlock_irqrestore(&info->slock, flags);
1548 mutex_unlock(&info->write_mtx);
1553 * Exception handler - write routine, called when user app writes to the device.
1554 * A per port write mutex is used to protect from another process writing to
1555 * this port at the same time. This other process could be running on the other CPU
1556 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1557 * Spinlocks protect the info xmit members.
1559 static int rp_write(struct tty_struct *tty,
1560 const unsigned char *buf, int count)
1562 struct r_port *info = tty->driver_data;
1564 const unsigned char *b;
1566 unsigned long flags;
1568 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1571 if (mutex_lock_interruptible(&info->write_mtx))
1572 return -ERESTARTSYS;
1574 #ifdef ROCKET_DEBUG_WRITE
1575 printk(KERN_INFO "rp_write %d chars...\n", count);
1577 cp = &info->channel;
1579 if (!tty->stopped && info->xmit_fifo_room < count)
1580 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1583 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1584 * into FIFO. Use the write queue for temp storage.
1586 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1587 c = min(count, info->xmit_fifo_room);
1590 /* Push data into FIFO, 2 bytes at a time */
1591 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1593 /* If there is a byte remaining, write it */
1595 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1601 spin_lock_irqsave(&info->slock, flags);
1602 info->xmit_fifo_room -= c;
1603 spin_unlock_irqrestore(&info->slock, flags);
1606 /* If count is zero, we wrote it all and are done */
1610 /* Write remaining data into the port's xmit_buf */
1613 if (!tty_port_active(&info->port))
1615 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1616 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1621 memcpy(info->xmit_buf + info->xmit_head, b, c);
1623 spin_lock_irqsave(&info->slock, flags);
1625 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1626 info->xmit_cnt += c;
1627 spin_unlock_irqrestore(&info->slock, flags);
1634 if ((retval > 0) && !tty->stopped)
1635 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1638 if (info->xmit_cnt < WAKEUP_CHARS) {
1640 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1641 wake_up_interruptible(&tty->poll_wait);
1644 mutex_unlock(&info->write_mtx);
1649 * Return the number of characters that can be sent. We estimate
1650 * only using the in-memory transmit buffer only, and ignore the
1651 * potential space in the transmit FIFO.
1653 static int rp_write_room(struct tty_struct *tty)
1655 struct r_port *info = tty->driver_data;
1658 if (rocket_paranoia_check(info, "rp_write_room"))
1661 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1664 #ifdef ROCKET_DEBUG_WRITE
1665 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1671 * Return the number of characters in the buffer. Again, this only
1672 * counts those characters in the in-memory transmit buffer.
1674 static int rp_chars_in_buffer(struct tty_struct *tty)
1676 struct r_port *info = tty->driver_data;
1678 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1681 #ifdef ROCKET_DEBUG_WRITE
1682 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1684 return info->xmit_cnt;
1688 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1689 * r_port struct for the port. Note that spinlock are used to protect info members,
1690 * do not call this function if the spinlock is already held.
1692 static void rp_flush_buffer(struct tty_struct *tty)
1694 struct r_port *info = tty->driver_data;
1696 unsigned long flags;
1698 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1701 spin_lock_irqsave(&info->slock, flags);
1702 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1703 spin_unlock_irqrestore(&info->slock, flags);
1705 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1706 wake_up_interruptible(&tty->poll_wait);
1710 cp = &info->channel;
1716 static const struct pci_device_id rocket_pci_ids[] = {
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1723 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1724 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1725 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1726 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1727 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1728 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1729 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1730 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1731 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1732 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1738 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1741 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1743 /* Resets the speaker controller on RocketModem II and III devices */
1744 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1748 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1749 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1750 addr = CtlP->AiopIO[0] + 0x4F;
1754 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1755 if ((model == MODEL_UPCI_RM3_8PORT)
1756 || (model == MODEL_UPCI_RM3_4PORT)) {
1757 addr = CtlP->AiopIO[0] + 0x88;
1762 /***************************************************************************
1763 Function: sPCIInitController
1764 Purpose: Initialization of controller global registers and controller
1766 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1767 IRQNum,Frequency,PeriodicOnly)
1768 CONTROLLER_T *CtlP; Ptr to controller structure
1769 int CtlNum; Controller number
1770 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1771 This list must be in the order the AIOPs will be found on the
1772 controller. Once an AIOP in the list is not found, it is
1773 assumed that there are no more AIOPs on the controller.
1774 int AiopIOListSize; Number of addresses in AiopIOList
1775 int IRQNum; Interrupt Request number. Can be any of the following:
1776 0: Disable global interrupts
1785 Byte_t Frequency: A flag identifying the frequency
1786 of the periodic interrupt, can be any one of the following:
1787 FREQ_DIS - periodic interrupt disabled
1788 FREQ_137HZ - 137 Hertz
1789 FREQ_69HZ - 69 Hertz
1790 FREQ_34HZ - 34 Hertz
1791 FREQ_17HZ - 17 Hertz
1794 If IRQNum is set to 0 the Frequency parameter is
1795 overidden, it is forced to a value of FREQ_DIS.
1796 int PeriodicOnly: 1 if all interrupts except the periodic
1797 interrupt are to be blocked.
1798 0 is both the periodic interrupt and
1799 other channel interrupts are allowed.
1800 If IRQNum is set to 0 the PeriodicOnly parameter is
1801 overidden, it is forced to a value of 0.
1802 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1803 initialization failed.
1806 If periodic interrupts are to be disabled but AIOP interrupts
1807 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1809 If interrupts are to be completely disabled set IRQNum to 0.
1811 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1812 invalid combination.
1814 This function performs initialization of global interrupt modes,
1815 but it does not actually enable global interrupts. To enable
1816 and disable global interrupts use functions sEnGlobalInt() and
1817 sDisGlobalInt(). Enabling of global interrupts is normally not
1818 done until all other initializations are complete.
1820 Even if interrupts are globally enabled, they must also be
1821 individually enabled for each channel that is to generate
1824 Warnings: No range checking on any of the parameters is done.
1826 No context switches are allowed while executing this function.
1828 After this function all AIOPs on the controller are disabled,
1829 they can be enabled with sEnAiop().
1831 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1832 ByteIO_t * AiopIOList, int AiopIOListSize,
1833 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1834 int PeriodicOnly, int altChanRingIndicator,
1840 CtlP->AltChanRingIndicator = altChanRingIndicator;
1841 CtlP->UPCIRingInd = UPCIRingInd;
1842 CtlP->CtlNum = CtlNum;
1843 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1844 CtlP->BusType = isPCI; /* controller release 1 */
1848 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1849 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1850 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1854 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1855 CtlP->AiopIntrBits = aiop_intr_bits;
1858 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1861 for (i = 0; i < AiopIOListSize; i++) {
1863 CtlP->AiopIO[i] = (WordIO_t) io;
1864 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1866 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1867 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1868 break; /* done looking for AIOPs */
1870 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1871 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1872 sOutB(io + _INDX_DATA, sClockPrescale);
1873 CtlP->NumAiop++; /* bump count of AIOPs */
1876 if (CtlP->NumAiop == 0)
1879 return (CtlP->NumAiop);
1883 * Called when a PCI card is found. Retrieves and stores model information,
1884 * init's aiopic and serial port hardware.
1885 * Inputs: i is the board number (0-n)
1887 static __init int register_PCI(int i, struct pci_dev *dev)
1889 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1890 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1894 int altChanRingIndicator = 0;
1895 int ports_per_aiop = 8;
1896 WordIO_t ConfigIO = 0;
1897 ByteIO_t UPCIRingInd = 0;
1899 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1900 pci_enable_device(dev) || i >= NUM_BOARDS)
1903 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1905 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1906 rocketModel[i].loadrm2 = 0;
1907 rocketModel[i].startingPortNumber = nextLineNumber;
1909 /* Depending on the model, set up some config variables */
1910 switch (dev->device) {
1911 case PCI_DEVICE_ID_RP4QUAD:
1914 rocketModel[i].model = MODEL_RP4QUAD;
1915 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1916 rocketModel[i].numPorts = 4;
1918 case PCI_DEVICE_ID_RP8OCTA:
1920 rocketModel[i].model = MODEL_RP8OCTA;
1921 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1922 rocketModel[i].numPorts = 8;
1924 case PCI_DEVICE_ID_URP8OCTA:
1926 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1927 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1928 rocketModel[i].numPorts = 8;
1930 case PCI_DEVICE_ID_RP8INTF:
1932 rocketModel[i].model = MODEL_RP8INTF;
1933 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1934 rocketModel[i].numPorts = 8;
1936 case PCI_DEVICE_ID_URP8INTF:
1938 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1939 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1940 rocketModel[i].numPorts = 8;
1942 case PCI_DEVICE_ID_RP8J:
1944 rocketModel[i].model = MODEL_RP8J;
1945 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1946 rocketModel[i].numPorts = 8;
1948 case PCI_DEVICE_ID_RP4J:
1951 rocketModel[i].model = MODEL_RP4J;
1952 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1953 rocketModel[i].numPorts = 4;
1955 case PCI_DEVICE_ID_RP8SNI:
1957 rocketModel[i].model = MODEL_RP8SNI;
1958 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1959 rocketModel[i].numPorts = 8;
1961 case PCI_DEVICE_ID_RP16SNI:
1963 rocketModel[i].model = MODEL_RP16SNI;
1964 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1965 rocketModel[i].numPorts = 16;
1967 case PCI_DEVICE_ID_RP16INTF:
1969 rocketModel[i].model = MODEL_RP16INTF;
1970 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1971 rocketModel[i].numPorts = 16;
1973 case PCI_DEVICE_ID_URP16INTF:
1975 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1976 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1977 rocketModel[i].numPorts = 16;
1979 case PCI_DEVICE_ID_CRP16INTF:
1981 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1982 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1983 rocketModel[i].numPorts = 16;
1985 case PCI_DEVICE_ID_RP32INTF:
1987 rocketModel[i].model = MODEL_RP32INTF;
1988 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1989 rocketModel[i].numPorts = 32;
1991 case PCI_DEVICE_ID_URP32INTF:
1993 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1994 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1995 rocketModel[i].numPorts = 32;
1997 case PCI_DEVICE_ID_RPP4:
2000 altChanRingIndicator++;
2002 rocketModel[i].model = MODEL_RPP4;
2003 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2004 rocketModel[i].numPorts = 4;
2006 case PCI_DEVICE_ID_RPP8:
2009 altChanRingIndicator++;
2011 rocketModel[i].model = MODEL_RPP8;
2012 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2013 rocketModel[i].numPorts = 8;
2015 case PCI_DEVICE_ID_RP2_232:
2018 altChanRingIndicator++;
2020 rocketModel[i].model = MODEL_RP2_232;
2021 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2022 rocketModel[i].numPorts = 2;
2024 case PCI_DEVICE_ID_RP2_422:
2027 altChanRingIndicator++;
2029 rocketModel[i].model = MODEL_RP2_422;
2030 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2031 rocketModel[i].numPorts = 2;
2033 case PCI_DEVICE_ID_RP6M:
2038 /* If revision is 1, the rocketmodem flash must be loaded.
2039 * If it is 2 it is a "socketed" version. */
2040 if (dev->revision == 1) {
2041 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2042 rocketModel[i].loadrm2 = 1;
2044 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2047 rocketModel[i].model = MODEL_RP6M;
2048 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2049 rocketModel[i].numPorts = 6;
2051 case PCI_DEVICE_ID_RP4M:
2054 if (dev->revision == 1) {
2055 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2056 rocketModel[i].loadrm2 = 1;
2058 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2061 rocketModel[i].model = MODEL_RP4M;
2062 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2063 rocketModel[i].numPorts = 4;
2071 * Check for UPCI boards.
2074 switch (dev->device) {
2075 case PCI_DEVICE_ID_URP32INTF:
2076 case PCI_DEVICE_ID_URP8INTF:
2077 case PCI_DEVICE_ID_URP16INTF:
2078 case PCI_DEVICE_ID_CRP16INTF:
2079 case PCI_DEVICE_ID_URP8OCTA:
2080 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2081 ConfigIO = pci_resource_start(dev, 1);
2082 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2083 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2086 * Check for octa or quad cable.
2089 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2090 PCI_GPIO_CTRL_8PORT)) {
2092 rocketModel[i].numPorts = 4;
2096 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2098 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2099 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2100 rocketModel[i].numPorts = 8;
2101 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2102 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2103 ConfigIO = pci_resource_start(dev, 1);
2104 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2106 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2108 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2109 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2110 rocketModel[i].numPorts = 4;
2111 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2112 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2113 ConfigIO = pci_resource_start(dev, 1);
2114 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2121 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2122 rp_baud_base[i] = 921600;
2125 * If support_low_speed is set, use the slow clock
2126 * prescale, which supports 50 bps
2128 if (support_low_speed) {
2129 /* mod 9 (divide by 10) prescale */
2130 sClockPrescale = 0x19;
2131 rp_baud_base[i] = 230400;
2133 /* mod 4 (divide by 5) prescale */
2134 sClockPrescale = 0x14;
2135 rp_baud_base[i] = 460800;
2139 for (aiop = 0; aiop < max_num_aiops; aiop++)
2140 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2141 ctlp = sCtlNumToCtlPtr(i);
2142 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2143 for (aiop = 0; aiop < max_num_aiops; aiop++)
2144 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2146 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2147 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2148 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2149 rocketModel[i].startingPortNumber,
2150 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2152 if (num_aiops <= 0) {
2153 rcktpt_io_addr[i] = 0;
2158 /* Reset the AIOPIC, init the serial ports */
2159 for (aiop = 0; aiop < num_aiops; aiop++) {
2160 sResetAiopByNum(ctlp, aiop);
2161 num_chan = ports_per_aiop;
2162 for (chan = 0; chan < num_chan; chan++)
2163 init_r_port(i, aiop, chan, dev);
2166 /* Rocket modems must be reset */
2167 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2168 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2169 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2170 num_chan = ports_per_aiop;
2171 for (chan = 0; chan < num_chan; chan++)
2172 sPCIModemReset(ctlp, chan, 1);
2174 for (chan = 0; chan < num_chan; chan++)
2175 sPCIModemReset(ctlp, chan, 0);
2177 rmSpeakerReset(ctlp, rocketModel[i].model);
2183 * Probes for PCI cards, inits them if found
2184 * Input: board_found = number of ISA boards already found, or the
2185 * starting board number
2186 * Returns: Number of PCI boards found
2188 static int __init init_PCI(int boards_found)
2190 struct pci_dev *dev = NULL;
2193 /* Work through the PCI device list, pulling out ours */
2194 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2195 if (register_PCI(count + boards_found, dev))
2201 #endif /* CONFIG_PCI */
2204 * Probes for ISA cards
2205 * Input: i = the board number to look for
2206 * Returns: 1 if board found, 0 else
2208 static int __init init_ISA(int i)
2210 int num_aiops, num_chan = 0, total_num_chan = 0;
2212 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2216 /* If io_addr is zero, no board configured */
2217 if (rcktpt_io_addr[i] == 0)
2220 /* Reserve the IO region */
2221 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2222 printk(KERN_ERR "Unable to reserve IO region for configured "
2223 "ISA RocketPort at address 0x%lx, board not "
2224 "installed...\n", rcktpt_io_addr[i]);
2225 rcktpt_io_addr[i] = 0;
2229 ctlp = sCtlNumToCtlPtr(i);
2231 ctlp->boardType = rcktpt_type[i];
2233 switch (rcktpt_type[i]) {
2234 case ROCKET_TYPE_PC104:
2235 type_string = "(PC104)";
2237 case ROCKET_TYPE_MODEM:
2238 type_string = "(RocketModem)";
2240 case ROCKET_TYPE_MODEMII:
2241 type_string = "(RocketModem II)";
2249 * If support_low_speed is set, use the slow clock prescale,
2250 * which supports 50 bps
2252 if (support_low_speed) {
2253 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2254 rp_baud_base[i] = 230400;
2256 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2257 rp_baud_base[i] = 460800;
2260 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2261 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2263 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2265 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2266 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2267 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2270 /* If something went wrong initing the AIOP's release the ISA IO memory */
2271 if (num_aiops <= 0) {
2272 release_region(rcktpt_io_addr[i], 64);
2273 rcktpt_io_addr[i] = 0;
2277 rocketModel[i].startingPortNumber = nextLineNumber;
2279 for (aiop = 0; aiop < num_aiops; aiop++) {
2280 sResetAiopByNum(ctlp, aiop);
2281 sEnAiop(ctlp, aiop);
2282 num_chan = sGetAiopNumChan(ctlp, aiop);
2283 total_num_chan += num_chan;
2284 for (chan = 0; chan < num_chan; chan++)
2285 init_r_port(i, aiop, chan, NULL);
2288 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2289 num_chan = sGetAiopNumChan(ctlp, 0);
2290 total_num_chan = num_chan;
2291 for (chan = 0; chan < num_chan; chan++)
2292 sModemReset(ctlp, chan, 1);
2294 for (chan = 0; chan < num_chan; chan++)
2295 sModemReset(ctlp, chan, 0);
2297 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2299 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2301 rocketModel[i].numPorts = total_num_chan;
2302 rocketModel[i].model = MODEL_ISA;
2304 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2305 i, rcktpt_io_addr[i], num_aiops, type_string);
2307 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2308 rocketModel[i].modelString,
2309 rocketModel[i].startingPortNumber,
2310 rocketModel[i].startingPortNumber +
2311 rocketModel[i].numPorts - 1);
2316 static const struct tty_operations rocket_ops = {
2320 .put_char = rp_put_char,
2321 .write_room = rp_write_room,
2322 .chars_in_buffer = rp_chars_in_buffer,
2323 .flush_buffer = rp_flush_buffer,
2325 .throttle = rp_throttle,
2326 .unthrottle = rp_unthrottle,
2327 .set_termios = rp_set_termios,
2330 .hangup = rp_hangup,
2331 .break_ctl = rp_break,
2332 .send_xchar = rp_send_xchar,
2333 .wait_until_sent = rp_wait_until_sent,
2334 .tiocmget = rp_tiocmget,
2335 .tiocmset = rp_tiocmset,
2338 static const struct tty_port_operations rocket_port_ops = {
2339 .carrier_raised = carrier_raised,
2344 * The module "startup" routine; it's run when the module is loaded.
2346 static int __init rp_init(void)
2348 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2350 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2351 ROCKET_VERSION, ROCKET_DATE);
2353 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2358 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2359 * zero, use the default controller IO address of board1 + 0x40.
2362 if (controller == 0)
2363 controller = board1 + 0x40;
2365 controller = 0; /* Used as a flag, meaning no ISA boards */
2368 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2369 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2370 printk(KERN_ERR "Unable to reserve IO region for first "
2371 "configured ISA RocketPort controller 0x%lx. "
2372 "Driver exiting\n", controller);
2377 /* Store ISA variable retrieved from command line or .conf file. */
2378 rcktpt_io_addr[0] = board1;
2379 rcktpt_io_addr[1] = board2;
2380 rcktpt_io_addr[2] = board3;
2381 rcktpt_io_addr[3] = board4;
2383 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2384 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2385 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2386 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2387 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2388 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2389 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2390 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2393 * Set up the tty driver structure and then register this
2394 * driver with the tty layer.
2397 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2398 rocket_driver->name = "ttyR";
2399 rocket_driver->driver_name = "Comtrol RocketPort";
2400 rocket_driver->major = TTY_ROCKET_MAJOR;
2401 rocket_driver->minor_start = 0;
2402 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2403 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2404 rocket_driver->init_termios = tty_std_termios;
2405 rocket_driver->init_termios.c_cflag =
2406 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2407 rocket_driver->init_termios.c_ispeed = 9600;
2408 rocket_driver->init_termios.c_ospeed = 9600;
2409 #ifdef ROCKET_SOFT_FLOW
2410 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2412 tty_set_operations(rocket_driver, &rocket_ops);
2414 ret = tty_register_driver(rocket_driver);
2416 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2417 goto err_controller;
2420 #ifdef ROCKET_DEBUG_OPEN
2421 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2425 * OK, let's probe each of the controllers looking for boards. Any boards found
2426 * will be initialized here.
2428 isa_boards_found = 0;
2429 pci_boards_found = 0;
2431 for (i = 0; i < NUM_BOARDS; i++) {
2437 if (isa_boards_found < NUM_BOARDS)
2438 pci_boards_found = init_PCI(isa_boards_found);
2441 max_board = pci_boards_found + isa_boards_found;
2443 if (max_board == 0) {
2444 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2451 tty_unregister_driver(rocket_driver);
2454 release_region(controller, 4);
2456 put_tty_driver(rocket_driver);
2462 static void rp_cleanup_module(void)
2467 del_timer_sync(&rocket_timer);
2469 retval = tty_unregister_driver(rocket_driver);
2471 printk(KERN_ERR "Error %d while trying to unregister "
2472 "rocketport driver\n", -retval);
2474 for (i = 0; i < MAX_RP_PORTS; i++)
2476 tty_unregister_device(rocket_driver, i);
2477 tty_port_destroy(&rp_table[i]->port);
2481 put_tty_driver(rocket_driver);
2483 for (i = 0; i < NUM_BOARDS; i++) {
2484 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2486 release_region(rcktpt_io_addr[i], 64);
2489 release_region(controller, 4);
2492 /***************************************************************************
2493 Function: sInitController
2494 Purpose: Initialization of controller global registers and controller
2496 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2497 IRQNum,Frequency,PeriodicOnly)
2498 CONTROLLER_T *CtlP; Ptr to controller structure
2499 int CtlNum; Controller number
2500 ByteIO_t MudbacIO; Mudbac base I/O address.
2501 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2502 This list must be in the order the AIOPs will be found on the
2503 controller. Once an AIOP in the list is not found, it is
2504 assumed that there are no more AIOPs on the controller.
2505 int AiopIOListSize; Number of addresses in AiopIOList
2506 int IRQNum; Interrupt Request number. Can be any of the following:
2507 0: Disable global interrupts
2516 Byte_t Frequency: A flag identifying the frequency
2517 of the periodic interrupt, can be any one of the following:
2518 FREQ_DIS - periodic interrupt disabled
2519 FREQ_137HZ - 137 Hertz
2520 FREQ_69HZ - 69 Hertz
2521 FREQ_34HZ - 34 Hertz
2522 FREQ_17HZ - 17 Hertz
2525 If IRQNum is set to 0 the Frequency parameter is
2526 overidden, it is forced to a value of FREQ_DIS.
2527 int PeriodicOnly: 1 if all interrupts except the periodic
2528 interrupt are to be blocked.
2529 0 is both the periodic interrupt and
2530 other channel interrupts are allowed.
2531 If IRQNum is set to 0 the PeriodicOnly parameter is
2532 overidden, it is forced to a value of 0.
2533 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2534 initialization failed.
2537 If periodic interrupts are to be disabled but AIOP interrupts
2538 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2540 If interrupts are to be completely disabled set IRQNum to 0.
2542 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2543 invalid combination.
2545 This function performs initialization of global interrupt modes,
2546 but it does not actually enable global interrupts. To enable
2547 and disable global interrupts use functions sEnGlobalInt() and
2548 sDisGlobalInt(). Enabling of global interrupts is normally not
2549 done until all other initializations are complete.
2551 Even if interrupts are globally enabled, they must also be
2552 individually enabled for each channel that is to generate
2555 Warnings: No range checking on any of the parameters is done.
2557 No context switches are allowed while executing this function.
2559 After this function all AIOPs on the controller are disabled,
2560 they can be enabled with sEnAiop().
2562 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2563 ByteIO_t * AiopIOList, int AiopIOListSize,
2564 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2570 CtlP->AiopIntrBits = aiop_intr_bits;
2571 CtlP->AltChanRingIndicator = 0;
2572 CtlP->CtlNum = CtlNum;
2573 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2574 CtlP->BusType = isISA;
2575 CtlP->MBaseIO = MudbacIO;
2576 CtlP->MReg1IO = MudbacIO + 1;
2577 CtlP->MReg2IO = MudbacIO + 2;
2578 CtlP->MReg3IO = MudbacIO + 3;
2580 CtlP->MReg2 = 0; /* interrupt disable */
2581 CtlP->MReg3 = 0; /* no periodic interrupts */
2583 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2584 CtlP->MReg2 = 0; /* interrupt disable */
2585 CtlP->MReg3 = 0; /* no periodic interrupts */
2587 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2588 CtlP->MReg3 = Frequency; /* set frequency */
2589 if (PeriodicOnly) { /* periodic interrupt only */
2590 CtlP->MReg3 |= PERIODIC_ONLY;
2594 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2595 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2596 sControllerEOI(CtlP); /* clear EOI if warm init */
2599 for (i = done = 0; i < AiopIOListSize; i++) {
2601 CtlP->AiopIO[i] = (WordIO_t) io;
2602 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2603 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2604 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2607 sEnAiop(CtlP, i); /* enable the AIOP */
2608 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2609 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2610 done = 1; /* done looking for AIOPs */
2612 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2613 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2614 sOutB(io + _INDX_DATA, sClockPrescale);
2615 CtlP->NumAiop++; /* bump count of AIOPs */
2617 sDisAiop(CtlP, i); /* disable AIOP */
2620 if (CtlP->NumAiop == 0)
2623 return (CtlP->NumAiop);
2626 /***************************************************************************
2627 Function: sReadAiopID
2628 Purpose: Read the AIOP idenfication number directly from an AIOP.
2629 Call: sReadAiopID(io)
2630 ByteIO_t io: AIOP base I/O address
2631 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2632 is replace by an identifying number.
2633 Flag AIOPID_NULL if no valid AIOP is found
2634 Warnings: No context switches are allowed while executing this function.
2637 static int sReadAiopID(ByteIO_t io)
2639 Byte_t AiopID; /* ID byte from AIOP */
2641 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2642 sOutB(io + _CMD_REG, 0x0);
2643 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2646 else /* AIOP does not exist */
2650 /***************************************************************************
2651 Function: sReadAiopNumChan
2652 Purpose: Read the number of channels available in an AIOP directly from
2654 Call: sReadAiopNumChan(io)
2655 WordIO_t io: AIOP base I/O address
2656 Return: int: The number of channels available
2657 Comments: The number of channels is determined by write/reads from identical
2658 offsets within the SRAM address spaces for channels 0 and 4.
2659 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2660 AIOP, otherwise it is an 8 channel.
2661 Warnings: No context switches are allowed while executing this function.
2663 static int sReadAiopNumChan(WordIO_t io)
2666 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2668 /* write to chan 0 SRAM */
2669 out32((DWordIO_t) io + _INDX_ADDR, R);
2670 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2671 x = sInW(io + _INDX_DATA);
2672 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2673 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2679 /***************************************************************************
2681 Purpose: Initialization of a channel and channel structure
2682 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2683 CONTROLLER_T *CtlP; Ptr to controller structure
2684 CHANNEL_T *ChP; Ptr to channel structure
2685 int AiopNum; AIOP number within controller
2686 int ChanNum; Channel number within AIOP
2687 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2688 number exceeds number of channels available in AIOP.
2689 Comments: This function must be called before a channel can be used.
2690 Warnings: No range checking on any of the parameters is done.
2692 No context switches are allowed while executing this function.
2694 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2705 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2706 return 0; /* exceeds num chans in AIOP */
2708 /* Channel, AIOP, and controller identifiers */
2710 ChP->ChanID = CtlP->AiopID[AiopNum];
2711 ChP->AiopNum = AiopNum;
2712 ChP->ChanNum = ChanNum;
2714 /* Global direct addresses */
2715 AiopIO = CtlP->AiopIO[AiopNum];
2716 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2717 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2718 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2719 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2720 ChP->IndexData = AiopIO + _INDX_DATA;
2722 /* Channel direct addresses */
2723 ChIOOff = AiopIO + ChP->ChanNum * 2;
2724 ChP->TxRxData = ChIOOff + _TD0;
2725 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2726 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2727 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2729 /* Initialize the channel from the RData array */
2730 for (i = 0; i < RDATASIZE; i += 4) {
2732 R[1] = RData[i + 1] + 0x10 * ChanNum;
2733 R[2] = RData[i + 2];
2734 R[3] = RData[i + 3];
2735 out32(ChP->IndexAddr, R);
2739 for (i = 0; i < RREGDATASIZE; i += 4) {
2740 ChR[i] = RRegData[i];
2741 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2742 ChR[i + 2] = RRegData[i + 2];
2743 ChR[i + 3] = RRegData[i + 3];
2746 /* Indexed registers */
2747 ChOff = (Word_t) ChanNum *0x1000;
2749 if (sClockPrescale == 0x14)
2754 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2755 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2756 ChP->BaudDiv[2] = (Byte_t) brd9600;
2757 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2758 out32(ChP->IndexAddr, ChP->BaudDiv);
2760 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2761 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2762 ChP->TxControl[2] = 0;
2763 ChP->TxControl[3] = 0;
2764 out32(ChP->IndexAddr, ChP->TxControl);
2766 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2767 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2768 ChP->RxControl[2] = 0;
2769 ChP->RxControl[3] = 0;
2770 out32(ChP->IndexAddr, ChP->RxControl);
2772 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2773 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2774 ChP->TxEnables[2] = 0;
2775 ChP->TxEnables[3] = 0;
2776 out32(ChP->IndexAddr, ChP->TxEnables);
2778 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2779 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2780 ChP->TxCompare[2] = 0;
2781 ChP->TxCompare[3] = 0;
2782 out32(ChP->IndexAddr, ChP->TxCompare);
2784 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2785 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2786 ChP->TxReplace1[2] = 0;
2787 ChP->TxReplace1[3] = 0;
2788 out32(ChP->IndexAddr, ChP->TxReplace1);
2790 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2791 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2792 ChP->TxReplace2[2] = 0;
2793 ChP->TxReplace2[3] = 0;
2794 out32(ChP->IndexAddr, ChP->TxReplace2);
2796 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2797 ChP->TxFIFO = ChOff + _TX_FIFO;
2799 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2800 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2801 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2802 sOutW(ChP->IndexData, 0);
2803 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2804 ChP->RxFIFO = ChOff + _RX_FIFO;
2806 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2807 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2808 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2809 sOutW(ChP->IndexData, 0);
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2811 sOutW(ChP->IndexData, 0);
2812 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2814 sOutB(ChP->IndexData, 0);
2815 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2816 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2817 sOutB(ChP->IndexData, 0);
2818 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2819 sEnRxProcessor(ChP); /* start the Rx processor */
2824 /***************************************************************************
2825 Function: sStopRxProcessor
2826 Purpose: Stop the receive processor from processing a channel.
2827 Call: sStopRxProcessor(ChP)
2828 CHANNEL_T *ChP; Ptr to channel structure
2830 Comments: The receive processor can be started again with sStartRxProcessor().
2831 This function causes the receive processor to skip over the
2832 stopped channel. It does not stop it from processing other channels.
2834 Warnings: No context switches are allowed while executing this function.
2836 Do not leave the receive processor stopped for more than one
2839 After calling this function a delay of 4 uS is required to ensure
2840 that the receive processor is no longer processing this channel.
2842 static void sStopRxProcessor(CHANNEL_T * ChP)
2850 out32(ChP->IndexAddr, R);
2853 /***************************************************************************
2854 Function: sFlushRxFIFO
2855 Purpose: Flush the Rx FIFO
2856 Call: sFlushRxFIFO(ChP)
2857 CHANNEL_T *ChP; Ptr to channel structure
2859 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2860 while it is being flushed the receive processor is stopped
2861 and the transmitter is disabled. After these operations a
2862 4 uS delay is done before clearing the pointers to allow
2863 the receive processor to stop. These items are handled inside
2865 Warnings: No context switches are allowed while executing this function.
2867 static void sFlushRxFIFO(CHANNEL_T * ChP)
2870 Byte_t Ch; /* channel number within AIOP */
2871 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2873 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2874 return; /* don't need to flush */
2877 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2879 sDisRxFIFO(ChP); /* disable it */
2880 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2881 sInB(ChP->IntChan); /* depends on bus i/o timing */
2883 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2884 Ch = (Byte_t) sGetChanNum(ChP);
2885 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2886 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2887 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2888 sOutW(ChP->IndexData, 0);
2889 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2890 sOutW(ChP->IndexData, 0);
2892 sEnRxFIFO(ChP); /* enable Rx FIFO */
2895 /***************************************************************************
2896 Function: sFlushTxFIFO
2897 Purpose: Flush the Tx FIFO
2898 Call: sFlushTxFIFO(ChP)
2899 CHANNEL_T *ChP; Ptr to channel structure
2901 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2902 while it is being flushed the receive processor is stopped
2903 and the transmitter is disabled. After these operations a
2904 4 uS delay is done before clearing the pointers to allow
2905 the receive processor to stop. These items are handled inside
2907 Warnings: No context switches are allowed while executing this function.
2909 static void sFlushTxFIFO(CHANNEL_T * ChP)
2912 Byte_t Ch; /* channel number within AIOP */
2913 int TxEnabled; /* 1 if transmitter enabled */
2915 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2916 return; /* don't need to flush */
2919 if (ChP->TxControl[3] & TX_ENABLE) {
2921 sDisTransmit(ChP); /* disable transmitter */
2923 sStopRxProcessor(ChP); /* stop Rx processor */
2924 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2925 sInB(ChP->IntChan); /* depends on bus i/o timing */
2926 Ch = (Byte_t) sGetChanNum(ChP);
2927 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2928 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2929 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2930 sOutW(ChP->IndexData, 0);
2932 sEnTransmit(ChP); /* enable transmitter */
2933 sStartRxProcessor(ChP); /* restart Rx processor */
2936 /***************************************************************************
2937 Function: sWriteTxPrioByte
2938 Purpose: Write a byte of priority transmit data to a channel
2939 Call: sWriteTxPrioByte(ChP,Data)
2940 CHANNEL_T *ChP; Ptr to channel structure
2941 Byte_t Data; The transmit data byte
2943 Return: int: 1 if the bytes is successfully written, otherwise 0.
2945 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2947 Warnings: No context switches are allowed while executing this function.
2949 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2951 Byte_t DWBuf[4]; /* buffer for double word writes */
2952 Word_t *WordPtr; /* must be far because Win SS != DS */
2953 register DWordIO_t IndexAddr;
2955 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2956 IndexAddr = ChP->IndexAddr;
2957 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2958 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2959 return (0); /* nothing sent */
2961 WordPtr = (Word_t *) (&DWBuf[0]);
2962 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2964 DWBuf[2] = Data; /* data byte value */
2965 out32(IndexAddr, DWBuf); /* write it out */
2967 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2969 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2970 DWBuf[3] = 0; /* priority buffer pointer */
2971 out32(IndexAddr, DWBuf); /* write it out */
2972 } else { /* write it to Tx FIFO */
2974 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2976 return (1); /* 1 byte sent */
2979 /***************************************************************************
2980 Function: sEnInterrupts
2981 Purpose: Enable one or more interrupts for a channel
2982 Call: sEnInterrupts(ChP,Flags)
2983 CHANNEL_T *ChP; Ptr to channel structure
2984 Word_t Flags: Interrupt enable flags, can be any combination
2985 of the following flags:
2986 TXINT_EN: Interrupt on Tx FIFO empty
2987 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2989 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2990 MCINT_EN: Interrupt on modem input change
2991 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2992 Interrupt Channel Register.
2994 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2995 enabled. If an interrupt enable flag is not set in Flags, that
2996 interrupt will not be changed. Interrupts can be disabled with
2997 function sDisInterrupts().
2999 This function sets the appropriate bit for the channel in the AIOP's
3000 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3001 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3003 Interrupts must also be globally enabled before channel interrupts
3004 will be passed on to the host. This is done with function
3007 In some cases it may be desirable to disable interrupts globally but
3008 enable channel interrupts. This would allow the global interrupt
3009 status register to be used to determine which AIOPs need service.
3011 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3013 Byte_t Mask; /* Interrupt Mask Register */
3015 ChP->RxControl[2] |=
3016 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3018 out32(ChP->IndexAddr, ChP->RxControl);
3020 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3022 out32(ChP->IndexAddr, ChP->TxControl);
3024 if (Flags & CHANINT_EN) {
3025 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3026 sOutB(ChP->IntMask, Mask);
3030 /***************************************************************************
3031 Function: sDisInterrupts
3032 Purpose: Disable one or more interrupts for a channel
3033 Call: sDisInterrupts(ChP,Flags)
3034 CHANNEL_T *ChP; Ptr to channel structure
3035 Word_t Flags: Interrupt flags, can be any combination
3036 of the following flags:
3037 TXINT_EN: Interrupt on Tx FIFO empty
3038 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3040 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3041 MCINT_EN: Interrupt on modem input change
3042 CHANINT_EN: Disable channel interrupt signal to the
3043 AIOP's Interrupt Channel Register.
3045 Comments: If an interrupt flag is set in Flags, that interrupt will be
3046 disabled. If an interrupt flag is not set in Flags, that
3047 interrupt will not be changed. Interrupts can be enabled with
3048 function sEnInterrupts().
3050 This function clears the appropriate bit for the channel in the AIOP's
3051 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3052 this channel's bit from being set in the AIOP's Interrupt Channel
3055 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3057 Byte_t Mask; /* Interrupt Mask Register */
3059 ChP->RxControl[2] &=
3060 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3061 out32(ChP->IndexAddr, ChP->RxControl);
3062 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3063 out32(ChP->IndexAddr, ChP->TxControl);
3065 if (Flags & CHANINT_EN) {
3066 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3067 sOutB(ChP->IntMask, Mask);
3071 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3073 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3077 * Not an official SSCI function, but how to reset RocketModems.
3080 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3085 addr = CtlP->AiopIO[0] + 0x400;
3086 val = sInB(CtlP->MReg3IO);
3087 /* if AIOP[1] is not enabled, enable it */
3088 if ((val & 2) == 0) {
3089 val = sInB(CtlP->MReg2IO);
3090 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3091 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3097 sOutB(addr + chan, 0); /* apply or remove reset */
3102 * Not an official SSCI function, but how to reset RocketModems.
3105 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3109 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3112 sOutB(addr + chan, 0); /* apply or remove reset */
3115 /* Returns the line number given the controller (board), aiop and channel number */
3116 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3118 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3122 * Stores the line number associated with a given controller (board), aiop
3123 * and channel number.
3124 * Returns: The line number assigned
3126 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3128 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3129 return (nextLineNumber - 1);