1 // SPDX-License-Identifier: GPL-2.0-only
3 * Thunderbolt driver - NHI driver
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
12 #include <linux/pm_runtime.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/pci.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/property.h>
25 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
28 * Used to enable end-to-end workaround for missing RX packets. Do not
29 * use this ring for anything else.
31 #define RING_E2E_UNUSED_HOPID 2
32 #define RING_FIRST_USABLE_HOPID TB_PATH_MIN_HOPID
35 * Minimal number of vectors when we use MSI-X. Two for control channel
36 * Rx/Tx and the rest four are for cross domain DMA paths.
38 #define MSIX_MIN_VECS 6
39 #define MSIX_MAX_VECS 16
41 #define NHI_MAILBOX_TIMEOUT 500 /* ms */
43 static int ring_interrupt_index(struct tb_ring *ring)
47 bit += ring->nhi->hop_count;
52 * ring_interrupt_active() - activate/deactivate interrupts for a single ring
54 * ring->nhi->lock must be held.
56 static void ring_interrupt_active(struct tb_ring *ring, bool active)
58 int reg = REG_RING_INTERRUPT_BASE +
59 ring_interrupt_index(ring) / 32 * 4;
60 int bit = ring_interrupt_index(ring) & 31;
65 u32 step, shift, ivr, misc;
66 void __iomem *ivr_base;
72 index = ring->hop + ring->nhi->hop_count;
75 * Ask the hardware to clear interrupt status bits automatically
76 * since we already know which interrupt was triggered.
78 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC);
79 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) {
80 misc |= REG_DMA_MISC_INT_AUTO_CLEAR;
81 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC);
84 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE;
85 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
86 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS;
87 ivr = ioread32(ivr_base + step);
88 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift);
90 ivr |= ring->vector << shift;
91 iowrite32(ivr, ivr_base + step);
94 old = ioread32(ring->nhi->iobase + reg);
100 dev_dbg(&ring->nhi->pdev->dev,
101 "%s interrupt at register %#x bit %d (%#x -> %#x)\n",
102 active ? "enabling" : "disabling", reg, bit, old, new);
105 dev_WARN(&ring->nhi->pdev->dev,
106 "interrupt for %s %d is already %s\n",
107 RING_TYPE(ring), ring->hop,
108 active ? "enabled" : "disabled");
109 iowrite32(new, ring->nhi->iobase + reg);
113 * nhi_disable_interrupts() - disable interrupts for all rings
115 * Use only during init and shutdown.
117 static void nhi_disable_interrupts(struct tb_nhi *nhi)
120 /* disable interrupts */
121 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
122 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
124 /* clear interrupt status bits */
125 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
126 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
129 /* ring helper methods */
131 static void __iomem *ring_desc_base(struct tb_ring *ring)
133 void __iomem *io = ring->nhi->iobase;
134 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE;
135 io += ring->hop * 16;
139 static void __iomem *ring_options_base(struct tb_ring *ring)
141 void __iomem *io = ring->nhi->iobase;
142 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE;
143 io += ring->hop * 32;
147 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
150 * The other 16-bits in the register is read-only and writes to it
151 * are ignored by the hardware so we can save one ioread32() by
152 * filling the read-only bits with zeroes.
154 iowrite32(cons, ring_desc_base(ring) + 8);
157 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
159 /* See ring_iowrite_cons() above for explanation */
160 iowrite32(prod << 16, ring_desc_base(ring) + 8);
163 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
165 iowrite32(value, ring_desc_base(ring) + offset);
168 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset)
170 iowrite32(value, ring_desc_base(ring) + offset);
171 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4);
174 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset)
176 iowrite32(value, ring_options_base(ring) + offset);
179 static bool ring_full(struct tb_ring *ring)
181 return ((ring->head + 1) % ring->size) == ring->tail;
184 static bool ring_empty(struct tb_ring *ring)
186 return ring->head == ring->tail;
190 * ring_write_descriptors() - post frames from ring->queue to the controller
192 * ring->lock is held.
194 static void ring_write_descriptors(struct tb_ring *ring)
196 struct ring_frame *frame, *n;
197 struct ring_desc *descriptor;
198 list_for_each_entry_safe(frame, n, &ring->queue, list) {
201 list_move_tail(&frame->list, &ring->in_flight);
202 descriptor = &ring->descriptors[ring->head];
203 descriptor->phys = frame->buffer_phy;
204 descriptor->time = 0;
205 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT;
207 descriptor->length = frame->size;
208 descriptor->eof = frame->eof;
209 descriptor->sof = frame->sof;
211 ring->head = (ring->head + 1) % ring->size;
213 ring_iowrite_prod(ring, ring->head);
215 ring_iowrite_cons(ring, ring->head);
220 * ring_work() - progress completed frames
222 * If the ring is shutting down then all frames are marked as canceled and
223 * their callbacks are invoked.
225 * Otherwise we collect all completed frame from the ring buffer, write new
226 * frame to the ring buffer and invoke the callbacks for the completed frames.
228 static void ring_work(struct work_struct *work)
230 struct tb_ring *ring = container_of(work, typeof(*ring), work);
231 struct ring_frame *frame;
232 bool canceled = false;
236 spin_lock_irqsave(&ring->lock, flags);
238 if (!ring->running) {
239 /* Move all frames to done and mark them as canceled. */
240 list_splice_tail_init(&ring->in_flight, &done);
241 list_splice_tail_init(&ring->queue, &done);
243 goto invoke_callback;
246 while (!ring_empty(ring)) {
247 if (!(ring->descriptors[ring->tail].flags
248 & RING_DESC_COMPLETED))
250 frame = list_first_entry(&ring->in_flight, typeof(*frame),
252 list_move_tail(&frame->list, &done);
254 frame->size = ring->descriptors[ring->tail].length;
255 frame->eof = ring->descriptors[ring->tail].eof;
256 frame->sof = ring->descriptors[ring->tail].sof;
257 frame->flags = ring->descriptors[ring->tail].flags;
259 ring->tail = (ring->tail + 1) % ring->size;
261 ring_write_descriptors(ring);
264 /* allow callbacks to schedule new work */
265 spin_unlock_irqrestore(&ring->lock, flags);
266 while (!list_empty(&done)) {
267 frame = list_first_entry(&done, typeof(*frame), list);
269 * The callback may reenqueue or delete frame.
270 * Do not hold on to it.
272 list_del_init(&frame->list);
274 frame->callback(ring, frame, canceled);
278 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame)
283 spin_lock_irqsave(&ring->lock, flags);
285 list_add_tail(&frame->list, &ring->queue);
286 ring_write_descriptors(ring);
290 spin_unlock_irqrestore(&ring->lock, flags);
293 EXPORT_SYMBOL_GPL(__tb_ring_enqueue);
296 * tb_ring_poll() - Poll one completed frame from the ring
297 * @ring: Ring to poll
299 * This function can be called when @start_poll callback of the @ring
300 * has been called. It will read one completed frame from the ring and
301 * return it to the caller. Returns %NULL if there is no more completed
304 struct ring_frame *tb_ring_poll(struct tb_ring *ring)
306 struct ring_frame *frame = NULL;
309 spin_lock_irqsave(&ring->lock, flags);
312 if (ring_empty(ring))
315 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) {
316 frame = list_first_entry(&ring->in_flight, typeof(*frame),
318 list_del_init(&frame->list);
321 frame->size = ring->descriptors[ring->tail].length;
322 frame->eof = ring->descriptors[ring->tail].eof;
323 frame->sof = ring->descriptors[ring->tail].sof;
324 frame->flags = ring->descriptors[ring->tail].flags;
327 ring->tail = (ring->tail + 1) % ring->size;
331 spin_unlock_irqrestore(&ring->lock, flags);
334 EXPORT_SYMBOL_GPL(tb_ring_poll);
336 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask)
338 int idx = ring_interrupt_index(ring);
339 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4;
343 val = ioread32(ring->nhi->iobase + reg);
348 iowrite32(val, ring->nhi->iobase + reg);
351 /* Both @nhi->lock and @ring->lock should be held */
352 static void __ring_interrupt(struct tb_ring *ring)
357 if (ring->start_poll) {
358 __ring_interrupt_mask(ring, true);
359 ring->start_poll(ring->poll_data);
361 schedule_work(&ring->work);
366 * tb_ring_poll_complete() - Re-start interrupt for the ring
367 * @ring: Ring to re-start the interrupt
369 * This will re-start (unmask) the ring interrupt once the user is done
372 void tb_ring_poll_complete(struct tb_ring *ring)
376 spin_lock_irqsave(&ring->nhi->lock, flags);
377 spin_lock(&ring->lock);
378 if (ring->start_poll)
379 __ring_interrupt_mask(ring, false);
380 spin_unlock(&ring->lock);
381 spin_unlock_irqrestore(&ring->nhi->lock, flags);
383 EXPORT_SYMBOL_GPL(tb_ring_poll_complete);
385 static irqreturn_t ring_msix(int irq, void *data)
387 struct tb_ring *ring = data;
389 spin_lock(&ring->nhi->lock);
390 spin_lock(&ring->lock);
391 __ring_interrupt(ring);
392 spin_unlock(&ring->lock);
393 spin_unlock(&ring->nhi->lock);
398 static int ring_request_msix(struct tb_ring *ring, bool no_suspend)
400 struct tb_nhi *nhi = ring->nhi;
401 unsigned long irqflags;
404 if (!nhi->pdev->msix_enabled)
407 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL);
413 ret = pci_irq_vector(ring->nhi->pdev, ring->vector);
419 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0;
420 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring);
427 ida_simple_remove(&nhi->msix_ida, ring->vector);
432 static void ring_release_msix(struct tb_ring *ring)
437 free_irq(ring->irq, ring);
438 ida_simple_remove(&ring->nhi->msix_ida, ring->vector);
443 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring)
447 spin_lock_irq(&nhi->lock);
453 * Automatically allocate HopID from the non-reserved
454 * range 8 .. hop_count - 1.
456 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) {
458 if (!nhi->tx_rings[i]) {
463 if (!nhi->rx_rings[i]) {
471 if (ring->hop < 0 || ring->hop >= nhi->hop_count) {
472 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop);
476 if (ring->is_tx && nhi->tx_rings[ring->hop]) {
477 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n",
481 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) {
482 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n",
489 nhi->tx_rings[ring->hop] = ring;
491 nhi->rx_rings[ring->hop] = ring;
494 spin_unlock_irq(&nhi->lock);
499 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size,
500 bool transmit, unsigned int flags,
501 u16 sof_mask, u16 eof_mask,
502 void (*start_poll)(void *),
505 struct tb_ring *ring = NULL;
507 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n",
508 transmit ? "TX" : "RX", hop, size);
510 /* Tx Ring 2 is reserved for E2E workaround */
511 if (transmit && hop == RING_E2E_UNUSED_HOPID)
514 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
518 spin_lock_init(&ring->lock);
519 INIT_LIST_HEAD(&ring->queue);
520 INIT_LIST_HEAD(&ring->in_flight);
521 INIT_WORK(&ring->work, ring_work);
525 ring->is_tx = transmit;
528 ring->sof_mask = sof_mask;
529 ring->eof_mask = eof_mask;
532 ring->running = false;
533 ring->start_poll = start_poll;
534 ring->poll_data = poll_data;
536 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev,
537 size * sizeof(*ring->descriptors),
538 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO);
539 if (!ring->descriptors)
542 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND))
545 if (nhi_alloc_hop(nhi, ring))
546 goto err_release_msix;
551 ring_release_msix(ring);
553 dma_free_coherent(&ring->nhi->pdev->dev,
554 ring->size * sizeof(*ring->descriptors),
555 ring->descriptors, ring->descriptors_dma);
563 * tb_ring_alloc_tx() - Allocate DMA ring for transmit
564 * @nhi: Pointer to the NHI the ring is to be allocated
565 * @hop: HopID (ring) to allocate
566 * @size: Number of entries in the ring
567 * @flags: Flags for the ring
569 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
572 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, NULL, NULL);
574 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx);
577 * tb_ring_alloc_rx() - Allocate DMA ring for receive
578 * @nhi: Pointer to the NHI the ring is to be allocated
579 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation.
580 * @size: Number of entries in the ring
581 * @flags: Flags for the ring
582 * @sof_mask: Mask of PDF values that start a frame
583 * @eof_mask: Mask of PDF values that end a frame
584 * @start_poll: If not %NULL the ring will call this function when an
585 * interrupt is triggered and masked, instead of callback
587 * @poll_data: Optional data passed to @start_poll
589 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
590 unsigned int flags, u16 sof_mask, u16 eof_mask,
591 void (*start_poll)(void *), void *poll_data)
593 return tb_ring_alloc(nhi, hop, size, false, flags, sof_mask, eof_mask,
594 start_poll, poll_data);
596 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx);
599 * tb_ring_start() - enable a ring
601 * Must not be invoked in parallel with tb_ring_stop().
603 void tb_ring_start(struct tb_ring *ring)
608 spin_lock_irq(&ring->nhi->lock);
609 spin_lock(&ring->lock);
610 if (ring->nhi->going_away)
613 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n");
616 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n",
617 RING_TYPE(ring), ring->hop);
619 if (ring->flags & RING_FLAG_FRAME) {
622 flags = RING_FLAG_ENABLE;
624 frame_size = TB_FRAME_SIZE;
625 flags = RING_FLAG_ENABLE | RING_FLAG_RAW;
628 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) {
632 * In order not to lose Rx packets we enable end-to-end
633 * workaround which transfers Rx credits to an unused Tx
636 hop = RING_E2E_UNUSED_HOPID << REG_RX_OPTIONS_E2E_HOP_SHIFT;
637 hop &= REG_RX_OPTIONS_E2E_HOP_MASK;
638 flags |= hop | RING_FLAG_E2E_FLOW_CONTROL;
641 ring_iowrite64desc(ring, ring->descriptors_dma, 0);
643 ring_iowrite32desc(ring, ring->size, 12);
644 ring_iowrite32options(ring, 0, 4); /* time releated ? */
645 ring_iowrite32options(ring, flags, 0);
647 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask;
649 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12);
650 ring_iowrite32options(ring, sof_eof_mask, 4);
651 ring_iowrite32options(ring, flags, 0);
653 ring_interrupt_active(ring, true);
654 ring->running = true;
656 spin_unlock(&ring->lock);
657 spin_unlock_irq(&ring->nhi->lock);
659 EXPORT_SYMBOL_GPL(tb_ring_start);
662 * tb_ring_stop() - shutdown a ring
664 * Must not be invoked from a callback.
666 * This method will disable the ring. Further calls to
667 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been
670 * All enqueued frames will be canceled and their callbacks will be executed
671 * with frame->canceled set to true (on the callback thread). This method
672 * returns only after all callback invocations have finished.
674 void tb_ring_stop(struct tb_ring *ring)
676 spin_lock_irq(&ring->nhi->lock);
677 spin_lock(&ring->lock);
678 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n",
679 RING_TYPE(ring), ring->hop);
680 if (ring->nhi->going_away)
682 if (!ring->running) {
683 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n",
684 RING_TYPE(ring), ring->hop);
687 ring_interrupt_active(ring, false);
689 ring_iowrite32options(ring, 0, 0);
690 ring_iowrite64desc(ring, 0, 0);
691 ring_iowrite32desc(ring, 0, 8);
692 ring_iowrite32desc(ring, 0, 12);
695 ring->running = false;
698 spin_unlock(&ring->lock);
699 spin_unlock_irq(&ring->nhi->lock);
702 * schedule ring->work to invoke callbacks on all remaining frames.
704 schedule_work(&ring->work);
705 flush_work(&ring->work);
707 EXPORT_SYMBOL_GPL(tb_ring_stop);
710 * tb_ring_free() - free ring
712 * When this method returns all invocations of ring->callback will have
715 * Ring must be stopped.
717 * Must NOT be called from ring_frame->callback!
719 void tb_ring_free(struct tb_ring *ring)
721 spin_lock_irq(&ring->nhi->lock);
723 * Dissociate the ring from the NHI. This also ensures that
724 * nhi_interrupt_work cannot reschedule ring->work.
727 ring->nhi->tx_rings[ring->hop] = NULL;
729 ring->nhi->rx_rings[ring->hop] = NULL;
732 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n",
733 RING_TYPE(ring), ring->hop);
735 spin_unlock_irq(&ring->nhi->lock);
737 ring_release_msix(ring);
739 dma_free_coherent(&ring->nhi->pdev->dev,
740 ring->size * sizeof(*ring->descriptors),
741 ring->descriptors, ring->descriptors_dma);
743 ring->descriptors = NULL;
744 ring->descriptors_dma = 0;
747 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring),
751 * ring->work can no longer be scheduled (it is scheduled only
752 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it
753 * to finish before freeing the ring.
755 flush_work(&ring->work);
758 EXPORT_SYMBOL_GPL(tb_ring_free);
761 * nhi_mailbox_cmd() - Send a command through NHI mailbox
762 * @nhi: Pointer to the NHI structure
763 * @cmd: Command to send
764 * @data: Data to be send with the command
766 * Sends mailbox command to the firmware running on NHI. Returns %0 in
767 * case of success and negative errno in case of failure.
769 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data)
774 iowrite32(data, nhi->iobase + REG_INMAIL_DATA);
776 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
777 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR);
778 val |= REG_INMAIL_OP_REQUEST | cmd;
779 iowrite32(val, nhi->iobase + REG_INMAIL_CMD);
781 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT);
783 val = ioread32(nhi->iobase + REG_INMAIL_CMD);
784 if (!(val & REG_INMAIL_OP_REQUEST))
786 usleep_range(10, 20);
787 } while (ktime_before(ktime_get(), timeout));
789 if (val & REG_INMAIL_OP_REQUEST)
791 if (val & REG_INMAIL_ERROR)
798 * nhi_mailbox_mode() - Return current firmware operation mode
799 * @nhi: Pointer to the NHI structure
801 * The function reads current firmware operation mode using NHI mailbox
802 * registers and returns it to the caller.
804 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi)
808 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD);
809 val &= REG_OUTMAIL_CMD_OPMODE_MASK;
810 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT;
812 return (enum nhi_fw_mode)val;
815 static void nhi_interrupt_work(struct work_struct *work)
817 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work);
818 int value = 0; /* Suppress uninitialized usage warning. */
821 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */
822 struct tb_ring *ring;
824 spin_lock_irq(&nhi->lock);
827 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields
828 * (TX, RX, RX overflow). We iterate over the bits and read a new
829 * dwords as required. The registers are cleared on read.
831 for (bit = 0; bit < 3 * nhi->hop_count; bit++) {
833 value = ioread32(nhi->iobase
834 + REG_RING_NOTIFY_BASE
836 if (++hop == nhi->hop_count) {
840 if ((value & (1 << (bit % 32))) == 0)
843 dev_warn(&nhi->pdev->dev,
844 "RX overflow for ring %d\n",
849 ring = nhi->tx_rings[hop];
851 ring = nhi->rx_rings[hop];
853 dev_warn(&nhi->pdev->dev,
854 "got interrupt for inactive %s ring %d\n",
860 spin_lock(&ring->lock);
861 __ring_interrupt(ring);
862 spin_unlock(&ring->lock);
864 spin_unlock_irq(&nhi->lock);
867 static irqreturn_t nhi_msi(int irq, void *data)
869 struct tb_nhi *nhi = data;
870 schedule_work(&nhi->interrupt_work);
874 static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
876 struct pci_dev *pdev = to_pci_dev(dev);
877 struct tb *tb = pci_get_drvdata(pdev);
878 struct tb_nhi *nhi = tb->nhi;
881 ret = tb_domain_suspend_noirq(tb);
885 if (nhi->ops && nhi->ops->suspend_noirq) {
886 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
894 static int nhi_suspend_noirq(struct device *dev)
896 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
899 static bool nhi_wake_supported(struct pci_dev *pdev)
904 * If power rails are sustainable for wakeup from S4 this
905 * property is set by the BIOS.
907 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
913 static int nhi_poweroff_noirq(struct device *dev)
915 struct pci_dev *pdev = to_pci_dev(dev);
918 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
919 return __nhi_suspend_noirq(dev, wakeup);
922 static void nhi_enable_int_throttling(struct tb_nhi *nhi)
924 /* Throttling is specified in 256ns increments */
925 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
929 * Configure interrupt throttling for all vectors even if we
932 for (i = 0; i < MSIX_MAX_VECS; i++) {
933 u32 reg = REG_INT_THROTTLING_RATE + i * 4;
934 iowrite32(throttle, nhi->iobase + reg);
938 static int nhi_resume_noirq(struct device *dev)
940 struct pci_dev *pdev = to_pci_dev(dev);
941 struct tb *tb = pci_get_drvdata(pdev);
942 struct tb_nhi *nhi = tb->nhi;
946 * Check that the device is still there. It may be that the user
947 * unplugged last device which causes the host controller to go
950 if (!pci_device_is_present(pdev)) {
951 nhi->going_away = true;
953 if (nhi->ops && nhi->ops->resume_noirq) {
954 ret = nhi->ops->resume_noirq(nhi);
958 nhi_enable_int_throttling(tb->nhi);
961 return tb_domain_resume_noirq(tb);
964 static int nhi_suspend(struct device *dev)
966 struct pci_dev *pdev = to_pci_dev(dev);
967 struct tb *tb = pci_get_drvdata(pdev);
969 return tb_domain_suspend(tb);
972 static void nhi_complete(struct device *dev)
974 struct pci_dev *pdev = to_pci_dev(dev);
975 struct tb *tb = pci_get_drvdata(pdev);
978 * If we were runtime suspended when system suspend started,
979 * schedule runtime resume now. It should bring the domain back
980 * to functional state.
982 if (pm_runtime_suspended(&pdev->dev))
983 pm_runtime_resume(&pdev->dev);
985 tb_domain_complete(tb);
988 static int nhi_runtime_suspend(struct device *dev)
990 struct pci_dev *pdev = to_pci_dev(dev);
991 struct tb *tb = pci_get_drvdata(pdev);
992 struct tb_nhi *nhi = tb->nhi;
995 ret = tb_domain_runtime_suspend(tb);
999 if (nhi->ops && nhi->ops->runtime_suspend) {
1000 ret = nhi->ops->runtime_suspend(tb->nhi);
1007 static int nhi_runtime_resume(struct device *dev)
1009 struct pci_dev *pdev = to_pci_dev(dev);
1010 struct tb *tb = pci_get_drvdata(pdev);
1011 struct tb_nhi *nhi = tb->nhi;
1014 if (nhi->ops && nhi->ops->runtime_resume) {
1015 ret = nhi->ops->runtime_resume(nhi);
1020 nhi_enable_int_throttling(nhi);
1021 return tb_domain_runtime_resume(tb);
1024 static void nhi_shutdown(struct tb_nhi *nhi)
1028 dev_dbg(&nhi->pdev->dev, "shutdown\n");
1030 for (i = 0; i < nhi->hop_count; i++) {
1031 if (nhi->tx_rings[i])
1032 dev_WARN(&nhi->pdev->dev,
1033 "TX ring %d is still active\n", i);
1034 if (nhi->rx_rings[i])
1035 dev_WARN(&nhi->pdev->dev,
1036 "RX ring %d is still active\n", i);
1038 nhi_disable_interrupts(nhi);
1040 * We have to release the irq before calling flush_work. Otherwise an
1041 * already executing IRQ handler could call schedule_work again.
1043 if (!nhi->pdev->msix_enabled) {
1044 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1045 flush_work(&nhi->interrupt_work);
1047 ida_destroy(&nhi->msix_ida);
1049 if (nhi->ops && nhi->ops->shutdown)
1050 nhi->ops->shutdown(nhi);
1053 static int nhi_init_msi(struct tb_nhi *nhi)
1055 struct pci_dev *pdev = nhi->pdev;
1058 /* In case someone left them on. */
1059 nhi_disable_interrupts(nhi);
1061 nhi_enable_int_throttling(nhi);
1063 ida_init(&nhi->msix_ida);
1066 * The NHI has 16 MSI-X vectors or a single MSI. We first try to
1067 * get all MSI-X vectors and if we succeed, each ring will have
1068 * one MSI-X. If for some reason that does not work out, we
1069 * fallback to a single MSI.
1071 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS,
1074 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1078 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work);
1080 irq = pci_irq_vector(nhi->pdev, 0);
1084 res = devm_request_irq(&pdev->dev, irq, nhi_msi,
1085 IRQF_NO_SUSPEND, "thunderbolt", nhi);
1087 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1095 static bool nhi_imr_valid(struct pci_dev *pdev)
1099 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1105 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1111 if (!nhi_imr_valid(pdev)) {
1112 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1116 res = pcim_enable_device(pdev);
1118 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1122 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1124 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1128 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1133 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1134 /* cannot fail - table is allocated bin pcim_iomap_regions */
1135 nhi->iobase = pcim_iomap_table(pdev)[0];
1136 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1137 if (nhi->hop_count != 12 && nhi->hop_count != 32)
1138 dev_warn(&pdev->dev, "unexpected hop count: %d\n",
1141 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1142 sizeof(*nhi->tx_rings), GFP_KERNEL);
1143 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,
1144 sizeof(*nhi->rx_rings), GFP_KERNEL);
1145 if (!nhi->tx_rings || !nhi->rx_rings)
1148 res = nhi_init_msi(nhi);
1150 dev_err(&pdev->dev, "cannot enable MSI, aborting\n");
1154 spin_lock_init(&nhi->lock);
1156 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1158 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1160 dev_err(&pdev->dev, "failed to set DMA mask\n");
1164 pci_set_master(pdev);
1166 if (nhi->ops && nhi->ops->init) {
1167 res = nhi->ops->init(nhi);
1172 tb = icm_probe(nhi);
1176 dev_err(&nhi->pdev->dev,
1177 "failed to determine connection manager, aborting\n");
1181 dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n");
1183 res = tb_domain_add(tb);
1186 * At this point the RX/TX rings might already have been
1187 * activated. Do a proper shutdown.
1193 pci_set_drvdata(pdev, tb);
1195 pm_runtime_allow(&pdev->dev);
1196 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY);
1197 pm_runtime_use_autosuspend(&pdev->dev);
1198 pm_runtime_put_autosuspend(&pdev->dev);
1203 static void nhi_remove(struct pci_dev *pdev)
1205 struct tb *tb = pci_get_drvdata(pdev);
1206 struct tb_nhi *nhi = tb->nhi;
1208 pm_runtime_get_sync(&pdev->dev);
1209 pm_runtime_dont_use_autosuspend(&pdev->dev);
1210 pm_runtime_forbid(&pdev->dev);
1212 tb_domain_remove(tb);
1217 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable
1218 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges
1219 * resume_noirq until we are done.
1221 static const struct dev_pm_ops nhi_pm_ops = {
1222 .suspend_noirq = nhi_suspend_noirq,
1223 .resume_noirq = nhi_resume_noirq,
1224 .freeze_noirq = nhi_suspend_noirq, /*
1225 * we just disable hotplug, the
1226 * pci-tunnels stay alive.
1228 .thaw_noirq = nhi_resume_noirq,
1229 .restore_noirq = nhi_resume_noirq,
1230 .suspend = nhi_suspend,
1231 .freeze = nhi_suspend,
1232 .poweroff_noirq = nhi_poweroff_noirq,
1233 .poweroff = nhi_suspend,
1234 .complete = nhi_complete,
1235 .runtime_suspend = nhi_runtime_suspend,
1236 .runtime_resume = nhi_runtime_resume,
1239 static struct pci_device_id nhi_ids[] = {
1241 * We have to specify class, the TB bridges use the same device and
1242 * vendor (sub)id on gen 1 and gen 2 controllers.
1245 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1246 .vendor = PCI_VENDOR_ID_INTEL,
1247 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
1248 .subvendor = 0x2222, .subdevice = 0x1111,
1251 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1252 .vendor = PCI_VENDOR_ID_INTEL,
1253 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
1254 .subvendor = 0x2222, .subdevice = 0x1111,
1257 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1258 .vendor = PCI_VENDOR_ID_INTEL,
1259 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI,
1260 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1263 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0,
1264 .vendor = PCI_VENDOR_ID_INTEL,
1265 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI,
1266 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID,
1270 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) },
1271 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) },
1272 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1273 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1274 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1275 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1276 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1277 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1278 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1279 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1280 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1281 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1282 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1283 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1288 MODULE_DEVICE_TABLE(pci, nhi_ids);
1289 MODULE_LICENSE("GPL");
1291 static struct pci_driver nhi_driver = {
1292 .name = "thunderbolt",
1293 .id_table = nhi_ids,
1295 .remove = nhi_remove,
1296 .driver.pm = &nhi_pm_ops,
1299 static int __init nhi_init(void)
1303 ret = tb_domain_init();
1306 ret = pci_register_driver(&nhi_driver);
1312 static void __exit nhi_unload(void)
1314 pci_unregister_driver(&nhi_driver);
1318 rootfs_initcall(nhi_init);
1319 module_exit(nhi_unload);