2 * OMAP5xxx bandgap registers, bitfields and temperature definitions
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * Eduardo Valentin <eduardo.valentin@ti.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 #ifndef __OMAP5XXX_BANDGAP_H
24 #define __OMAP5XXX_BANDGAP_H
29 * Below, in sequence, are the Register definitions,
30 * the bitfields and the temperature definitions for OMAP5430.
34 * OMAP5430 register definitions
36 * Registers are defined as offsets. The offsets are
37 * relative to FUSE_OPP_BGAP_GPU on 5430.
39 * Register below are grouped by domain (not necessarily in offset order)
42 /* OMAP5430.GPU register offsets */
43 #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
44 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
45 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
46 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
47 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
48 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
50 /* OMAP5430.MPU register offsets */
51 #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
52 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
53 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
54 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
55 #define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
56 #define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
58 /* OMAP5430.MPU register offsets */
59 #define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
60 #define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
61 #define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
62 #define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
63 #define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
64 #define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
66 /* OMAP5430.common register offsets */
67 #define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
68 #define OMAP5430_BGAP_STATUS_OFFSET 0x1C8
71 * Register bitfields for OMAP5430
73 * All the macros bellow define the required bits for
74 * controlling temperature on OMAP5430. Bit defines are
75 * grouped by register.
78 /* OMAP5430.TEMP_SENSOR */
79 #define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
80 #define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
81 #define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
82 #define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
84 /* OMAP5430.BANDGAP_CTRL */
85 #define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
86 #define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
87 #define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
88 #define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
89 #define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
90 #define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
91 #define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
92 #define OMAP5430_MASK_COLD_GPU_MASK BIT(2)
93 #define OMAP5430_MASK_HOT_MPU_MASK BIT(1)
94 #define OMAP5430_MASK_COLD_MPU_MASK BIT(0)
96 /* OMAP5430.BANDGAP_COUNTER */
97 #define OMAP5430_COUNTER_MASK (0xffffff << 0)
99 /* OMAP5430.BANDGAP_THRESHOLD */
100 #define OMAP5430_T_HOT_MASK (0x3ff << 16)
101 #define OMAP5430_T_COLD_MASK (0x3ff << 0)
103 /* OMAP5430.TSHUT_THRESHOLD */
104 #define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
105 #define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
107 /* OMAP5430.BANDGAP_STATUS */
108 #define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
109 #define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
110 #define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
111 #define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)
112 #define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)
113 #define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)
116 * Temperature limits and thresholds for OMAP5430
118 * All the macros bellow are definitions for handling the
119 * ADC conversions and representation of temperature limits
120 * and thresholds for OMAP5430. Definitions are grouped
121 * by temperature domain.
124 /* OMAP5430.common temperature definitions */
125 /* ADC conversion table limits */
126 #define OMAP5430_ADC_START_VALUE 540
127 #define OMAP5430_ADC_END_VALUE 945
129 /* OMAP5430.GPU temperature definitions */
130 /* bandgap clock limits */
131 #define OMAP5430_GPU_MAX_FREQ 1500000
132 #define OMAP5430_GPU_MIN_FREQ 1000000
133 /* interrupts thresholds */
134 #define OMAP5430_GPU_TSHUT_HOT 915
135 #define OMAP5430_GPU_TSHUT_COLD 900
136 #define OMAP5430_GPU_T_HOT 800
137 #define OMAP5430_GPU_T_COLD 795
139 /* OMAP5430.MPU temperature definitions */
140 /* bandgap clock limits */
141 #define OMAP5430_MPU_MAX_FREQ 1500000
142 #define OMAP5430_MPU_MIN_FREQ 1000000
143 /* interrupts thresholds */
144 #define OMAP5430_MPU_TSHUT_HOT 915
145 #define OMAP5430_MPU_TSHUT_COLD 900
146 #define OMAP5430_MPU_T_HOT 800
147 #define OMAP5430_MPU_T_COLD 795
149 /* OMAP5430.CORE temperature definitions */
150 /* bandgap clock limits */
151 #define OMAP5430_CORE_MAX_FREQ 1500000
152 #define OMAP5430_CORE_MIN_FREQ 1000000
153 /* interrupts thresholds */
154 #define OMAP5430_CORE_TSHUT_HOT 915
155 #define OMAP5430_CORE_TSHUT_COLD 900
156 #define OMAP5430_CORE_T_HOT 800
157 #define OMAP5430_CORE_T_COLD 795
159 #endif /* __OMAP5XXX_BANDGAP_H */