drivers/thermal/ti-soc-thermal/dra752-thermal-data.c

   1 /*
   2  * DRA752 thermal data.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Inc.
   5  * Contact:
   6  *      Eduardo Valentin <eduardo.valentin@ti.com>
   7  *      Tero Kristo <t-kristo@ti.com>
   8  *
   9  * This file is partially autogenerated.
  10  *
  11  * This software is licensed under the terms of the GNU General Public
  12  * License version 2, as published by the Free Software Foundation, and
  13  * may be copied, distributed, and modified under those terms.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21
  22 #include "ti-thermal.h"
  23 #include "ti-bandgap.h"
  24 #include "dra752-bandgap.h"
  25
  26 /*
  27  * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
  28  * IVA and DSPEVE need to describe the individual registers and
  29  * bit fields.
  30  */
  31
  32 /*
  33  * DRA752 CORE thermal sensor register offsets and bit-fields
  34  */
  35 static struct temp_sensor_registers
  36 dra752_core_temp_sensor_registers = {
  37         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
  38         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  39         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  40         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  41         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
  42         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
  43         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
  44         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
  45         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
  46         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
  47         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  48         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  49         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
  50         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
  51         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
  52         .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
  53         .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
  54         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
  55 };
  56
  57 /*
  58  * DRA752 IVA thermal sensor register offsets and bit-fields
  59  */
  60 static struct temp_sensor_registers
  61 dra752_iva_temp_sensor_registers = {
  62         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
  63         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  64         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  65         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  66         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
  67         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
  68         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
  69         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
  70         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
  71         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
  72         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  73         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  74         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
  75         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
  76         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
  77         .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
  78         .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
  79         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
  80 };
  81
  82 /*
  83  * DRA752 MPU thermal sensor register offsets and bit-fields
  84  */
  85 static struct temp_sensor_registers
  86 dra752_mpu_temp_sensor_registers = {
  87         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
  88         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  89         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  90         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  91         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
  92         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
  93         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
  94         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
  95         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
  96         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
  97         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  98         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  99         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 100         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
 101         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
 102         .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
 103         .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
 104         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
 105 };
 106
 107 /*
 108  * DRA752 DSPEVE thermal sensor register offsets and bit-fields
 109  */
 110 static struct temp_sensor_registers
 111 dra752_dspeve_temp_sensor_registers = {
 112         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
 113         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 114         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 115         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 116         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
 117         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
 118         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
 119         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
 120         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
 121         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
 122         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 123         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 124         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
 125         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
 126         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
 127         .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
 128         .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
 129         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
 130 };
 131
 132 /*
 133  * DRA752 GPU thermal sensor register offsets and bit-fields
 134  */
 135 static struct temp_sensor_registers
 136 dra752_gpu_temp_sensor_registers = {
 137         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
 138         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 139         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 140         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 141         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
 142         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
 143         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
 144         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
 145         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
 146         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
 147         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 148         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 149         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 150         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
 151         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
 152         .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
 153         .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
 154         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
 155 };
 156
 157 /* Thresholds and limits for DRA752 MPU temperature sensor */
 158 static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
 159         .t_hot = DRA752_MPU_T_HOT,
 160         .t_cold = DRA752_MPU_T_COLD,
 161         .min_freq = DRA752_MPU_MIN_FREQ,
 162         .max_freq = DRA752_MPU_MAX_FREQ,
 163 };
 164
 165 /* Thresholds and limits for DRA752 GPU temperature sensor */
 166 static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
 167         .t_hot = DRA752_GPU_T_HOT,
 168         .t_cold = DRA752_GPU_T_COLD,
 169         .min_freq = DRA752_GPU_MIN_FREQ,
 170         .max_freq = DRA752_GPU_MAX_FREQ,
 171 };
 172
 173 /* Thresholds and limits for DRA752 CORE temperature sensor */
 174 static struct temp_sensor_data dra752_core_temp_sensor_data = {
 175         .t_hot = DRA752_CORE_T_HOT,
 176         .t_cold = DRA752_CORE_T_COLD,
 177         .min_freq = DRA752_CORE_MIN_FREQ,
 178         .max_freq = DRA752_CORE_MAX_FREQ,
 179 };
 180
 181 /* Thresholds and limits for DRA752 DSPEVE temperature sensor */
 182 static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
 183         .t_hot = DRA752_DSPEVE_T_HOT,
 184         .t_cold = DRA752_DSPEVE_T_COLD,
 185         .min_freq = DRA752_DSPEVE_MIN_FREQ,
 186         .max_freq = DRA752_DSPEVE_MAX_FREQ,
 187 };
 188
 189 /* Thresholds and limits for DRA752 IVA temperature sensor */
 190 static struct temp_sensor_data dra752_iva_temp_sensor_data = {
 191         .t_hot = DRA752_IVA_T_HOT,
 192         .t_cold = DRA752_IVA_T_COLD,
 193         .min_freq = DRA752_IVA_MIN_FREQ,
 194         .max_freq = DRA752_IVA_MAX_FREQ,
 195 };
 196
 197 /*
 198  * DRA752 : Temperature values in milli degree celsius
 199  * ADC code values from 540 to 945
 200  */
 201 static
 202 int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
 203         /* Index 540 - 549 */
 204         -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
 205         -37800,
 206         /* Index 550 - 559 */
 207         -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
 208         -33400,
 209         /* Index 560 - 569 */
 210         -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
 211         -29400,
 212         /* Index 570 - 579 */
 213         -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
 214         -25000,
 215         /* Index 580 - 589 */
 216         -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
 217         -21000,
 218         /* Index 590 - 599 */
 219         -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
 220         -16600,
 221         /* Index 600 - 609 */
 222         -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
 223         -12500,
 224         /* Index 610 - 619 */
 225         -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
 226         -8200,
 227         /* Index 620 - 629 */
 228         -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
 229         -3900,
 230         /* Index 630 - 639 */
 231         -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
 232         200,
 233         /* Index 640 - 649 */
 234         600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
 235         4500,
 236         /* Index 650 - 659 */
 237         5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
 238         8600,
 239         /* Index 660 - 669 */
 240         9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
 241         12700,
 242         /* Index 670 - 679 */
 243         13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
 244         17000,
 245         /* Index 680 - 689 */
 246         17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
 247         21000,
 248         /* Index 690 - 699 */
 249         21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
 250         25400,
 251         /* Index 700 - 709 */
 252         25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
 253         29400,
 254         /* Index 710 - 719 */
 255         29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
 256         33800,
 257         /* Index 720 - 729 */
 258         34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
 259         37800,
 260         /* Index 730 - 739 */
 261         38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
 262         41800,
 263         /* Index 740 - 749 */
 264         42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
 265         46200,
 266         /* Index 750 - 759 */
 267         46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
 268         50200,
 269         /* Index 760 - 769 */
 270         50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
 271         54200,
 272         /* Index 770 - 779 */
 273         54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
 274         58600,
 275         /* Index 780 - 789 */
 276         59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
 277         62600,
 278         /* Index 790 - 799 */
 279         63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
 280         66600,
 281         /* Index 800 - 809 */
 282         67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
 283         70600,
 284         /* Index 810 - 819 */
 285         71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
 286         75000,
 287         /* Index 820 - 829 */
 288         75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
 289         79000,
 290         /* Index 830 - 839 */
 291         79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
 292         83000,
 293         /* Index 840 - 849 */
 294         83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
 295         87000,
 296         /* Index 850 - 859 */
 297         87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
 298         91000,
 299         /* Index 860 - 869 */
 300         91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
 301         95000,
 302         /* Index 870 - 879 */
 303         95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
 304         99400,
 305         /* Index 880 - 889 */
 306         99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
 307         103400,
 308         /* Index 890 - 899 */
 309         103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
 310         107400,
 311         /* Index 900 - 909 */
 312         107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
 313         111400,
 314         /* Index 910 - 919 */
 315         111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
 316         115400,
 317         /* Index 920 - 929 */
 318         115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
 319         119400,
 320         /* Index 930 - 939 */
 321         119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
 322         123400,
 323         /* Index 940 - 945 */
 324         123800, 124200, 124600, 124900, 125000, 125000,
 325 };
 326
 327 /* DRA752 data */
 328 const struct ti_bandgap_data dra752_data = {
 329         .features = TI_BANDGAP_FEATURE_FREEZE_BIT |
 330                         TI_BANDGAP_FEATURE_TALERT |
 331                         TI_BANDGAP_FEATURE_COUNTER_DELAY |
 332                         TI_BANDGAP_FEATURE_HISTORY_BUFFER |
 333                         TI_BANDGAP_FEATURE_ERRATA_814,
 334         .fclock_name = "l3instr_ts_gclk_div",
 335         .div_ck_name = "l3instr_ts_gclk_div",
 336         .conv_table = dra752_adc_to_temp,
 337         .adc_start_val = DRA752_ADC_START_VALUE,
 338         .adc_end_val = DRA752_ADC_END_VALUE,
 339         .expose_sensor = ti_thermal_expose_sensor,
 340         .remove_sensor = ti_thermal_remove_sensor,
 341         .sensors = {
 342                 {
 343                 .registers = &dra752_mpu_temp_sensor_registers,
 344                 .ts_data = &dra752_mpu_temp_sensor_data,
 345                 .domain = "cpu",
 346                 .register_cooling = ti_thermal_register_cpu_cooling,
 347                 .unregister_cooling = ti_thermal_unregister_cpu_cooling,
 348                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 349                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 350                 },
 351                 {
 352                 .registers = &dra752_gpu_temp_sensor_registers,
 353                 .ts_data = &dra752_gpu_temp_sensor_data,
 354                 .domain = "gpu",
 355                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 356                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 357                 },
 358                 {
 359                 .registers = &dra752_core_temp_sensor_registers,
 360                 .ts_data = &dra752_core_temp_sensor_data,
 361                 .domain = "core",
 362                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 363                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 364                 },
 365                 {
 366                 .registers = &dra752_dspeve_temp_sensor_registers,
 367                 .ts_data = &dra752_dspeve_temp_sensor_data,
 368                 .domain = "dspeve",
 369                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 370                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 371                 },
 372                 {
 373                 .registers = &dra752_iva_temp_sensor_registers,
 374                 .ts_data = &dra752_iva_temp_sensor_data,
 375                 .domain = "iva",
 376                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 377                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 378                 },
 379         },
 380         .sensor_count = 5,
 381 };