2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
8 * Copyright (C) 2011 Samsung Electronics
9 * Donggeun Kim <dg77.kim@samsung.com>
10 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/clk.h>
30 #include <linux/interrupt.h>
31 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/regulator/consumer.h>
38 #include "exynos_tmu.h"
39 #include "../thermal_core.h"
41 /* Exynos generic registers */
42 #define EXYNOS_TMU_REG_TRIMINFO 0x0
43 #define EXYNOS_TMU_REG_CONTROL 0x20
44 #define EXYNOS_TMU_REG_STATUS 0x28
45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
46 #define EXYNOS_TMU_REG_INTEN 0x70
47 #define EXYNOS_TMU_REG_INTSTAT 0x74
48 #define EXYNOS_TMU_REG_INTCLEAR 0x78
50 #define EXYNOS_TMU_TEMP_MASK 0xff
51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
55 #define EXYNOS_TMU_CORE_EN_SHIFT 0
57 /* Exynos3250 specific registers */
58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
60 /* Exynos4210 specific registers */
61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
66 #define EXYNOS_THD_TEMP_RISE 0x50
67 #define EXYNOS_THD_TEMP_FALL 0x54
68 #define EXYNOS_EMUL_CON 0x80
70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
71 #define EXYNOS_TRIMINFO_25_SHIFT 0
72 #define EXYNOS_TRIMINFO_85_SHIFT 8
73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
83 #define EXYNOS_EMUL_TIME 0x57F0
84 #define EXYNOS_EMUL_TIME_MASK 0xffff
85 #define EXYNOS_EMUL_TIME_SHIFT 16
86 #define EXYNOS_EMUL_DATA_SHIFT 8
87 #define EXYNOS_EMUL_DATA_MASK 0xFF
88 #define EXYNOS_EMUL_ENABLE 0x1
90 /* Exynos5260 specific */
91 #define EXYNOS5260_TMU_REG_INTEN 0xC0
92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
94 #define EXYNOS5260_EMUL_CON 0x100
96 /* Exynos4412 specific */
97 #define EXYNOS4412_MUX_ADDR_VALUE 6
98 #define EXYNOS4412_MUX_ADDR_SHIFT 20
100 /* Exynos5433 specific registers */
101 #define EXYNOS5433_TMU_REG_CONTROL1 0x024
102 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c
103 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030
104 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034
105 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044
106 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050
107 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054
108 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060
109 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064
110 #define EXYNOS5433_TMU_REG_INTEN 0x0c0
111 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8
112 #define EXYNOS5433_TMU_EMUL_CON 0x110
113 #define EXYNOS5433_TMU_PD_DET_EN 0x130
115 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16
116 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23
117 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \
118 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
119 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23)
121 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0
122 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1
124 #define EXYNOS5433_PD_DET_EN 1
126 /*exynos5440 specific registers*/
127 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
128 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
129 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
130 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
131 #define EXYNOS5440_TMU_S0_7_TH0 0x110
132 #define EXYNOS5440_TMU_S0_7_TH1 0x130
133 #define EXYNOS5440_TMU_S0_7_TH2 0x150
134 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
135 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
136 /* exynos5440 common registers */
137 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
138 #define EXYNOS5440_TMU_PMIN 0x004
140 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
141 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
142 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
143 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
144 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
145 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
146 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
148 /* Exynos7 specific registers */
149 #define EXYNOS7_THD_TEMP_RISE7_6 0x50
150 #define EXYNOS7_THD_TEMP_FALL7_6 0x60
151 #define EXYNOS7_TMU_REG_INTEN 0x110
152 #define EXYNOS7_TMU_REG_INTPEND 0x118
153 #define EXYNOS7_TMU_REG_EMUL_CON 0x160
155 #define EXYNOS7_TMU_TEMP_MASK 0x1ff
156 #define EXYNOS7_PD_DET_EN_SHIFT 23
157 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
158 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1
159 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2
160 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3
161 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4
162 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5
163 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6
164 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7
165 #define EXYNOS7_EMUL_DATA_SHIFT 7
166 #define EXYNOS7_EMUL_DATA_MASK 0x1ff
168 #define MCELSIUS 1000
170 * struct exynos_tmu_data : A structure to hold the private data of the TMU
172 * @id: identifier of the one instance of the TMU controller.
173 * @pdata: pointer to the tmu platform/configuration data
174 * @base: base address of the single instance of the TMU controller.
175 * @base_second: base address of the common registers of the TMU controller.
176 * @irq: irq number of the TMU controller.
177 * @soc: id of the SOC type.
178 * @irq_work: pointer to the irq work structure.
179 * @lock: lock to implement synchronization.
180 * @clk: pointer to the clock structure.
181 * @clk_sec: pointer to the clock structure for accessing the base_second.
182 * @sclk: pointer to the clock structure for accessing the tmu special clk.
183 * @temp_error1: fused value of the first point trim.
184 * @temp_error2: fused value of the second point trim.
185 * @regulator: pointer to the TMU regulator structure.
186 * @reg_conf: pointer to structure to register with core thermal.
187 * @ntrip: number of supported trip points.
188 * @enabled: current status of TMU device
189 * @tmu_initialize: SoC specific TMU initialization method
190 * @tmu_control: SoC specific TMU control method
191 * @tmu_read: SoC specific TMU temperature read method
192 * @tmu_set_emulation: SoC specific TMU emulation setting method
193 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
195 struct exynos_tmu_data {
197 struct exynos_tmu_platform_data *pdata;
199 void __iomem *base_second;
202 struct work_struct irq_work;
204 struct clk *clk, *clk_sec, *sclk;
205 u16 temp_error1, temp_error2;
206 struct regulator *regulator;
207 struct thermal_zone_device *tzd;
211 int (*tmu_initialize)(struct platform_device *pdev);
212 void (*tmu_control)(struct platform_device *pdev, bool on);
213 int (*tmu_read)(struct exynos_tmu_data *data);
214 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
215 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
218 static void exynos_report_trigger(struct exynos_tmu_data *p)
220 char data[10], *envp[] = { data, NULL };
221 struct thermal_zone_device *tz = p->tzd;
226 pr_err("No thermal zone device defined\n");
230 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
232 mutex_lock(&tz->lock);
233 /* Find the level for which trip happened */
234 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
235 tz->ops->get_trip_temp(tz, i, &temp);
236 if (tz->last_temperature < temp)
240 snprintf(data, sizeof(data), "%u", i);
241 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
242 mutex_unlock(&tz->lock);
246 * TMU treats temperature as a mapped temperature code.
247 * The temperature is converted differently depending on the calibration type.
249 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
251 struct exynos_tmu_platform_data *pdata = data->pdata;
254 switch (pdata->cal_type) {
255 case TYPE_TWO_POINT_TRIMMING:
256 temp_code = (temp - pdata->first_point_trim) *
257 (data->temp_error2 - data->temp_error1) /
258 (pdata->second_point_trim - pdata->first_point_trim) +
261 case TYPE_ONE_POINT_TRIMMING:
262 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
265 temp_code = temp + pdata->default_temp_offset;
273 * Calculate a temperature value from a temperature code.
274 * The unit of the temperature is degree Celsius.
276 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
278 struct exynos_tmu_platform_data *pdata = data->pdata;
281 switch (pdata->cal_type) {
282 case TYPE_TWO_POINT_TRIMMING:
283 temp = (temp_code - data->temp_error1) *
284 (pdata->second_point_trim - pdata->first_point_trim) /
285 (data->temp_error2 - data->temp_error1) +
286 pdata->first_point_trim;
288 case TYPE_ONE_POINT_TRIMMING:
289 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
292 temp = temp_code - pdata->default_temp_offset;
299 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
301 struct exynos_tmu_platform_data *pdata = data->pdata;
303 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
304 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
305 EXYNOS_TMU_TEMP_MASK);
307 if (!data->temp_error1 ||
308 (pdata->min_efuse_value > data->temp_error1) ||
309 (data->temp_error1 > pdata->max_efuse_value))
310 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
312 if (!data->temp_error2)
314 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
315 EXYNOS_TMU_TEMP_MASK;
318 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
320 struct thermal_zone_device *tz = data->tzd;
321 const struct thermal_trip * const trips =
322 of_thermal_get_trip_points(tz);
327 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
332 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
333 if (trips[i].type == THERMAL_TRIP_CRITICAL)
336 temp = trips[i].temperature / MCELSIUS;
338 temp -= (trips[i].hysteresis / MCELSIUS);
340 threshold &= ~(0xff << 8 * i);
342 threshold |= temp_to_code(data, temp) << 8 * i;
348 static int exynos_tmu_initialize(struct platform_device *pdev)
350 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
353 if (of_thermal_get_ntrips(data->tzd) > data->ntrip) {
355 "More trip points than supported by this TMU.\n");
357 "%d trip points should be configured in polling mode.\n",
358 (of_thermal_get_ntrips(data->tzd) - data->ntrip));
361 mutex_lock(&data->lock);
362 clk_enable(data->clk);
363 if (!IS_ERR(data->clk_sec))
364 clk_enable(data->clk_sec);
365 ret = data->tmu_initialize(pdev);
366 clk_disable(data->clk);
367 mutex_unlock(&data->lock);
368 if (!IS_ERR(data->clk_sec))
369 clk_disable(data->clk_sec);
374 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
376 struct exynos_tmu_platform_data *pdata = data->pdata;
378 if (data->soc == SOC_ARCH_EXYNOS4412 ||
379 data->soc == SOC_ARCH_EXYNOS3250)
380 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
382 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
383 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
385 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
386 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
388 if (pdata->noise_cancel_mode) {
389 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
390 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
396 static void exynos_tmu_control(struct platform_device *pdev, bool on)
398 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
400 mutex_lock(&data->lock);
401 clk_enable(data->clk);
402 data->tmu_control(pdev, on);
404 clk_disable(data->clk);
405 mutex_unlock(&data->lock);
408 static int exynos4210_tmu_initialize(struct platform_device *pdev)
410 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
411 struct thermal_zone_device *tz = data->tzd;
412 const struct thermal_trip * const trips =
413 of_thermal_get_trip_points(tz);
414 int ret = 0, threshold_code, i;
415 unsigned long reference, temp;
419 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
425 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
431 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
433 /* Write temperature code for threshold */
434 reference = trips[0].temperature / MCELSIUS;
435 threshold_code = temp_to_code(data, reference);
436 if (threshold_code < 0) {
437 ret = threshold_code;
440 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
442 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
443 temp = trips[i].temperature / MCELSIUS;
444 writeb(temp - reference, data->base +
445 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
448 data->tmu_clear_irqs(data);
453 static int exynos4412_tmu_initialize(struct platform_device *pdev)
455 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
456 const struct thermal_trip * const trips =
457 of_thermal_get_trip_points(data->tzd);
458 unsigned int status, trim_info, con, ctrl, rising_threshold;
459 int ret = 0, threshold_code, i;
460 unsigned long crit_temp = 0;
462 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
468 if (data->soc == SOC_ARCH_EXYNOS3250 ||
469 data->soc == SOC_ARCH_EXYNOS4412 ||
470 data->soc == SOC_ARCH_EXYNOS5250) {
471 if (data->soc == SOC_ARCH_EXYNOS3250) {
472 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
473 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
474 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
476 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
477 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
478 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
481 /* On exynos5420 the triminfo register is in the shared space */
482 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
483 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
485 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
487 sanitize_temp_error(data, trim_info);
489 /* Write temperature code for rising and falling threshold */
490 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
491 rising_threshold = get_th_reg(data, rising_threshold, false);
492 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
493 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
495 data->tmu_clear_irqs(data);
497 /* if last threshold limit is also present */
498 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
499 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
500 crit_temp = trips[i].temperature;
505 if (i == of_thermal_get_ntrips(data->tzd)) {
506 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
512 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
513 /* 1-4 level to be assigned in th0 reg */
514 rising_threshold &= ~(0xff << 8 * i);
515 rising_threshold |= threshold_code << 8 * i;
516 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
517 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
518 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
519 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
525 static int exynos5433_tmu_initialize(struct platform_device *pdev)
527 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
528 struct exynos_tmu_platform_data *pdata = data->pdata;
529 struct thermal_zone_device *tz = data->tzd;
530 unsigned int status, trim_info;
531 unsigned int rising_threshold = 0, falling_threshold = 0;
533 int ret = 0, threshold_code, i, sensor_id, cal_type;
535 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
541 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
542 sanitize_temp_error(data, trim_info);
544 /* Read the temperature sensor id */
545 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
546 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
547 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
549 /* Read the calibration mode */
550 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
551 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
552 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
555 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
556 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
558 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
559 pdata->cal_type = TYPE_TWO_POINT_TRIMMING;
562 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
566 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
569 /* Write temperature code for rising and falling threshold */
570 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
571 int rising_reg_offset, falling_reg_offset;
579 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0;
580 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0;
587 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4;
588 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4;
595 /* Write temperature code for rising threshold */
596 tz->ops->get_trip_temp(tz, i, &temp);
598 threshold_code = temp_to_code(data, temp);
600 rising_threshold = readl(data->base + rising_reg_offset);
601 rising_threshold &= ~(0xff << j * 8);
602 rising_threshold |= (threshold_code << j * 8);
603 writel(rising_threshold, data->base + rising_reg_offset);
605 /* Write temperature code for falling threshold */
606 tz->ops->get_trip_hyst(tz, i, &temp_hist);
607 temp_hist = temp - (temp_hist / MCELSIUS);
608 threshold_code = temp_to_code(data, temp_hist);
610 falling_threshold = readl(data->base + falling_reg_offset);
611 falling_threshold &= ~(0xff << j * 8);
612 falling_threshold |= (threshold_code << j * 8);
613 writel(falling_threshold, data->base + falling_reg_offset);
616 data->tmu_clear_irqs(data);
621 static int exynos5440_tmu_initialize(struct platform_device *pdev)
623 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
624 unsigned int trim_info = 0, con, rising_threshold;
629 * For exynos5440 soc triminfo value is swapped between TMU0 and
630 * TMU2, so the below logic is needed.
634 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
635 EXYNOS5440_TMU_S0_7_TRIM);
638 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
641 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
642 EXYNOS5440_TMU_S0_7_TRIM);
644 sanitize_temp_error(data, trim_info);
646 /* Write temperature code for rising and falling threshold */
647 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
648 rising_threshold = get_th_reg(data, rising_threshold, false);
649 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
650 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
652 data->tmu_clear_irqs(data);
654 /* if last threshold limit is also present */
655 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
656 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
657 /* 5th level to be assigned in th2 reg */
659 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
660 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
661 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
662 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
663 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
665 /* Clear the PMIN in the common TMU register */
667 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
672 static int exynos7_tmu_initialize(struct platform_device *pdev)
674 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
675 struct thermal_zone_device *tz = data->tzd;
676 struct exynos_tmu_platform_data *pdata = data->pdata;
677 unsigned int status, trim_info;
678 unsigned int rising_threshold = 0, falling_threshold = 0;
679 int ret = 0, threshold_code, i;
681 unsigned int reg_off, bit_off;
683 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
689 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
691 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
692 if (!data->temp_error1 ||
693 (pdata->min_efuse_value > data->temp_error1) ||
694 (data->temp_error1 > pdata->max_efuse_value))
695 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
697 /* Write temperature code for rising and falling threshold */
698 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
700 * On exynos7 there are 4 rising and 4 falling threshold
701 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
702 * register holds the value of two threshold levels (at bit
703 * offsets 0 and 16). Based on the fact that there are atmost
704 * eight possible trigger levels, calculate the register and
705 * bit offsets where the threshold levels are to be written.
707 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
708 * [24:16] - Threshold level 7
709 * [8:0] - Threshold level 6
710 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
711 * [24:16] - Threshold level 5
712 * [8:0] - Threshold level 4
714 * and similarly for falling thresholds.
716 * Based on the above, calculate the register and bit offsets
717 * for rising/falling threshold levels and populate them.
719 reg_off = ((7 - i) / 2) * 4;
720 bit_off = ((8 - i) % 2);
722 tz->ops->get_trip_temp(tz, i, &temp);
725 tz->ops->get_trip_hyst(tz, i, &temp_hist);
726 temp_hist = temp - (temp_hist / MCELSIUS);
728 /* Set 9-bit temperature code for rising threshold levels */
729 threshold_code = temp_to_code(data, temp);
730 rising_threshold = readl(data->base +
731 EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
732 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
733 rising_threshold |= threshold_code << (16 * bit_off);
734 writel(rising_threshold,
735 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
737 /* Set 9-bit temperature code for falling threshold levels */
738 threshold_code = temp_to_code(data, temp_hist);
739 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
740 falling_threshold |= threshold_code << (16 * bit_off);
741 writel(falling_threshold,
742 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
745 data->tmu_clear_irqs(data);
750 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
752 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
753 struct thermal_zone_device *tz = data->tzd;
754 unsigned int con, interrupt_en;
756 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
759 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
761 (of_thermal_is_trip_valid(tz, 3)
762 << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
763 (of_thermal_is_trip_valid(tz, 2)
764 << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
765 (of_thermal_is_trip_valid(tz, 1)
766 << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
767 (of_thermal_is_trip_valid(tz, 0)
768 << EXYNOS_TMU_INTEN_RISE0_SHIFT);
770 if (data->soc != SOC_ARCH_EXYNOS4210)
772 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
774 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
775 interrupt_en = 0; /* Disable all interrupts */
777 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
778 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
781 static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
783 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
784 struct thermal_zone_device *tz = data->tzd;
785 unsigned int con, interrupt_en, pd_det_en;
787 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
790 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
792 (of_thermal_is_trip_valid(tz, 7)
793 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
794 (of_thermal_is_trip_valid(tz, 6)
795 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
796 (of_thermal_is_trip_valid(tz, 5)
797 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
798 (of_thermal_is_trip_valid(tz, 4)
799 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
800 (of_thermal_is_trip_valid(tz, 3)
801 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
802 (of_thermal_is_trip_valid(tz, 2)
803 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
804 (of_thermal_is_trip_valid(tz, 1)
805 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
806 (of_thermal_is_trip_valid(tz, 0)
807 << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
810 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
812 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
813 interrupt_en = 0; /* Disable all interrupts */
816 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
818 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
819 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
820 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
823 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
825 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
826 struct thermal_zone_device *tz = data->tzd;
827 unsigned int con, interrupt_en;
829 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
832 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
834 (of_thermal_is_trip_valid(tz, 3)
835 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
836 (of_thermal_is_trip_valid(tz, 2)
837 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
838 (of_thermal_is_trip_valid(tz, 1)
839 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
840 (of_thermal_is_trip_valid(tz, 0)
841 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
843 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
845 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
846 interrupt_en = 0; /* Disable all interrupts */
848 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
849 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
852 static void exynos7_tmu_control(struct platform_device *pdev, bool on)
854 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
855 struct thermal_zone_device *tz = data->tzd;
856 unsigned int con, interrupt_en;
858 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
861 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
862 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
864 (of_thermal_is_trip_valid(tz, 7)
865 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
866 (of_thermal_is_trip_valid(tz, 6)
867 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
868 (of_thermal_is_trip_valid(tz, 5)
869 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
870 (of_thermal_is_trip_valid(tz, 4)
871 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
872 (of_thermal_is_trip_valid(tz, 3)
873 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
874 (of_thermal_is_trip_valid(tz, 2)
875 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
876 (of_thermal_is_trip_valid(tz, 1)
877 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
878 (of_thermal_is_trip_valid(tz, 0)
879 << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
882 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
884 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
885 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
886 interrupt_en = 0; /* Disable all interrupts */
889 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
890 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
893 static int exynos_get_temp(void *p, int *temp)
895 struct exynos_tmu_data *data = p;
898 if (!data || !data->tmu_read || !data->enabled)
901 mutex_lock(&data->lock);
902 clk_enable(data->clk);
904 value = data->tmu_read(data);
908 *temp = code_to_temp(data, value) * MCELSIUS;
910 clk_disable(data->clk);
911 mutex_unlock(&data->lock);
916 #ifdef CONFIG_THERMAL_EMULATION
917 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
923 if (data->soc != SOC_ARCH_EXYNOS5440) {
924 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
925 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
927 if (data->soc == SOC_ARCH_EXYNOS7) {
928 val &= ~(EXYNOS7_EMUL_DATA_MASK <<
929 EXYNOS7_EMUL_DATA_SHIFT);
930 val |= (temp_to_code(data, temp) <<
931 EXYNOS7_EMUL_DATA_SHIFT) |
934 val &= ~(EXYNOS_EMUL_DATA_MASK <<
935 EXYNOS_EMUL_DATA_SHIFT);
936 val |= (temp_to_code(data, temp) <<
937 EXYNOS_EMUL_DATA_SHIFT) |
941 val &= ~EXYNOS_EMUL_ENABLE;
947 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
953 if (data->soc == SOC_ARCH_EXYNOS5260)
954 emul_con = EXYNOS5260_EMUL_CON;
955 else if (data->soc == SOC_ARCH_EXYNOS5433)
956 emul_con = EXYNOS5433_TMU_EMUL_CON;
957 else if (data->soc == SOC_ARCH_EXYNOS7)
958 emul_con = EXYNOS7_TMU_REG_EMUL_CON;
960 emul_con = EXYNOS_EMUL_CON;
962 val = readl(data->base + emul_con);
963 val = get_emul_con_reg(data, val, temp);
964 writel(val, data->base + emul_con);
967 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
972 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
973 val = get_emul_con_reg(data, val, temp);
974 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
977 static int exynos_tmu_set_emulation(void *drv_data, int temp)
979 struct exynos_tmu_data *data = drv_data;
982 if (data->soc == SOC_ARCH_EXYNOS4210)
985 if (temp && temp < MCELSIUS)
988 mutex_lock(&data->lock);
989 clk_enable(data->clk);
990 data->tmu_set_emulation(data, temp);
991 clk_disable(data->clk);
992 mutex_unlock(&data->lock);
998 #define exynos4412_tmu_set_emulation NULL
999 #define exynos5440_tmu_set_emulation NULL
1000 static int exynos_tmu_set_emulation(void *drv_data, int temp)
1002 #endif /* CONFIG_THERMAL_EMULATION */
1004 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
1006 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
1008 /* "temp_code" should range between 75 and 175 */
1009 return (ret < 75 || ret > 175) ? -ENODATA : ret;
1012 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
1014 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
1017 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
1019 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
1022 static int exynos7_tmu_read(struct exynos_tmu_data *data)
1024 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
1025 EXYNOS7_TMU_TEMP_MASK;
1028 static void exynos_tmu_work(struct work_struct *work)
1030 struct exynos_tmu_data *data = container_of(work,
1031 struct exynos_tmu_data, irq_work);
1032 unsigned int val_type;
1034 if (!IS_ERR(data->clk_sec))
1035 clk_enable(data->clk_sec);
1036 /* Find which sensor generated this interrupt */
1037 if (data->soc == SOC_ARCH_EXYNOS5440) {
1038 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
1039 if (!((val_type >> data->id) & 0x1))
1042 if (!IS_ERR(data->clk_sec))
1043 clk_disable(data->clk_sec);
1045 exynos_report_trigger(data);
1046 mutex_lock(&data->lock);
1047 clk_enable(data->clk);
1049 /* TODO: take action based on particular interrupt */
1050 data->tmu_clear_irqs(data);
1052 clk_disable(data->clk);
1053 mutex_unlock(&data->lock);
1055 enable_irq(data->irq);
1058 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
1060 unsigned int val_irq;
1061 u32 tmu_intstat, tmu_intclear;
1063 if (data->soc == SOC_ARCH_EXYNOS5260) {
1064 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
1065 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
1066 } else if (data->soc == SOC_ARCH_EXYNOS7) {
1067 tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
1068 tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
1069 } else if (data->soc == SOC_ARCH_EXYNOS5433) {
1070 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
1071 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
1073 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
1074 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
1077 val_irq = readl(data->base + tmu_intstat);
1079 * Clear the interrupts. Please note that the documentation for
1080 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
1081 * states that INTCLEAR register has a different placing of bits
1082 * responsible for FALL IRQs than INTSTAT register. Exynos5420
1083 * and Exynos5440 documentation is correct (Exynos4210 doesn't
1084 * support FALL IRQs at all).
1086 writel(val_irq, data->base + tmu_intclear);
1089 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
1091 unsigned int val_irq;
1093 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
1094 /* clear the interrupts */
1095 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
1098 static irqreturn_t exynos_tmu_irq(int irq, void *id)
1100 struct exynos_tmu_data *data = id;
1102 disable_irq_nosync(irq);
1103 schedule_work(&data->irq_work);
1108 static const struct of_device_id exynos_tmu_match[] = {
1109 { .compatible = "samsung,exynos3250-tmu", },
1110 { .compatible = "samsung,exynos4210-tmu", },
1111 { .compatible = "samsung,exynos4412-tmu", },
1112 { .compatible = "samsung,exynos5250-tmu", },
1113 { .compatible = "samsung,exynos5260-tmu", },
1114 { .compatible = "samsung,exynos5420-tmu", },
1115 { .compatible = "samsung,exynos5420-tmu-ext-triminfo", },
1116 { .compatible = "samsung,exynos5433-tmu", },
1117 { .compatible = "samsung,exynos5440-tmu", },
1118 { .compatible = "samsung,exynos7-tmu", },
1121 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
1123 static int exynos_of_get_soc_type(struct device_node *np)
1125 if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
1126 return SOC_ARCH_EXYNOS3250;
1127 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
1128 return SOC_ARCH_EXYNOS4210;
1129 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
1130 return SOC_ARCH_EXYNOS4412;
1131 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
1132 return SOC_ARCH_EXYNOS5250;
1133 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
1134 return SOC_ARCH_EXYNOS5260;
1135 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
1136 return SOC_ARCH_EXYNOS5420;
1137 else if (of_device_is_compatible(np,
1138 "samsung,exynos5420-tmu-ext-triminfo"))
1139 return SOC_ARCH_EXYNOS5420_TRIMINFO;
1140 else if (of_device_is_compatible(np, "samsung,exynos5433-tmu"))
1141 return SOC_ARCH_EXYNOS5433;
1142 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
1143 return SOC_ARCH_EXYNOS5440;
1144 else if (of_device_is_compatible(np, "samsung,exynos7-tmu"))
1145 return SOC_ARCH_EXYNOS7;
1150 static int exynos_of_sensor_conf(struct device_node *np,
1151 struct exynos_tmu_platform_data *pdata)
1158 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
1159 pdata->gain = (u8)value;
1160 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
1161 pdata->reference_voltage = (u8)value;
1162 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
1163 pdata->noise_cancel_mode = (u8)value;
1165 of_property_read_u32(np, "samsung,tmu_efuse_value",
1166 &pdata->efuse_value);
1167 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
1168 &pdata->min_efuse_value);
1169 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
1170 &pdata->max_efuse_value);
1172 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
1173 pdata->first_point_trim = (u8)value;
1174 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
1175 pdata->second_point_trim = (u8)value;
1176 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
1177 pdata->default_temp_offset = (u8)value;
1179 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1185 static int exynos_map_dt_data(struct platform_device *pdev)
1187 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1188 struct exynos_tmu_platform_data *pdata;
1189 struct resource res;
1191 if (!data || !pdev->dev.of_node)
1194 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
1198 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1199 if (data->irq <= 0) {
1200 dev_err(&pdev->dev, "failed to get IRQ\n");
1204 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
1205 dev_err(&pdev->dev, "failed to get Resource 0\n");
1209 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1211 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1212 return -EADDRNOTAVAIL;
1215 pdata = devm_kzalloc(&pdev->dev,
1216 sizeof(struct exynos_tmu_platform_data),
1221 exynos_of_sensor_conf(pdev->dev.of_node, pdata);
1222 data->pdata = pdata;
1223 data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
1225 switch (data->soc) {
1226 case SOC_ARCH_EXYNOS4210:
1227 data->tmu_initialize = exynos4210_tmu_initialize;
1228 data->tmu_control = exynos4210_tmu_control;
1229 data->tmu_read = exynos4210_tmu_read;
1230 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1233 case SOC_ARCH_EXYNOS3250:
1234 case SOC_ARCH_EXYNOS4412:
1235 case SOC_ARCH_EXYNOS5250:
1236 case SOC_ARCH_EXYNOS5260:
1237 case SOC_ARCH_EXYNOS5420:
1238 case SOC_ARCH_EXYNOS5420_TRIMINFO:
1239 data->tmu_initialize = exynos4412_tmu_initialize;
1240 data->tmu_control = exynos4210_tmu_control;
1241 data->tmu_read = exynos4412_tmu_read;
1242 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1243 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1246 case SOC_ARCH_EXYNOS5433:
1247 data->tmu_initialize = exynos5433_tmu_initialize;
1248 data->tmu_control = exynos5433_tmu_control;
1249 data->tmu_read = exynos4412_tmu_read;
1250 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1251 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1254 case SOC_ARCH_EXYNOS5440:
1255 data->tmu_initialize = exynos5440_tmu_initialize;
1256 data->tmu_control = exynos5440_tmu_control;
1257 data->tmu_read = exynos5440_tmu_read;
1258 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1259 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1262 case SOC_ARCH_EXYNOS7:
1263 data->tmu_initialize = exynos7_tmu_initialize;
1264 data->tmu_control = exynos7_tmu_control;
1265 data->tmu_read = exynos7_tmu_read;
1266 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1267 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1271 dev_err(&pdev->dev, "Platform not supported\n");
1276 * Check if the TMU shares some registers and then try to map the
1277 * memory of common registers.
1279 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
1280 data->soc != SOC_ARCH_EXYNOS5440)
1283 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
1284 dev_err(&pdev->dev, "failed to get Resource 1\n");
1288 data->base_second = devm_ioremap(&pdev->dev, res.start,
1289 resource_size(&res));
1290 if (!data->base_second) {
1291 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1298 static const struct thermal_zone_of_device_ops exynos_sensor_ops = {
1299 .get_temp = exynos_get_temp,
1300 .set_emul_temp = exynos_tmu_set_emulation,
1303 static int exynos_tmu_probe(struct platform_device *pdev)
1305 struct exynos_tmu_data *data;
1308 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1313 platform_set_drvdata(pdev, data);
1314 mutex_init(&data->lock);
1317 * Try enabling the regulator if found
1318 * TODO: Add regulator as an SOC feature, so that regulator enable
1319 * is a compulsory call.
1321 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
1322 if (!IS_ERR(data->regulator)) {
1323 ret = regulator_enable(data->regulator);
1325 dev_err(&pdev->dev, "failed to enable vtmu\n");
1329 if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
1330 return -EPROBE_DEFER;
1331 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
1334 ret = exynos_map_dt_data(pdev);
1338 INIT_WORK(&data->irq_work, exynos_tmu_work);
1340 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1341 if (IS_ERR(data->clk)) {
1342 dev_err(&pdev->dev, "Failed to get clock\n");
1343 ret = PTR_ERR(data->clk);
1347 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1348 if (IS_ERR(data->clk_sec)) {
1349 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1350 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1351 ret = PTR_ERR(data->clk_sec);
1355 ret = clk_prepare(data->clk_sec);
1357 dev_err(&pdev->dev, "Failed to get clock\n");
1362 ret = clk_prepare(data->clk);
1364 dev_err(&pdev->dev, "Failed to get clock\n");
1368 switch (data->soc) {
1369 case SOC_ARCH_EXYNOS5433:
1370 case SOC_ARCH_EXYNOS7:
1371 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1372 if (IS_ERR(data->sclk)) {
1373 dev_err(&pdev->dev, "Failed to get sclk\n");
1374 ret = PTR_ERR(data->sclk);
1377 ret = clk_prepare_enable(data->sclk);
1379 dev_err(&pdev->dev, "Failed to enable sclk\n");
1389 * data->tzd must be registered before calling exynos_tmu_initialize(),
1390 * requesting irq and calling exynos_tmu_control().
1392 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
1393 &exynos_sensor_ops);
1394 if (IS_ERR(data->tzd)) {
1395 ret = PTR_ERR(data->tzd);
1396 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret);
1400 ret = exynos_tmu_initialize(pdev);
1402 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1406 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1407 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1409 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1413 exynos_tmu_control(pdev, true);
1417 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1419 clk_disable_unprepare(data->sclk);
1421 clk_unprepare(data->clk);
1423 if (!IS_ERR(data->clk_sec))
1424 clk_unprepare(data->clk_sec);
1426 if (!IS_ERR(data->regulator))
1427 regulator_disable(data->regulator);
1432 static int exynos_tmu_remove(struct platform_device *pdev)
1434 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1435 struct thermal_zone_device *tzd = data->tzd;
1437 thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
1438 exynos_tmu_control(pdev, false);
1440 clk_disable_unprepare(data->sclk);
1441 clk_unprepare(data->clk);
1442 if (!IS_ERR(data->clk_sec))
1443 clk_unprepare(data->clk_sec);
1445 if (!IS_ERR(data->regulator))
1446 regulator_disable(data->regulator);
1451 #ifdef CONFIG_PM_SLEEP
1452 static int exynos_tmu_suspend(struct device *dev)
1454 exynos_tmu_control(to_platform_device(dev), false);
1459 static int exynos_tmu_resume(struct device *dev)
1461 struct platform_device *pdev = to_platform_device(dev);
1463 exynos_tmu_initialize(pdev);
1464 exynos_tmu_control(pdev, true);
1469 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1470 exynos_tmu_suspend, exynos_tmu_resume);
1471 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
1473 #define EXYNOS_TMU_PM NULL
1476 static struct platform_driver exynos_tmu_driver = {
1478 .name = "exynos-tmu",
1479 .pm = EXYNOS_TMU_PM,
1480 .of_match_table = exynos_tmu_match,
1482 .probe = exynos_tmu_probe,
1483 .remove = exynos_tmu_remove,
1486 module_platform_driver(exynos_tmu_driver);
1488 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1489 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1490 MODULE_LICENSE("GPL");
1491 MODULE_ALIAS("platform:exynos-tmu");