drivers/thermal/samsung/exynos_tmu.c

   1 /*
   2  * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
   3  *
   4  *  Copyright (C) 2014 Samsung Electronics
   5  *  Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
   6  *  Lukasz Majewski <l.majewski@samsung.com>
   7  *
   8  *  Copyright (C) 2011 Samsung Electronics
   9  *  Donggeun Kim <dg77.kim@samsung.com>
  10  *  Amit Daniel Kachhap <amit.kachhap@linaro.org>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  25  *
  26  */
  27
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/module.h>
  32 #include <linux/of.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/regulator/consumer.h>
  37
  38 #include "exynos_tmu.h"
  39 #include "../thermal_core.h"
  40
  41 /* Exynos generic registers */
  42 #define EXYNOS_TMU_REG_TRIMINFO         0x0
  43 #define EXYNOS_TMU_REG_CONTROL          0x20
  44 #define EXYNOS_TMU_REG_STATUS           0x28
  45 #define EXYNOS_TMU_REG_CURRENT_TEMP     0x40
  46 #define EXYNOS_TMU_REG_INTEN            0x70
  47 #define EXYNOS_TMU_REG_INTSTAT          0x74
  48 #define EXYNOS_TMU_REG_INTCLEAR         0x78
  49
  50 #define EXYNOS_TMU_TEMP_MASK            0xff
  51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT    24
  52 #define EXYNOS_TMU_REF_VOLTAGE_MASK     0x1f
  53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK   0xf
  54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT  8
  55 #define EXYNOS_TMU_CORE_EN_SHIFT        0
  56
  57 /* Exynos3250 specific registers */
  58 #define EXYNOS_TMU_TRIMINFO_CON1        0x10
  59
  60 /* Exynos4210 specific registers */
  61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP       0x44
  62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0  0x50
  63
  64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
  65 #define EXYNOS_TMU_TRIMINFO_CON2        0x14
  66 #define EXYNOS_THD_TEMP_RISE            0x50
  67 #define EXYNOS_THD_TEMP_FALL            0x54
  68 #define EXYNOS_EMUL_CON         0x80
  69
  70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE   1
  71 #define EXYNOS_TRIMINFO_25_SHIFT        0
  72 #define EXYNOS_TRIMINFO_85_SHIFT        8
  73 #define EXYNOS_TMU_TRIP_MODE_SHIFT      13
  74 #define EXYNOS_TMU_TRIP_MODE_MASK       0x7
  75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT  12
  76
  77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT    0
  78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT    4
  79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT    8
  80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT    12
  81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT    16
  82
  83 #define EXYNOS_EMUL_TIME        0x57F0
  84 #define EXYNOS_EMUL_TIME_MASK   0xffff
  85 #define EXYNOS_EMUL_TIME_SHIFT  16
  86 #define EXYNOS_EMUL_DATA_SHIFT  8
  87 #define EXYNOS_EMUL_DATA_MASK   0xFF
  88 #define EXYNOS_EMUL_ENABLE      0x1
  89
  90 /* Exynos5260 specific */
  91 #define EXYNOS5260_TMU_REG_INTEN                0xC0
  92 #define EXYNOS5260_TMU_REG_INTSTAT              0xC4
  93 #define EXYNOS5260_TMU_REG_INTCLEAR             0xC8
  94 #define EXYNOS5260_EMUL_CON                     0x100
  95
  96 /* Exynos4412 specific */
  97 #define EXYNOS4412_MUX_ADDR_VALUE          6
  98 #define EXYNOS4412_MUX_ADDR_SHIFT          20
  99
 100 /* Exynos5433 specific registers */
 101 #define EXYNOS5433_TMU_REG_CONTROL1             0x024
 102 #define EXYNOS5433_TMU_SAMPLING_INTERVAL        0x02c
 103 #define EXYNOS5433_TMU_COUNTER_VALUE0           0x030
 104 #define EXYNOS5433_TMU_COUNTER_VALUE1           0x034
 105 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1        0x044
 106 #define EXYNOS5433_THD_TEMP_RISE3_0             0x050
 107 #define EXYNOS5433_THD_TEMP_RISE7_4             0x054
 108 #define EXYNOS5433_THD_TEMP_FALL3_0             0x060
 109 #define EXYNOS5433_THD_TEMP_FALL7_4             0x064
 110 #define EXYNOS5433_TMU_REG_INTEN                0x0c0
 111 #define EXYNOS5433_TMU_REG_INTPEND              0x0c8
 112 #define EXYNOS5433_TMU_EMUL_CON                 0x110
 113 #define EXYNOS5433_TMU_PD_DET_EN                0x130
 114
 115 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT     16
 116 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT     23
 117 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK      \
 118                         (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT)
 119 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK      BIT(23)
 120
 121 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING  0
 122 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING  1
 123
 124 #define EXYNOS5433_PD_DET_EN                    1
 125
 126 /*exynos5440 specific registers*/
 127 #define EXYNOS5440_TMU_S0_7_TRIM                0x000
 128 #define EXYNOS5440_TMU_S0_7_CTRL                0x020
 129 #define EXYNOS5440_TMU_S0_7_DEBUG               0x040
 130 #define EXYNOS5440_TMU_S0_7_TEMP                0x0f0
 131 #define EXYNOS5440_TMU_S0_7_TH0                 0x110
 132 #define EXYNOS5440_TMU_S0_7_TH1                 0x130
 133 #define EXYNOS5440_TMU_S0_7_TH2                 0x150
 134 #define EXYNOS5440_TMU_S0_7_IRQEN               0x210
 135 #define EXYNOS5440_TMU_S0_7_IRQ                 0x230
 136 /* exynos5440 common registers */
 137 #define EXYNOS5440_TMU_IRQ_STATUS               0x000
 138 #define EXYNOS5440_TMU_PMIN                     0x004
 139
 140 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT        0
 141 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT        1
 142 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT        2
 143 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT        3
 144 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT        4
 145 #define EXYNOS5440_TMU_TH_RISE4_SHIFT           24
 146 #define EXYNOS5440_EFUSE_SWAP_OFFSET            8
 147
 148 /* Exynos7 specific registers */
 149 #define EXYNOS7_THD_TEMP_RISE7_6                0x50
 150 #define EXYNOS7_THD_TEMP_FALL7_6                0x60
 151 #define EXYNOS7_TMU_REG_INTEN                   0x110
 152 #define EXYNOS7_TMU_REG_INTPEND                 0x118
 153 #define EXYNOS7_TMU_REG_EMUL_CON                0x160
 154
 155 #define EXYNOS7_TMU_TEMP_MASK                   0x1ff
 156 #define EXYNOS7_PD_DET_EN_SHIFT                 23
 157 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT           0
 158 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT           1
 159 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT           2
 160 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT           3
 161 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT           4
 162 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT           5
 163 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT           6
 164 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT           7
 165 #define EXYNOS7_EMUL_DATA_SHIFT                 7
 166 #define EXYNOS7_EMUL_DATA_MASK                  0x1ff
 167
 168 #define MCELSIUS        1000
 169 /**
 170  * struct exynos_tmu_data : A structure to hold the private data of the TMU
 171         driver
 172  * @id: identifier of the one instance of the TMU controller.
 173  * @pdata: pointer to the tmu platform/configuration data
 174  * @base: base address of the single instance of the TMU controller.
 175  * @base_second: base address of the common registers of the TMU controller.
 176  * @irq: irq number of the TMU controller.
 177  * @soc: id of the SOC type.
 178  * @irq_work: pointer to the irq work structure.
 179  * @lock: lock to implement synchronization.
 180  * @clk: pointer to the clock structure.
 181  * @clk_sec: pointer to the clock structure for accessing the base_second.
 182  * @sclk: pointer to the clock structure for accessing the tmu special clk.
 183  * @temp_error1: fused value of the first point trim.
 184  * @temp_error2: fused value of the second point trim.
 185  * @regulator: pointer to the TMU regulator structure.
 186  * @reg_conf: pointer to structure to register with core thermal.
 187  * @ntrip: number of supported trip points.
 188  * @enabled: current status of TMU device
 189  * @tmu_initialize: SoC specific TMU initialization method
 190  * @tmu_control: SoC specific TMU control method
 191  * @tmu_read: SoC specific TMU temperature read method
 192  * @tmu_set_emulation: SoC specific TMU emulation setting method
 193  * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
 194  */
 195 struct exynos_tmu_data {
 196         int id;
 197         struct exynos_tmu_platform_data *pdata;
 198         void __iomem *base;
 199         void __iomem *base_second;
 200         int irq;
 201         enum soc_type soc;
 202         struct work_struct irq_work;
 203         struct mutex lock;
 204         struct clk *clk, *clk_sec, *sclk;
 205         u16 temp_error1, temp_error2;
 206         struct regulator *regulator;
 207         struct thermal_zone_device *tzd;
 208         unsigned int ntrip;
 209         bool enabled;
 210
 211         int (*tmu_initialize)(struct platform_device *pdev);
 212         void (*tmu_control)(struct platform_device *pdev, bool on);
 213         int (*tmu_read)(struct exynos_tmu_data *data);
 214         void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp);
 215         void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
 216 };
 217
 218 static void exynos_report_trigger(struct exynos_tmu_data *p)
 219 {
 220         char data[10], *envp[] = { data, NULL };
 221         struct thermal_zone_device *tz = p->tzd;
 222         int temp;
 223         unsigned int i;
 224
 225         if (!tz) {
 226                 pr_err("No thermal zone device defined\n");
 227                 return;
 228         }
 229
 230         thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED);
 231
 232         mutex_lock(&tz->lock);
 233         /* Find the level for which trip happened */
 234         for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
 235                 tz->ops->get_trip_temp(tz, i, &temp);
 236                 if (tz->last_temperature < temp)
 237                         break;
 238         }
 239
 240         snprintf(data, sizeof(data), "%u", i);
 241         kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
 242         mutex_unlock(&tz->lock);
 243 }
 244
 245 /*
 246  * TMU treats temperature as a mapped temperature code.
 247  * The temperature is converted differently depending on the calibration type.
 248  */
 249 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
 250 {
 251         struct exynos_tmu_platform_data *pdata = data->pdata;
 252         int temp_code;
 253
 254         switch (pdata->cal_type) {
 255         case TYPE_TWO_POINT_TRIMMING:
 256                 temp_code = (temp - pdata->first_point_trim) *
 257                         (data->temp_error2 - data->temp_error1) /
 258                         (pdata->second_point_trim - pdata->first_point_trim) +
 259                         data->temp_error1;
 260                 break;
 261         case TYPE_ONE_POINT_TRIMMING:
 262                 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
 263                 break;
 264         default:
 265                 temp_code = temp + pdata->default_temp_offset;
 266                 break;
 267         }
 268
 269         return temp_code;
 270 }
 271
 272 /*
 273  * Calculate a temperature value from a temperature code.
 274  * The unit of the temperature is degree Celsius.
 275  */
 276 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
 277 {
 278         struct exynos_tmu_platform_data *pdata = data->pdata;
 279         int temp;
 280
 281         switch (pdata->cal_type) {
 282         case TYPE_TWO_POINT_TRIMMING:
 283                 temp = (temp_code - data->temp_error1) *
 284                         (pdata->second_point_trim - pdata->first_point_trim) /
 285                         (data->temp_error2 - data->temp_error1) +
 286                         pdata->first_point_trim;
 287                 break;
 288         case TYPE_ONE_POINT_TRIMMING:
 289                 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
 290                 break;
 291         default:
 292                 temp = temp_code - pdata->default_temp_offset;
 293                 break;
 294         }
 295
 296         return temp;
 297 }
 298
 299 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
 300 {
 301         struct exynos_tmu_platform_data *pdata = data->pdata;
 302
 303         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 304         data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
 305                                 EXYNOS_TMU_TEMP_MASK);
 306
 307         if (!data->temp_error1 ||
 308                 (pdata->min_efuse_value > data->temp_error1) ||
 309                 (data->temp_error1 > pdata->max_efuse_value))
 310                 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
 311
 312         if (!data->temp_error2)
 313                 data->temp_error2 =
 314                         (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
 315                         EXYNOS_TMU_TEMP_MASK;
 316 }
 317
 318 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
 319 {
 320         struct thermal_zone_device *tz = data->tzd;
 321         const struct thermal_trip * const trips =
 322                 of_thermal_get_trip_points(tz);
 323         unsigned long temp;
 324         int i;
 325
 326         if (!trips) {
 327                 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
 328                        __func__);
 329                 return 0;
 330         }
 331
 332         for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
 333                 if (trips[i].type == THERMAL_TRIP_CRITICAL)
 334                         continue;
 335
 336                 temp = trips[i].temperature / MCELSIUS;
 337                 if (falling)
 338                         temp -= (trips[i].hysteresis / MCELSIUS);
 339                 else
 340                         threshold &= ~(0xff << 8 * i);
 341
 342                 threshold |= temp_to_code(data, temp) << 8 * i;
 343         }
 344
 345         return threshold;
 346 }
 347
 348 static int exynos_tmu_initialize(struct platform_device *pdev)
 349 {
 350         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 351         int ret;
 352
 353         if (of_thermal_get_ntrips(data->tzd) > data->ntrip) {
 354                 dev_info(&pdev->dev,
 355                          "More trip points than supported by this TMU.\n");
 356                 dev_info(&pdev->dev,
 357                          "%d trip points should be configured in polling mode.\n",
 358                          (of_thermal_get_ntrips(data->tzd) - data->ntrip));
 359         }
 360
 361         mutex_lock(&data->lock);
 362         clk_enable(data->clk);
 363         if (!IS_ERR(data->clk_sec))
 364                 clk_enable(data->clk_sec);
 365         ret = data->tmu_initialize(pdev);
 366         clk_disable(data->clk);
 367         mutex_unlock(&data->lock);
 368         if (!IS_ERR(data->clk_sec))
 369                 clk_disable(data->clk_sec);
 370
 371         return ret;
 372 }
 373
 374 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
 375 {
 376         struct exynos_tmu_platform_data *pdata = data->pdata;
 377
 378         if (data->soc == SOC_ARCH_EXYNOS4412 ||
 379             data->soc == SOC_ARCH_EXYNOS3250)
 380                 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
 381
 382         con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
 383         con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
 384
 385         con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
 386         con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
 387
 388         if (pdata->noise_cancel_mode) {
 389                 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
 390                 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
 391         }
 392
 393         return con;
 394 }
 395
 396 static void exynos_tmu_control(struct platform_device *pdev, bool on)
 397 {
 398         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 399
 400         mutex_lock(&data->lock);
 401         clk_enable(data->clk);
 402         data->tmu_control(pdev, on);
 403         data->enabled = on;
 404         clk_disable(data->clk);
 405         mutex_unlock(&data->lock);
 406 }
 407
 408 static int exynos4210_tmu_initialize(struct platform_device *pdev)
 409 {
 410         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 411         struct thermal_zone_device *tz = data->tzd;
 412         const struct thermal_trip * const trips =
 413                 of_thermal_get_trip_points(tz);
 414         int ret = 0, threshold_code, i;
 415         unsigned long reference, temp;
 416         unsigned int status;
 417
 418         if (!trips) {
 419                 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
 420                        __func__);
 421                 ret = -ENODEV;
 422                 goto out;
 423         }
 424
 425         status = readb(data->base + EXYNOS_TMU_REG_STATUS);
 426         if (!status) {
 427                 ret = -EBUSY;
 428                 goto out;
 429         }
 430
 431         sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
 432
 433         /* Write temperature code for threshold */
 434         reference = trips[0].temperature / MCELSIUS;
 435         threshold_code = temp_to_code(data, reference);
 436         if (threshold_code < 0) {
 437                 ret = threshold_code;
 438                 goto out;
 439         }
 440         writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
 441
 442         for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
 443                 temp = trips[i].temperature / MCELSIUS;
 444                 writeb(temp - reference, data->base +
 445                        EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
 446         }
 447
 448         data->tmu_clear_irqs(data);
 449 out:
 450         return ret;
 451 }
 452
 453 static int exynos4412_tmu_initialize(struct platform_device *pdev)
 454 {
 455         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 456         const struct thermal_trip * const trips =
 457                 of_thermal_get_trip_points(data->tzd);
 458         unsigned int status, trim_info, con, ctrl, rising_threshold;
 459         int ret = 0, threshold_code, i;
 460         unsigned long crit_temp = 0;
 461
 462         status = readb(data->base + EXYNOS_TMU_REG_STATUS);
 463         if (!status) {
 464                 ret = -EBUSY;
 465                 goto out;
 466         }
 467
 468         if (data->soc == SOC_ARCH_EXYNOS3250 ||
 469             data->soc == SOC_ARCH_EXYNOS4412 ||
 470             data->soc == SOC_ARCH_EXYNOS5250) {
 471                 if (data->soc == SOC_ARCH_EXYNOS3250) {
 472                         ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
 473                         ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
 474                         writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
 475                 }
 476                 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
 477                 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
 478                 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
 479         }
 480
 481         /* On exynos5420 the triminfo register is in the shared space */
 482         if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
 483                 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
 484         else
 485                 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 486
 487         sanitize_temp_error(data, trim_info);
 488
 489         /* Write temperature code for rising and falling threshold */
 490         rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
 491         rising_threshold = get_th_reg(data, rising_threshold, false);
 492         writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
 493         writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
 494
 495         data->tmu_clear_irqs(data);
 496
 497         /* if last threshold limit is also present */
 498         for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
 499                 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
 500                         crit_temp = trips[i].temperature;
 501                         break;
 502                 }
 503         }
 504
 505         if (i == of_thermal_get_ntrips(data->tzd)) {
 506                 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
 507                        __func__);
 508                 ret = -EINVAL;
 509                 goto out;
 510         }
 511
 512         threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
 513         /* 1-4 level to be assigned in th0 reg */
 514         rising_threshold &= ~(0xff << 8 * i);
 515         rising_threshold |= threshold_code << 8 * i;
 516         writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
 517         con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
 518         con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
 519         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 520
 521 out:
 522         return ret;
 523 }
 524
 525 static int exynos5433_tmu_initialize(struct platform_device *pdev)
 526 {
 527         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 528         struct exynos_tmu_platform_data *pdata = data->pdata;
 529         struct thermal_zone_device *tz = data->tzd;
 530         unsigned int status, trim_info;
 531         unsigned int rising_threshold = 0, falling_threshold = 0;
 532         int temp, temp_hist;
 533         int ret = 0, threshold_code, i, sensor_id, cal_type;
 534
 535         status = readb(data->base + EXYNOS_TMU_REG_STATUS);
 536         if (!status) {
 537                 ret = -EBUSY;
 538                 goto out;
 539         }
 540
 541         trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 542         sanitize_temp_error(data, trim_info);
 543
 544         /* Read the temperature sensor id */
 545         sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK)
 546                                 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT;
 547         dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id);
 548
 549         /* Read the calibration mode */
 550         writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO);
 551         cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK)
 552                                 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT;
 553
 554         switch (cal_type) {
 555         case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING:
 556                 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
 557                 break;
 558         case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING:
 559                 pdata->cal_type = TYPE_TWO_POINT_TRIMMING;
 560                 break;
 561         default:
 562                 pdata->cal_type = TYPE_ONE_POINT_TRIMMING;
 563                 break;
 564         }
 565
 566         dev_info(&pdev->dev, "Calibration type is %d-point calibration\n",
 567                         cal_type ?  2 : 1);
 568
 569         /* Write temperature code for rising and falling threshold */
 570         for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
 571                 int rising_reg_offset, falling_reg_offset;
 572                 int j = 0;
 573
 574                 switch (i) {
 575                 case 0:
 576                 case 1:
 577                 case 2:
 578                 case 3:
 579                         rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0;
 580                         falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0;
 581                         j = i;
 582                         break;
 583                 case 4:
 584                 case 5:
 585                 case 6:
 586                 case 7:
 587                         rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4;
 588                         falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4;
 589                         j = i - 4;
 590                         break;
 591                 default:
 592                         continue;
 593                 }
 594
 595                 /* Write temperature code for rising threshold */
 596                 tz->ops->get_trip_temp(tz, i, &temp);
 597                 temp /= MCELSIUS;
 598                 threshold_code = temp_to_code(data, temp);
 599
 600                 rising_threshold = readl(data->base + rising_reg_offset);
 601                 rising_threshold &= ~(0xff << j * 8);
 602                 rising_threshold |= (threshold_code << j * 8);
 603                 writel(rising_threshold, data->base + rising_reg_offset);
 604
 605                 /* Write temperature code for falling threshold */
 606                 tz->ops->get_trip_hyst(tz, i, &temp_hist);
 607                 temp_hist = temp - (temp_hist / MCELSIUS);
 608                 threshold_code = temp_to_code(data, temp_hist);
 609
 610                 falling_threshold = readl(data->base + falling_reg_offset);
 611                 falling_threshold &= ~(0xff << j * 8);
 612                 falling_threshold |= (threshold_code << j * 8);
 613                 writel(falling_threshold, data->base + falling_reg_offset);
 614         }
 615
 616         data->tmu_clear_irqs(data);
 617 out:
 618         return ret;
 619 }
 620
 621 static int exynos5440_tmu_initialize(struct platform_device *pdev)
 622 {
 623         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 624         unsigned int trim_info = 0, con, rising_threshold;
 625         int threshold_code;
 626         int crit_temp = 0;
 627
 628         /*
 629          * For exynos5440 soc triminfo value is swapped between TMU0 and
 630          * TMU2, so the below logic is needed.
 631          */
 632         switch (data->id) {
 633         case 0:
 634                 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
 635                                  EXYNOS5440_TMU_S0_7_TRIM);
 636                 break;
 637         case 1:
 638                 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
 639                 break;
 640         case 2:
 641                 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
 642                                   EXYNOS5440_TMU_S0_7_TRIM);
 643         }
 644         sanitize_temp_error(data, trim_info);
 645
 646         /* Write temperature code for rising and falling threshold */
 647         rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
 648         rising_threshold = get_th_reg(data, rising_threshold, false);
 649         writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
 650         writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
 651
 652         data->tmu_clear_irqs(data);
 653
 654         /* if last threshold limit is also present */
 655         if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
 656                 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
 657                 /* 5th level to be assigned in th2 reg */
 658                 rising_threshold =
 659                         threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
 660                 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
 661                 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
 662                 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
 663                 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
 664         }
 665         /* Clear the PMIN in the common TMU register */
 666         if (!data->id)
 667                 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
 668
 669         return 0;
 670 }
 671
 672 static int exynos7_tmu_initialize(struct platform_device *pdev)
 673 {
 674         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 675         struct thermal_zone_device *tz = data->tzd;
 676         struct exynos_tmu_platform_data *pdata = data->pdata;
 677         unsigned int status, trim_info;
 678         unsigned int rising_threshold = 0, falling_threshold = 0;
 679         int ret = 0, threshold_code, i;
 680         int temp, temp_hist;
 681         unsigned int reg_off, bit_off;
 682
 683         status = readb(data->base + EXYNOS_TMU_REG_STATUS);
 684         if (!status) {
 685                 ret = -EBUSY;
 686                 goto out;
 687         }
 688
 689         trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
 690
 691         data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
 692         if (!data->temp_error1 ||
 693             (pdata->min_efuse_value > data->temp_error1) ||
 694             (data->temp_error1 > pdata->max_efuse_value))
 695                 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
 696
 697         /* Write temperature code for rising and falling threshold */
 698         for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
 699                 /*
 700                  * On exynos7 there are 4 rising and 4 falling threshold
 701                  * registers (0x50-0x5c and 0x60-0x6c respectively). Each
 702                  * register holds the value of two threshold levels (at bit
 703                  * offsets 0 and 16). Based on the fact that there are atmost
 704                  * eight possible trigger levels, calculate the register and
 705                  * bit offsets where the threshold levels are to be written.
 706                  *
 707                  * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
 708                  * [24:16] - Threshold level 7
 709                  * [8:0] - Threshold level 6
 710                  * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
 711                  * [24:16] - Threshold level 5
 712                  * [8:0] - Threshold level 4
 713                  *
 714                  * and similarly for falling thresholds.
 715                  *
 716                  * Based on the above, calculate the register and bit offsets
 717                  * for rising/falling threshold levels and populate them.
 718                  */
 719                 reg_off = ((7 - i) / 2) * 4;
 720                 bit_off = ((8 - i) % 2);
 721
 722                 tz->ops->get_trip_temp(tz, i, &temp);
 723                 temp /= MCELSIUS;
 724
 725                 tz->ops->get_trip_hyst(tz, i, &temp_hist);
 726                 temp_hist = temp - (temp_hist / MCELSIUS);
 727
 728                 /* Set 9-bit temperature code for rising threshold levels */
 729                 threshold_code = temp_to_code(data, temp);
 730                 rising_threshold = readl(data->base +
 731                         EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
 732                 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
 733                 rising_threshold |= threshold_code << (16 * bit_off);
 734                 writel(rising_threshold,
 735                        data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
 736
 737                 /* Set 9-bit temperature code for falling threshold levels */
 738                 threshold_code = temp_to_code(data, temp_hist);
 739                 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
 740                 falling_threshold |= threshold_code << (16 * bit_off);
 741                 writel(falling_threshold,
 742                        data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
 743         }
 744
 745         data->tmu_clear_irqs(data);
 746 out:
 747         return ret;
 748 }
 749
 750 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
 751 {
 752         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 753         struct thermal_zone_device *tz = data->tzd;
 754         unsigned int con, interrupt_en;
 755
 756         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 757
 758         if (on) {
 759                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 760                 interrupt_en =
 761                         (of_thermal_is_trip_valid(tz, 3)
 762                          << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
 763                         (of_thermal_is_trip_valid(tz, 2)
 764                          << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
 765                         (of_thermal_is_trip_valid(tz, 1)
 766                          << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
 767                         (of_thermal_is_trip_valid(tz, 0)
 768                          << EXYNOS_TMU_INTEN_RISE0_SHIFT);
 769
 770                 if (data->soc != SOC_ARCH_EXYNOS4210)
 771                         interrupt_en |=
 772                                 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 773         } else {
 774                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 775                 interrupt_en = 0; /* Disable all interrupts */
 776         }
 777         writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
 778         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 779 }
 780
 781 static void exynos5433_tmu_control(struct platform_device *pdev, bool on)
 782 {
 783         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 784         struct thermal_zone_device *tz = data->tzd;
 785         unsigned int con, interrupt_en, pd_det_en;
 786
 787         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 788
 789         if (on) {
 790                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 791                 interrupt_en =
 792                         (of_thermal_is_trip_valid(tz, 7)
 793                         << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
 794                         (of_thermal_is_trip_valid(tz, 6)
 795                         << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
 796                         (of_thermal_is_trip_valid(tz, 5)
 797                         << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
 798                         (of_thermal_is_trip_valid(tz, 4)
 799                         << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
 800                         (of_thermal_is_trip_valid(tz, 3)
 801                         << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
 802                         (of_thermal_is_trip_valid(tz, 2)
 803                         << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
 804                         (of_thermal_is_trip_valid(tz, 1)
 805                         << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
 806                         (of_thermal_is_trip_valid(tz, 0)
 807                         << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
 808
 809                 interrupt_en |=
 810                         interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 811         } else {
 812                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 813                 interrupt_en = 0; /* Disable all interrupts */
 814         }
 815
 816         pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0;
 817
 818         writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN);
 819         writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN);
 820         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 821 }
 822
 823 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
 824 {
 825         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 826         struct thermal_zone_device *tz = data->tzd;
 827         unsigned int con, interrupt_en;
 828
 829         con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
 830
 831         if (on) {
 832                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 833                 interrupt_en =
 834                         (of_thermal_is_trip_valid(tz, 3)
 835                          << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
 836                         (of_thermal_is_trip_valid(tz, 2)
 837                          << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
 838                         (of_thermal_is_trip_valid(tz, 1)
 839                          << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
 840                         (of_thermal_is_trip_valid(tz, 0)
 841                          << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
 842                 interrupt_en |=
 843                         interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
 844         } else {
 845                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 846                 interrupt_en = 0; /* Disable all interrupts */
 847         }
 848         writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
 849         writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
 850 }
 851
 852 static void exynos7_tmu_control(struct platform_device *pdev, bool on)
 853 {
 854         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
 855         struct thermal_zone_device *tz = data->tzd;
 856         unsigned int con, interrupt_en;
 857
 858         con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
 859
 860         if (on) {
 861                 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
 862                 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT);
 863                 interrupt_en =
 864                         (of_thermal_is_trip_valid(tz, 7)
 865                         << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
 866                         (of_thermal_is_trip_valid(tz, 6)
 867                         << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
 868                         (of_thermal_is_trip_valid(tz, 5)
 869                         << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
 870                         (of_thermal_is_trip_valid(tz, 4)
 871                         << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
 872                         (of_thermal_is_trip_valid(tz, 3)
 873                         << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
 874                         (of_thermal_is_trip_valid(tz, 2)
 875                         << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
 876                         (of_thermal_is_trip_valid(tz, 1)
 877                         << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
 878                         (of_thermal_is_trip_valid(tz, 0)
 879                         << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
 880
 881                 interrupt_en |=
 882                         interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
 883         } else {
 884                 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
 885                 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT);
 886                 interrupt_en = 0; /* Disable all interrupts */
 887         }
 888
 889         writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
 890         writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
 891 }
 892
 893 static int exynos_get_temp(void *p, int *temp)
 894 {
 895         struct exynos_tmu_data *data = p;
 896         int value, ret = 0;
 897
 898         if (!data || !data->tmu_read || !data->enabled)
 899                 return -EINVAL;
 900
 901         mutex_lock(&data->lock);
 902         clk_enable(data->clk);
 903
 904         value = data->tmu_read(data);
 905         if (value < 0)
 906                 ret = value;
 907         else
 908                 *temp = code_to_temp(data, value) * MCELSIUS;
 909
 910         clk_disable(data->clk);
 911         mutex_unlock(&data->lock);
 912
 913         return ret;
 914 }
 915
 916 #ifdef CONFIG_THERMAL_EMULATION
 917 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
 918                             int temp)
 919 {
 920         if (temp) {
 921                 temp /= MCELSIUS;
 922
 923                 if (data->soc != SOC_ARCH_EXYNOS5440) {
 924                         val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
 925                         val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
 926                 }
 927                 if (data->soc == SOC_ARCH_EXYNOS7) {
 928                         val &= ~(EXYNOS7_EMUL_DATA_MASK <<
 929                                 EXYNOS7_EMUL_DATA_SHIFT);
 930                         val |= (temp_to_code(data, temp) <<
 931                                 EXYNOS7_EMUL_DATA_SHIFT) |
 932                                 EXYNOS_EMUL_ENABLE;
 933                 } else {
 934                         val &= ~(EXYNOS_EMUL_DATA_MASK <<
 935                                 EXYNOS_EMUL_DATA_SHIFT);
 936                         val |= (temp_to_code(data, temp) <<
 937                                 EXYNOS_EMUL_DATA_SHIFT) |
 938                                 EXYNOS_EMUL_ENABLE;
 939                 }
 940         } else {
 941                 val &= ~EXYNOS_EMUL_ENABLE;
 942         }
 943
 944         return val;
 945 }
 946
 947 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
 948                                          int temp)
 949 {
 950         unsigned int val;
 951         u32 emul_con;
 952
 953         if (data->soc == SOC_ARCH_EXYNOS5260)
 954                 emul_con = EXYNOS5260_EMUL_CON;
 955         else if (data->soc == SOC_ARCH_EXYNOS5433)
 956                 emul_con = EXYNOS5433_TMU_EMUL_CON;
 957         else if (data->soc == SOC_ARCH_EXYNOS7)
 958                 emul_con = EXYNOS7_TMU_REG_EMUL_CON;
 959         else
 960                 emul_con = EXYNOS_EMUL_CON;
 961
 962         val = readl(data->base + emul_con);
 963         val = get_emul_con_reg(data, val, temp);
 964         writel(val, data->base + emul_con);
 965 }
 966
 967 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
 968                                          int temp)
 969 {
 970         unsigned int val;
 971
 972         val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
 973         val = get_emul_con_reg(data, val, temp);
 974         writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
 975 }
 976
 977 static int exynos_tmu_set_emulation(void *drv_data, int temp)
 978 {
 979         struct exynos_tmu_data *data = drv_data;
 980         int ret = -EINVAL;
 981
 982         if (data->soc == SOC_ARCH_EXYNOS4210)
 983                 goto out;
 984
 985         if (temp && temp < MCELSIUS)
 986                 goto out;
 987
 988         mutex_lock(&data->lock);
 989         clk_enable(data->clk);
 990         data->tmu_set_emulation(data, temp);
 991         clk_disable(data->clk);
 992         mutex_unlock(&data->lock);
 993         return 0;
 994 out:
 995         return ret;
 996 }
 997 #else
 998 #define exynos4412_tmu_set_emulation NULL
 999 #define exynos5440_tmu_set_emulation NULL
1000 static int exynos_tmu_set_emulation(void *drv_data, int temp)
1001         { return -EINVAL; }
1002 #endif /* CONFIG_THERMAL_EMULATION */
1003
1004 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
1005 {
1006         int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
1007
1008         /* "temp_code" should range between 75 and 175 */
1009         return (ret < 75 || ret > 175) ? -ENODATA : ret;
1010 }
1011
1012 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
1013 {
1014         return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
1015 }
1016
1017 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
1018 {
1019         return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
1020 }
1021
1022 static int exynos7_tmu_read(struct exynos_tmu_data *data)
1023 {
1024         return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
1025                 EXYNOS7_TMU_TEMP_MASK;
1026 }
1027
1028 static void exynos_tmu_work(struct work_struct *work)
1029 {
1030         struct exynos_tmu_data *data = container_of(work,
1031                         struct exynos_tmu_data, irq_work);
1032         unsigned int val_type;
1033
1034         if (!IS_ERR(data->clk_sec))
1035                 clk_enable(data->clk_sec);
1036         /* Find which sensor generated this interrupt */
1037         if (data->soc == SOC_ARCH_EXYNOS5440) {
1038                 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
1039                 if (!((val_type >> data->id) & 0x1))
1040                         goto out;
1041         }
1042         if (!IS_ERR(data->clk_sec))
1043                 clk_disable(data->clk_sec);
1044
1045         exynos_report_trigger(data);
1046         mutex_lock(&data->lock);
1047         clk_enable(data->clk);
1048
1049         /* TODO: take action based on particular interrupt */
1050         data->tmu_clear_irqs(data);
1051
1052         clk_disable(data->clk);
1053         mutex_unlock(&data->lock);
1054 out:
1055         enable_irq(data->irq);
1056 }
1057
1058 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
1059 {
1060         unsigned int val_irq;
1061         u32 tmu_intstat, tmu_intclear;
1062
1063         if (data->soc == SOC_ARCH_EXYNOS5260) {
1064                 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
1065                 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
1066         } else if (data->soc == SOC_ARCH_EXYNOS7) {
1067                 tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
1068                 tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
1069         } else if (data->soc == SOC_ARCH_EXYNOS5433) {
1070                 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND;
1071                 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND;
1072         } else {
1073                 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
1074                 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
1075         }
1076
1077         val_irq = readl(data->base + tmu_intstat);
1078         /*
1079          * Clear the interrupts.  Please note that the documentation for
1080          * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
1081          * states that INTCLEAR register has a different placing of bits
1082          * responsible for FALL IRQs than INTSTAT register.  Exynos5420
1083          * and Exynos5440 documentation is correct (Exynos4210 doesn't
1084          * support FALL IRQs at all).
1085          */
1086         writel(val_irq, data->base + tmu_intclear);
1087 }
1088
1089 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
1090 {
1091         unsigned int val_irq;
1092
1093         val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
1094         /* clear the interrupts */
1095         writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
1096 }
1097
1098 static irqreturn_t exynos_tmu_irq(int irq, void *id)
1099 {
1100         struct exynos_tmu_data *data = id;
1101
1102         disable_irq_nosync(irq);
1103         schedule_work(&data->irq_work);
1104
1105         return IRQ_HANDLED;
1106 }
1107
1108 static const struct of_device_id exynos_tmu_match[] = {
1109         { .compatible = "samsung,exynos3250-tmu", },
1110         { .compatible = "samsung,exynos4210-tmu", },
1111         { .compatible = "samsung,exynos4412-tmu", },
1112         { .compatible = "samsung,exynos5250-tmu", },
1113         { .compatible = "samsung,exynos5260-tmu", },
1114         { .compatible = "samsung,exynos5420-tmu", },
1115         { .compatible = "samsung,exynos5420-tmu-ext-triminfo", },
1116         { .compatible = "samsung,exynos5433-tmu", },
1117         { .compatible = "samsung,exynos5440-tmu", },
1118         { .compatible = "samsung,exynos7-tmu", },
1119         { /* sentinel */ },
1120 };
1121 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
1122
1123 static int exynos_of_get_soc_type(struct device_node *np)
1124 {
1125         if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
1126                 return SOC_ARCH_EXYNOS3250;
1127         else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
1128                 return SOC_ARCH_EXYNOS4210;
1129         else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
1130                 return SOC_ARCH_EXYNOS4412;
1131         else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
1132                 return SOC_ARCH_EXYNOS5250;
1133         else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
1134                 return SOC_ARCH_EXYNOS5260;
1135         else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
1136                 return SOC_ARCH_EXYNOS5420;
1137         else if (of_device_is_compatible(np,
1138                                          "samsung,exynos5420-tmu-ext-triminfo"))
1139                 return SOC_ARCH_EXYNOS5420_TRIMINFO;
1140         else if (of_device_is_compatible(np, "samsung,exynos5433-tmu"))
1141                 return SOC_ARCH_EXYNOS5433;
1142         else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
1143                 return SOC_ARCH_EXYNOS5440;
1144         else if (of_device_is_compatible(np, "samsung,exynos7-tmu"))
1145                 return SOC_ARCH_EXYNOS7;
1146
1147         return -EINVAL;
1148 }
1149
1150 static int exynos_of_sensor_conf(struct device_node *np,
1151                                  struct exynos_tmu_platform_data *pdata)
1152 {
1153         u32 value;
1154         int ret;
1155
1156         of_node_get(np);
1157
1158         ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
1159         pdata->gain = (u8)value;
1160         of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
1161         pdata->reference_voltage = (u8)value;
1162         of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
1163         pdata->noise_cancel_mode = (u8)value;
1164
1165         of_property_read_u32(np, "samsung,tmu_efuse_value",
1166                              &pdata->efuse_value);
1167         of_property_read_u32(np, "samsung,tmu_min_efuse_value",
1168                              &pdata->min_efuse_value);
1169         of_property_read_u32(np, "samsung,tmu_max_efuse_value",
1170                              &pdata->max_efuse_value);
1171
1172         of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
1173         pdata->first_point_trim = (u8)value;
1174         of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
1175         pdata->second_point_trim = (u8)value;
1176         of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
1177         pdata->default_temp_offset = (u8)value;
1178
1179         of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1180         of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode);
1181
1182         of_node_put(np);
1183         return 0;
1184 }
1185
1186 static int exynos_map_dt_data(struct platform_device *pdev)
1187 {
1188         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1189         struct exynos_tmu_platform_data *pdata;
1190         struct resource res;
1191
1192         if (!data || !pdev->dev.of_node)
1193                 return -ENODEV;
1194
1195         data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
1196         if (data->id < 0)
1197                 data->id = 0;
1198
1199         data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1200         if (data->irq <= 0) {
1201                 dev_err(&pdev->dev, "failed to get IRQ\n");
1202                 return -ENODEV;
1203         }
1204
1205         if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
1206                 dev_err(&pdev->dev, "failed to get Resource 0\n");
1207                 return -ENODEV;
1208         }
1209
1210         data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1211         if (!data->base) {
1212                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1213                 return -EADDRNOTAVAIL;
1214         }
1215
1216         pdata = devm_kzalloc(&pdev->dev,
1217                              sizeof(struct exynos_tmu_platform_data),
1218                              GFP_KERNEL);
1219         if (!pdata)
1220                 return -ENOMEM;
1221
1222         exynos_of_sensor_conf(pdev->dev.of_node, pdata);
1223         data->pdata = pdata;
1224         data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
1225
1226         switch (data->soc) {
1227         case SOC_ARCH_EXYNOS4210:
1228                 data->tmu_initialize = exynos4210_tmu_initialize;
1229                 data->tmu_control = exynos4210_tmu_control;
1230                 data->tmu_read = exynos4210_tmu_read;
1231                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1232                 data->ntrip = 4;
1233                 break;
1234         case SOC_ARCH_EXYNOS3250:
1235         case SOC_ARCH_EXYNOS4412:
1236         case SOC_ARCH_EXYNOS5250:
1237         case SOC_ARCH_EXYNOS5260:
1238         case SOC_ARCH_EXYNOS5420:
1239         case SOC_ARCH_EXYNOS5420_TRIMINFO:
1240                 data->tmu_initialize = exynos4412_tmu_initialize;
1241                 data->tmu_control = exynos4210_tmu_control;
1242                 data->tmu_read = exynos4412_tmu_read;
1243                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1244                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1245                 data->ntrip = 4;
1246                 break;
1247         case SOC_ARCH_EXYNOS5433:
1248                 data->tmu_initialize = exynos5433_tmu_initialize;
1249                 data->tmu_control = exynos5433_tmu_control;
1250                 data->tmu_read = exynos4412_tmu_read;
1251                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1252                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1253                 data->ntrip = 8;
1254                 break;
1255         case SOC_ARCH_EXYNOS5440:
1256                 data->tmu_initialize = exynos5440_tmu_initialize;
1257                 data->tmu_control = exynos5440_tmu_control;
1258                 data->tmu_read = exynos5440_tmu_read;
1259                 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1260                 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1261                 data->ntrip = 4;
1262                 break;
1263         case SOC_ARCH_EXYNOS7:
1264                 data->tmu_initialize = exynos7_tmu_initialize;
1265                 data->tmu_control = exynos7_tmu_control;
1266                 data->tmu_read = exynos7_tmu_read;
1267                 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1268                 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1269                 data->ntrip = 8;
1270                 break;
1271         default:
1272                 dev_err(&pdev->dev, "Platform not supported\n");
1273                 return -EINVAL;
1274         }
1275
1276         /*
1277          * Check if the TMU shares some registers and then try to map the
1278          * memory of common registers.
1279          */
1280         if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
1281             data->soc != SOC_ARCH_EXYNOS5440)
1282                 return 0;
1283
1284         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
1285                 dev_err(&pdev->dev, "failed to get Resource 1\n");
1286                 return -ENODEV;
1287         }
1288
1289         data->base_second = devm_ioremap(&pdev->dev, res.start,
1290                                         resource_size(&res));
1291         if (!data->base_second) {
1292                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1293                 return -ENOMEM;
1294         }
1295
1296         return 0;
1297 }
1298
1299 static struct thermal_zone_of_device_ops exynos_sensor_ops = {
1300         .get_temp = exynos_get_temp,
1301         .set_emul_temp = exynos_tmu_set_emulation,
1302 };
1303
1304 static int exynos_tmu_probe(struct platform_device *pdev)
1305 {
1306         struct exynos_tmu_data *data;
1307         int ret;
1308
1309         data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1310                                         GFP_KERNEL);
1311         if (!data)
1312                 return -ENOMEM;
1313
1314         platform_set_drvdata(pdev, data);
1315         mutex_init(&data->lock);
1316
1317         /*
1318          * Try enabling the regulator if found
1319          * TODO: Add regulator as an SOC feature, so that regulator enable
1320          * is a compulsory call.
1321          */
1322         data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu");
1323         if (!IS_ERR(data->regulator)) {
1324                 ret = regulator_enable(data->regulator);
1325                 if (ret) {
1326                         dev_err(&pdev->dev, "failed to enable vtmu\n");
1327                         return ret;
1328                 }
1329         } else {
1330                 if (PTR_ERR(data->regulator) == -EPROBE_DEFER)
1331                         return -EPROBE_DEFER;
1332                 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
1333         }
1334
1335         ret = exynos_map_dt_data(pdev);
1336         if (ret)
1337                 goto err_sensor;
1338
1339         INIT_WORK(&data->irq_work, exynos_tmu_work);
1340
1341         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1342         if (IS_ERR(data->clk)) {
1343                 dev_err(&pdev->dev, "Failed to get clock\n");
1344                 ret = PTR_ERR(data->clk);
1345                 goto err_sensor;
1346         }
1347
1348         data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1349         if (IS_ERR(data->clk_sec)) {
1350                 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1351                         dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1352                         ret = PTR_ERR(data->clk_sec);
1353                         goto err_sensor;
1354                 }
1355         } else {
1356                 ret = clk_prepare(data->clk_sec);
1357                 if (ret) {
1358                         dev_err(&pdev->dev, "Failed to get clock\n");
1359                         goto err_sensor;
1360                 }
1361         }
1362
1363         ret = clk_prepare(data->clk);
1364         if (ret) {
1365                 dev_err(&pdev->dev, "Failed to get clock\n");
1366                 goto err_clk_sec;
1367         }
1368
1369         switch (data->soc) {
1370         case SOC_ARCH_EXYNOS5433:
1371         case SOC_ARCH_EXYNOS7:
1372                 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1373                 if (IS_ERR(data->sclk)) {
1374                         dev_err(&pdev->dev, "Failed to get sclk\n");
1375                         ret = PTR_ERR(data->sclk);
1376                         goto err_clk;
1377                 } else {
1378                         ret = clk_prepare_enable(data->sclk);
1379                         if (ret) {
1380                                 dev_err(&pdev->dev, "Failed to enable sclk\n");
1381                                 goto err_clk;
1382                         }
1383                 }
1384                 break;
1385         default:
1386                 break;
1387         }
1388
1389         /*
1390          * data->tzd must be registered before calling exynos_tmu_initialize(),
1391          * requesting irq and calling exynos_tmu_control().
1392          */
1393         data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
1394                                                     &exynos_sensor_ops);
1395         if (IS_ERR(data->tzd)) {
1396                 ret = PTR_ERR(data->tzd);
1397                 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret);
1398                 goto err_sclk;
1399         }
1400
1401         ret = exynos_tmu_initialize(pdev);
1402         if (ret) {
1403                 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1404                 goto err_thermal;
1405         }
1406
1407         ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1408                 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1409         if (ret) {
1410                 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1411                 goto err_thermal;
1412         }
1413
1414         exynos_tmu_control(pdev, true);
1415         return 0;
1416
1417 err_thermal:
1418         thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1419 err_sclk:
1420         clk_disable_unprepare(data->sclk);
1421 err_clk:
1422         clk_unprepare(data->clk);
1423 err_clk_sec:
1424         if (!IS_ERR(data->clk_sec))
1425                 clk_unprepare(data->clk_sec);
1426 err_sensor:
1427         if (!IS_ERR(data->regulator))
1428                 regulator_disable(data->regulator);
1429
1430         return ret;
1431 }
1432
1433 static int exynos_tmu_remove(struct platform_device *pdev)
1434 {
1435         struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1436         struct thermal_zone_device *tzd = data->tzd;
1437
1438         thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
1439         exynos_tmu_control(pdev, false);
1440
1441         clk_disable_unprepare(data->sclk);
1442         clk_unprepare(data->clk);
1443         if (!IS_ERR(data->clk_sec))
1444                 clk_unprepare(data->clk_sec);
1445
1446         if (!IS_ERR(data->regulator))
1447                 regulator_disable(data->regulator);
1448
1449         return 0;
1450 }
1451
1452 #ifdef CONFIG_PM_SLEEP
1453 static int exynos_tmu_suspend(struct device *dev)
1454 {
1455         exynos_tmu_control(to_platform_device(dev), false);
1456
1457         return 0;
1458 }
1459
1460 static int exynos_tmu_resume(struct device *dev)
1461 {
1462         struct platform_device *pdev = to_platform_device(dev);
1463
1464         exynos_tmu_initialize(pdev);
1465         exynos_tmu_control(pdev, true);
1466
1467         return 0;
1468 }
1469
1470 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1471                          exynos_tmu_suspend, exynos_tmu_resume);
1472 #define EXYNOS_TMU_PM   (&exynos_tmu_pm)
1473 #else
1474 #define EXYNOS_TMU_PM   NULL
1475 #endif
1476
1477 static struct platform_driver exynos_tmu_driver = {
1478         .driver = {
1479                 .name   = "exynos-tmu",
1480                 .pm     = EXYNOS_TMU_PM,
1481                 .of_match_table = exynos_tmu_match,
1482         },
1483         .probe = exynos_tmu_probe,
1484         .remove = exynos_tmu_remove,
1485 };
1486
1487 module_platform_driver(exynos_tmu_driver);
1488
1489 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1490 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1491 MODULE_LICENSE("GPL");
1492 MODULE_ALIAS("platform:exynos-tmu");