1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <wxt@rock-chips.com>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/thermal.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/pinctrl/consumer.h>
23 * If the temperature over a period of time High,
24 * the resulting TSHUT gave CRU module,let it reset the entire chip,
25 * or via GPIO give PMIC.
33 * The system Temperature Sensors tshut(tshut) polarity
34 * the bit 8 is tshut polarity.
35 * 0: low active, 1: high active
43 * The system has two Temperature Sensors.
44 * sensor0 is for CPU, and sensor1 is for GPU.
52 * The conversion table has the adc value and temperature.
53 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
54 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
61 #include "thermal_hwmon.h"
64 * The max sensors is two in rockchip SoCs.
65 * Two sensors: CPU and GPU sensor.
67 #define SOC_MAX_SENSORS 2
70 * struct chip_tsadc_table - hold information about chip-specific differences
71 * @id: conversion table
72 * @length: size of conversion table
73 * @data_mask: mask to apply on data inputs
74 * @mode: sort mode of this adc variant (incrementing or decrementing)
76 struct chip_tsadc_table {
77 const struct tsadc_table *id;
80 enum adc_sort_mode mode;
84 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
85 * @chn_id: array of sensor ids of chip corresponding to the channel
86 * @chn_num: the channel number of tsadc chip
87 * @tshut_temp: the hardware-controlled shutdown temperature value
88 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
89 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
90 * @initialize: SoC special initialize tsadc controller method
91 * @irq_ack: clear the interrupt
92 * @control: enable/disable method for the tsadc controller
93 * @get_temp: get the temperature
94 * @set_alarm_temp: set the high temperature interrupt
95 * @set_tshut_temp: set the hardware-controlled shutdown temperature
96 * @set_tshut_mode: set the hardware-controlled shutdown mode
97 * @table: the chip-specific conversion table
99 struct rockchip_tsadc_chip {
100 /* The sensor id of chip correspond to the ADC channel */
101 int chn_id[SOC_MAX_SENSORS];
104 /* The hardware-controlled tshut property */
106 enum tshut_mode tshut_mode;
107 enum tshut_polarity tshut_polarity;
109 /* Chip-wide methods */
110 void (*initialize)(struct regmap *grf,
111 void __iomem *reg, enum tshut_polarity p);
112 void (*irq_ack)(void __iomem *reg);
113 void (*control)(void __iomem *reg, bool on);
115 /* Per-sensor methods */
116 int (*get_temp)(const struct chip_tsadc_table *table,
117 int chn, void __iomem *reg, int *temp);
118 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
119 int chn, void __iomem *reg, int temp);
120 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
121 int chn, void __iomem *reg, int temp);
122 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
124 /* Per-table methods */
125 struct chip_tsadc_table table;
129 * struct rockchip_thermal_sensor - hold the information of thermal sensor
130 * @thermal: pointer to the platform/configuration data
131 * @tzd: pointer to a thermal zone
132 * @id: identifier of the thermal sensor
134 struct rockchip_thermal_sensor {
135 struct rockchip_thermal_data *thermal;
136 struct thermal_zone_device *tzd;
141 * struct rockchip_thermal_data - hold the private data of thermal driver
142 * @chip: pointer to the platform/configuration data
143 * @pdev: platform device of thermal
144 * @reset: the reset controller of tsadc
145 * @sensors: array of thermal sensors
146 * @clk: the controller clock is divided by the exteral 24MHz
147 * @pclk: the advanced peripherals bus clock
148 * @grf: the general register file will be used to do static set by software
149 * @regs: the base address of tsadc controller
150 * @tshut_temp: the hardware-controlled shutdown temperature value
151 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
152 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
154 struct rockchip_thermal_data {
155 const struct rockchip_tsadc_chip *chip;
156 struct platform_device *pdev;
157 struct reset_control *reset;
159 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
168 enum tshut_mode tshut_mode;
169 enum tshut_polarity tshut_polarity;
173 * TSADC Sensor Register description:
175 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
176 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
179 #define TSADCV2_USER_CON 0x00
180 #define TSADCV2_AUTO_CON 0x04
181 #define TSADCV2_INT_EN 0x08
182 #define TSADCV2_INT_PD 0x0c
183 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
184 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
185 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
186 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
187 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
188 #define TSADCV2_AUTO_PERIOD 0x68
189 #define TSADCV2_AUTO_PERIOD_HT 0x6c
191 #define TSADCV2_AUTO_EN BIT(0)
192 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
193 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
195 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
197 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
198 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
199 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
201 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
202 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
204 #define TSADCV2_DATA_MASK 0xfff
205 #define TSADCV3_DATA_MASK 0x3ff
207 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
208 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
209 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
210 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
211 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
212 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
214 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
216 #define GRF_SARADC_TESTBIT 0x0e644
217 #define GRF_TSADC_TESTBIT_L 0x0e648
218 #define GRF_TSADC_TESTBIT_H 0x0e64c
220 #define PX30_GRF_SOC_CON2 0x0408
222 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
223 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
224 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
225 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
227 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
230 * struct tsadc_table - code to temperature conversion table
231 * @code: the value of adc channel
232 * @temp: the temperature
234 * code to temperature mapping of the temperature sensor is a piece wise linear
235 * curve.Any temperature, code faling between to 2 give temperatures can be
236 * linearly interpolated.
237 * Code to Temperature mapping should be updated based on manufacturer results.
244 static const struct tsadc_table rv1108_table[] = {
280 {TSADCV2_DATA_MASK, 125000},
283 static const struct tsadc_table rk3228_code_table[] = {
319 {TSADCV2_DATA_MASK, 125000},
322 static const struct tsadc_table rk3288_code_table[] = {
323 {TSADCV2_DATA_MASK, -40000},
361 static const struct tsadc_table rk3328_code_table[] = {
396 {TSADCV2_DATA_MASK, 125000},
399 static const struct tsadc_table rk3368_code_table[] = {
435 {TSADCV3_DATA_MASK, 125000},
438 static const struct tsadc_table rk3399_code_table[] = {
474 {TSADCV3_DATA_MASK, 125000},
477 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
483 u32 error = table->data_mask;
486 high = (table->length - 1) - 1; /* ignore the last check for table */
487 mid = (high + low) / 2;
489 /* Return mask code data when the temp is over table range */
490 if (temp < table->id[low].temp || temp > table->id[high].temp)
493 while (low <= high) {
494 if (temp == table->id[mid].temp)
495 return table->id[mid].code;
496 else if (temp < table->id[mid].temp)
500 mid = (low + high) / 2;
504 * The conversion code granularity provided by the table. Let's
505 * assume that the relationship between temperature and
506 * analog value between 2 table entries is linear and interpolate
507 * to produce less granular result.
509 num = abs(table->id[mid + 1].code - table->id[mid].code);
510 num *= temp - table->id[mid].temp;
511 denom = table->id[mid + 1].temp - table->id[mid].temp;
513 switch (table->mode) {
515 return table->id[mid].code - (num / denom);
517 return table->id[mid].code + (num / denom);
519 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
524 pr_err("%s: invalid temperature, temp=%d error=%d\n",
525 __func__, temp, error);
529 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
532 unsigned int low = 1;
533 unsigned int high = table->length - 1;
534 unsigned int mid = (low + high) / 2;
538 WARN_ON(table->length < 2);
540 switch (table->mode) {
542 code &= table->data_mask;
543 if (code <= table->id[high].code)
544 return -EAGAIN; /* Incorrect reading */
546 while (low <= high) {
547 if (code >= table->id[mid].code &&
548 code < table->id[mid - 1].code)
550 else if (code < table->id[mid].code)
555 mid = (low + high) / 2;
559 code &= table->data_mask;
560 if (code < table->id[low].code)
561 return -EAGAIN; /* Incorrect reading */
563 while (low <= high) {
564 if (code <= table->id[mid].code &&
565 code > table->id[mid - 1].code)
567 else if (code > table->id[mid].code)
572 mid = (low + high) / 2;
576 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
581 * The 5C granularity provided by the table is too much. Let's
582 * assume that the relationship between sensor readings and
583 * temperature between 2 table entries is linear and interpolate
584 * to produce less granular result.
586 num = table->id[mid].temp - table->id[mid - 1].temp;
587 num *= abs(table->id[mid - 1].code - code);
588 denom = abs(table->id[mid - 1].code - table->id[mid].code);
589 *temp = table->id[mid - 1].temp + (num / denom);
595 * rk_tsadcv2_initialize - initialize TASDC Controller.
596 * @grf: the general register file will be used to do static set by software
597 * @regs: the base address of tsadc controller
598 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
600 * (1) Set TSADC_V2_AUTO_PERIOD:
601 * Configure the interleave between every two accessing of
602 * TSADC in normal operation.
604 * (2) Set TSADCV2_AUTO_PERIOD_HT:
605 * Configure the interleave between every two accessing of
606 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
608 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
609 * If the temperature is higher than COMP_INT or COMP_SHUT for
610 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
612 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
613 enum tshut_polarity tshut_polarity)
615 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
616 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
617 regs + TSADCV2_AUTO_CON);
619 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
620 regs + TSADCV2_AUTO_CON);
622 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
623 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
624 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
625 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
626 regs + TSADCV2_AUTO_PERIOD_HT);
627 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
628 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
632 * rk_tsadcv3_initialize - initialize TASDC Controller.
633 * @grf: the general register file will be used to do static set by software
634 * @regs: the base address of tsadc controller
635 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
637 * (1) The tsadc control power sequence.
639 * (2) Set TSADC_V2_AUTO_PERIOD:
640 * Configure the interleave between every two accessing of
641 * TSADC in normal operation.
643 * (2) Set TSADCV2_AUTO_PERIOD_HT:
644 * Configure the interleave between every two accessing of
645 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
647 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
648 * If the temperature is higher than COMP_INT or COMP_SHUT for
649 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
651 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
652 enum tshut_polarity tshut_polarity)
654 /* The tsadc control power sequence */
656 /* Set interleave value to workround ic time sync issue */
657 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
660 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
661 regs + TSADCV2_AUTO_PERIOD);
662 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
663 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
664 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
665 regs + TSADCV2_AUTO_PERIOD_HT);
666 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
667 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
670 /* Enable the voltage common mode feature */
671 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
672 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
674 usleep_range(15, 100); /* The spec note says at least 15 us */
675 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
676 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
677 usleep_range(90, 200); /* The spec note says at least 90 us */
679 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
680 regs + TSADCV2_AUTO_PERIOD);
681 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
682 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
683 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
684 regs + TSADCV2_AUTO_PERIOD_HT);
685 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
686 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
689 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
690 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
691 regs + TSADCV2_AUTO_CON);
693 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
694 regs + TSADCV2_AUTO_CON);
697 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
698 enum tshut_polarity tshut_polarity)
700 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
701 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
704 static void rk_tsadcv2_irq_ack(void __iomem *regs)
708 val = readl_relaxed(regs + TSADCV2_INT_PD);
709 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
712 static void rk_tsadcv3_irq_ack(void __iomem *regs)
716 val = readl_relaxed(regs + TSADCV2_INT_PD);
717 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
720 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
724 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
726 val |= TSADCV2_AUTO_EN;
728 val &= ~TSADCV2_AUTO_EN;
730 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
734 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
735 * @regs: the base address of tsadc controller
736 * @enable: boolean flag to enable the controller
738 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
739 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
740 * adc value if setting this bit to enable.
742 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
746 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
748 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
750 val &= ~TSADCV2_AUTO_EN;
752 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
755 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
756 int chn, void __iomem *regs, int *temp)
760 val = readl_relaxed(regs + TSADCV2_DATA(chn));
762 return rk_tsadcv2_code_to_temp(table, val, temp);
765 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
766 int chn, void __iomem *regs, int temp)
772 * In some cases, some sensors didn't need the trip points, the
773 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
774 * in the end, ignore this case and disable the high temperature
777 if (temp == INT_MAX) {
778 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
779 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
780 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
784 /* Make sure the value is valid */
785 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
786 if (alarm_value == table->data_mask)
789 writel_relaxed(alarm_value & table->data_mask,
790 regs + TSADCV2_COMP_INT(chn));
792 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
793 int_en |= TSADCV2_INT_SRC_EN(chn);
794 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
799 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
800 int chn, void __iomem *regs, int temp)
802 u32 tshut_value, val;
804 /* Make sure the value is valid */
805 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
806 if (tshut_value == table->data_mask)
809 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
811 /* TSHUT will be valid */
812 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
813 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
818 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
819 enum tshut_mode mode)
823 val = readl_relaxed(regs + TSADCV2_INT_EN);
824 if (mode == TSHUT_MODE_GPIO) {
825 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
826 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
828 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
829 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
832 writel_relaxed(val, regs + TSADCV2_INT_EN);
835 static const struct rockchip_tsadc_chip px30_tsadc_data = {
836 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
837 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
838 .chn_num = 2, /* 2 channels for tsadc */
840 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
843 .initialize = rk_tsadcv4_initialize,
844 .irq_ack = rk_tsadcv3_irq_ack,
845 .control = rk_tsadcv3_control,
846 .get_temp = rk_tsadcv2_get_temp,
847 .set_alarm_temp = rk_tsadcv2_alarm_temp,
848 .set_tshut_temp = rk_tsadcv2_tshut_temp,
849 .set_tshut_mode = rk_tsadcv2_tshut_mode,
852 .id = rk3328_code_table,
853 .length = ARRAY_SIZE(rk3328_code_table),
854 .data_mask = TSADCV2_DATA_MASK,
855 .mode = ADC_INCREMENT,
859 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
860 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
861 .chn_num = 1, /* one channel for tsadc */
863 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
864 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
867 .initialize = rk_tsadcv2_initialize,
868 .irq_ack = rk_tsadcv3_irq_ack,
869 .control = rk_tsadcv3_control,
870 .get_temp = rk_tsadcv2_get_temp,
871 .set_alarm_temp = rk_tsadcv2_alarm_temp,
872 .set_tshut_temp = rk_tsadcv2_tshut_temp,
873 .set_tshut_mode = rk_tsadcv2_tshut_mode,
877 .length = ARRAY_SIZE(rv1108_table),
878 .data_mask = TSADCV2_DATA_MASK,
879 .mode = ADC_INCREMENT,
883 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
884 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
885 .chn_num = 1, /* one channel for tsadc */
887 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
888 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
891 .initialize = rk_tsadcv2_initialize,
892 .irq_ack = rk_tsadcv3_irq_ack,
893 .control = rk_tsadcv3_control,
894 .get_temp = rk_tsadcv2_get_temp,
895 .set_alarm_temp = rk_tsadcv2_alarm_temp,
896 .set_tshut_temp = rk_tsadcv2_tshut_temp,
897 .set_tshut_mode = rk_tsadcv2_tshut_mode,
900 .id = rk3228_code_table,
901 .length = ARRAY_SIZE(rk3228_code_table),
902 .data_mask = TSADCV3_DATA_MASK,
903 .mode = ADC_INCREMENT,
907 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
908 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
909 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
910 .chn_num = 2, /* two channels for tsadc */
912 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
913 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
916 .initialize = rk_tsadcv2_initialize,
917 .irq_ack = rk_tsadcv2_irq_ack,
918 .control = rk_tsadcv2_control,
919 .get_temp = rk_tsadcv2_get_temp,
920 .set_alarm_temp = rk_tsadcv2_alarm_temp,
921 .set_tshut_temp = rk_tsadcv2_tshut_temp,
922 .set_tshut_mode = rk_tsadcv2_tshut_mode,
925 .id = rk3288_code_table,
926 .length = ARRAY_SIZE(rk3288_code_table),
927 .data_mask = TSADCV2_DATA_MASK,
928 .mode = ADC_DECREMENT,
932 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
933 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
934 .chn_num = 1, /* one channels for tsadc */
936 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
939 .initialize = rk_tsadcv2_initialize,
940 .irq_ack = rk_tsadcv3_irq_ack,
941 .control = rk_tsadcv3_control,
942 .get_temp = rk_tsadcv2_get_temp,
943 .set_alarm_temp = rk_tsadcv2_alarm_temp,
944 .set_tshut_temp = rk_tsadcv2_tshut_temp,
945 .set_tshut_mode = rk_tsadcv2_tshut_mode,
948 .id = rk3328_code_table,
949 .length = ARRAY_SIZE(rk3328_code_table),
950 .data_mask = TSADCV2_DATA_MASK,
951 .mode = ADC_INCREMENT,
955 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
956 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
957 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
958 .chn_num = 2, /* two channels for tsadc */
960 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
961 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
964 .initialize = rk_tsadcv3_initialize,
965 .irq_ack = rk_tsadcv3_irq_ack,
966 .control = rk_tsadcv3_control,
967 .get_temp = rk_tsadcv2_get_temp,
968 .set_alarm_temp = rk_tsadcv2_alarm_temp,
969 .set_tshut_temp = rk_tsadcv2_tshut_temp,
970 .set_tshut_mode = rk_tsadcv2_tshut_mode,
973 .id = rk3228_code_table,
974 .length = ARRAY_SIZE(rk3228_code_table),
975 .data_mask = TSADCV3_DATA_MASK,
976 .mode = ADC_INCREMENT,
980 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
981 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
982 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
983 .chn_num = 2, /* two channels for tsadc */
985 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
986 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
989 .initialize = rk_tsadcv2_initialize,
990 .irq_ack = rk_tsadcv2_irq_ack,
991 .control = rk_tsadcv2_control,
992 .get_temp = rk_tsadcv2_get_temp,
993 .set_alarm_temp = rk_tsadcv2_alarm_temp,
994 .set_tshut_temp = rk_tsadcv2_tshut_temp,
995 .set_tshut_mode = rk_tsadcv2_tshut_mode,
998 .id = rk3368_code_table,
999 .length = ARRAY_SIZE(rk3368_code_table),
1000 .data_mask = TSADCV3_DATA_MASK,
1001 .mode = ADC_INCREMENT,
1005 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1006 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1007 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1008 .chn_num = 2, /* two channels for tsadc */
1010 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1011 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1012 .tshut_temp = 95000,
1014 .initialize = rk_tsadcv3_initialize,
1015 .irq_ack = rk_tsadcv3_irq_ack,
1016 .control = rk_tsadcv3_control,
1017 .get_temp = rk_tsadcv2_get_temp,
1018 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1019 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1020 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1023 .id = rk3399_code_table,
1024 .length = ARRAY_SIZE(rk3399_code_table),
1025 .data_mask = TSADCV3_DATA_MASK,
1026 .mode = ADC_INCREMENT,
1030 static const struct of_device_id of_rockchip_thermal_match[] = {
1031 { .compatible = "rockchip,px30-tsadc",
1032 .data = (void *)&px30_tsadc_data,
1035 .compatible = "rockchip,rv1108-tsadc",
1036 .data = (void *)&rv1108_tsadc_data,
1039 .compatible = "rockchip,rk3228-tsadc",
1040 .data = (void *)&rk3228_tsadc_data,
1043 .compatible = "rockchip,rk3288-tsadc",
1044 .data = (void *)&rk3288_tsadc_data,
1047 .compatible = "rockchip,rk3328-tsadc",
1048 .data = (void *)&rk3328_tsadc_data,
1051 .compatible = "rockchip,rk3366-tsadc",
1052 .data = (void *)&rk3366_tsadc_data,
1055 .compatible = "rockchip,rk3368-tsadc",
1056 .data = (void *)&rk3368_tsadc_data,
1059 .compatible = "rockchip,rk3399-tsadc",
1060 .data = (void *)&rk3399_tsadc_data,
1064 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1067 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1069 struct thermal_zone_device *tzd = sensor->tzd;
1072 thermal_zone_device_enable(tzd);
1074 thermal_zone_device_disable(tzd);
1077 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1079 struct rockchip_thermal_data *thermal = dev;
1082 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1084 thermal->chip->irq_ack(thermal->regs);
1086 for (i = 0; i < thermal->chip->chn_num; i++)
1087 thermal_zone_device_update(thermal->sensors[i].tzd,
1088 THERMAL_EVENT_UNSPECIFIED);
1093 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1095 struct rockchip_thermal_sensor *sensor = _sensor;
1096 struct rockchip_thermal_data *thermal = sensor->thermal;
1097 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1099 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1100 __func__, sensor->id, low, high);
1102 return tsadc->set_alarm_temp(&tsadc->table,
1103 sensor->id, thermal->regs, high);
1106 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1108 struct rockchip_thermal_sensor *sensor = _sensor;
1109 struct rockchip_thermal_data *thermal = sensor->thermal;
1110 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1113 retval = tsadc->get_temp(&tsadc->table,
1114 sensor->id, thermal->regs, out_temp);
1115 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1116 sensor->id, *out_temp, retval);
1121 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1122 .get_temp = rockchip_thermal_get_temp,
1123 .set_trips = rockchip_thermal_set_trips,
1126 static int rockchip_configure_from_dt(struct device *dev,
1127 struct device_node *np,
1128 struct rockchip_thermal_data *thermal)
1130 u32 shut_temp, tshut_mode, tshut_polarity;
1132 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1134 "Missing tshut temp property, using default %d\n",
1135 thermal->chip->tshut_temp);
1136 thermal->tshut_temp = thermal->chip->tshut_temp;
1138 if (shut_temp > INT_MAX) {
1139 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1143 thermal->tshut_temp = shut_temp;
1146 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1148 "Missing tshut mode property, using default (%s)\n",
1149 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1151 thermal->tshut_mode = thermal->chip->tshut_mode;
1153 thermal->tshut_mode = tshut_mode;
1156 if (thermal->tshut_mode > 1) {
1157 dev_err(dev, "Invalid tshut mode specified: %d\n",
1158 thermal->tshut_mode);
1162 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1165 "Missing tshut-polarity property, using default (%s)\n",
1166 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1168 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1170 thermal->tshut_polarity = tshut_polarity;
1173 if (thermal->tshut_polarity > 1) {
1174 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1175 thermal->tshut_polarity);
1179 /* The tsadc wont to handle the error in here since some SoCs didn't
1180 * need this property.
1182 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1183 if (IS_ERR(thermal->grf))
1184 dev_warn(dev, "Missing rockchip,grf property\n");
1190 rockchip_thermal_register_sensor(struct platform_device *pdev,
1191 struct rockchip_thermal_data *thermal,
1192 struct rockchip_thermal_sensor *sensor,
1195 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1198 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1200 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1201 thermal->tshut_temp);
1203 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1204 __func__, thermal->tshut_temp, error);
1206 sensor->thermal = thermal;
1208 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1209 sensor, &rockchip_of_thermal_ops);
1210 if (IS_ERR(sensor->tzd)) {
1211 error = PTR_ERR(sensor->tzd);
1212 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1221 * Reset TSADC Controller, reset all tsadc registers.
1222 * @reset: the reset controller of tsadc
1224 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1226 reset_control_assert(reset);
1227 usleep_range(10, 20);
1228 reset_control_deassert(reset);
1231 static int rockchip_thermal_probe(struct platform_device *pdev)
1233 struct device_node *np = pdev->dev.of_node;
1234 struct rockchip_thermal_data *thermal;
1235 const struct of_device_id *match;
1236 struct resource *res;
1241 match = of_match_node(of_rockchip_thermal_match, np);
1245 irq = platform_get_irq(pdev, 0);
1249 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1254 thermal->pdev = pdev;
1256 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1261 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1262 if (IS_ERR(thermal->regs))
1263 return PTR_ERR(thermal->regs);
1265 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1266 if (IS_ERR(thermal->reset)) {
1267 error = PTR_ERR(thermal->reset);
1268 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1272 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1273 if (IS_ERR(thermal->clk)) {
1274 error = PTR_ERR(thermal->clk);
1275 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1279 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1280 if (IS_ERR(thermal->pclk)) {
1281 error = PTR_ERR(thermal->pclk);
1282 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1287 error = clk_prepare_enable(thermal->clk);
1289 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1294 error = clk_prepare_enable(thermal->pclk);
1296 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1297 goto err_disable_clk;
1300 rockchip_thermal_reset_controller(thermal->reset);
1302 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1304 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1306 goto err_disable_pclk;
1309 thermal->chip->initialize(thermal->grf, thermal->regs,
1310 thermal->tshut_polarity);
1312 for (i = 0; i < thermal->chip->chn_num; i++) {
1313 error = rockchip_thermal_register_sensor(pdev, thermal,
1314 &thermal->sensors[i],
1315 thermal->chip->chn_id[i]);
1318 "failed to register sensor[%d] : error = %d\n",
1320 goto err_disable_pclk;
1324 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1325 &rockchip_thermal_alarm_irq_thread,
1327 "rockchip_thermal", thermal);
1330 "failed to request tsadc irq: %d\n", error);
1331 goto err_disable_pclk;
1334 thermal->chip->control(thermal->regs, true);
1336 for (i = 0; i < thermal->chip->chn_num; i++) {
1337 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1338 thermal->sensors[i].tzd->tzp->no_hwmon = false;
1339 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1341 dev_warn(&pdev->dev,
1342 "failed to register sensor %d with hwmon: %d\n",
1346 platform_set_drvdata(pdev, thermal);
1351 clk_disable_unprepare(thermal->pclk);
1353 clk_disable_unprepare(thermal->clk);
1358 static int rockchip_thermal_remove(struct platform_device *pdev)
1360 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1363 for (i = 0; i < thermal->chip->chn_num; i++) {
1364 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1366 thermal_remove_hwmon_sysfs(sensor->tzd);
1367 rockchip_thermal_toggle_sensor(sensor, false);
1370 thermal->chip->control(thermal->regs, false);
1372 clk_disable_unprepare(thermal->pclk);
1373 clk_disable_unprepare(thermal->clk);
1378 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1380 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1383 for (i = 0; i < thermal->chip->chn_num; i++)
1384 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1386 thermal->chip->control(thermal->regs, false);
1388 clk_disable(thermal->pclk);
1389 clk_disable(thermal->clk);
1391 pinctrl_pm_select_sleep_state(dev);
1396 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1398 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1402 error = clk_enable(thermal->clk);
1406 error = clk_enable(thermal->pclk);
1408 clk_disable(thermal->clk);
1412 rockchip_thermal_reset_controller(thermal->reset);
1414 thermal->chip->initialize(thermal->grf, thermal->regs,
1415 thermal->tshut_polarity);
1417 for (i = 0; i < thermal->chip->chn_num; i++) {
1418 int id = thermal->sensors[i].id;
1420 thermal->chip->set_tshut_mode(id, thermal->regs,
1421 thermal->tshut_mode);
1423 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1425 thermal->tshut_temp);
1427 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1428 __func__, thermal->tshut_temp, error);
1431 thermal->chip->control(thermal->regs, true);
1433 for (i = 0; i < thermal->chip->chn_num; i++)
1434 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1436 pinctrl_pm_select_default_state(dev);
1441 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1442 rockchip_thermal_suspend, rockchip_thermal_resume);
1444 static struct platform_driver rockchip_thermal_driver = {
1446 .name = "rockchip-thermal",
1447 .pm = &rockchip_thermal_pm_ops,
1448 .of_match_table = of_rockchip_thermal_match,
1450 .probe = rockchip_thermal_probe,
1451 .remove = rockchip_thermal_remove,
1454 module_platform_driver(rockchip_thermal_driver);
1456 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1457 MODULE_AUTHOR("Rockchip, Inc.");
1458 MODULE_LICENSE("GPL v2");
1459 MODULE_ALIAS("platform:rockchip-thermal");