drivers/staging/wilc1000/wilc_spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
   4  * All rights reserved.
   5  */
   6
   7 #include <linux/spi/spi.h>
   8
   9 #include "wilc_wfi_netdevice.h"
  10
  11 struct wilc_spi {
  12         int crc_off;
  13         int nint;
  14         int has_thrpt_enh;
  15 };
  16
  17 static struct wilc_spi g_spi;
  18 static const struct wilc_hif_func wilc_hif_spi;
  19
  20 /********************************************
  21  *
  22  *      Crc7
  23  *
  24  ********************************************/
  25
  26 static const u8 crc7_syndrome_table[256] = {
  27         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  28         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  29         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  30         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  31         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  32         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  33         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  34         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  35         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  36         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  37         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  38         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  39         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  40         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  41         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  42         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  43         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  44         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  45         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  46         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  47         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  48         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  49         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  50         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  51         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  52         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  53         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  54         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  55         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  56         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  57         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  58         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  59 };
  60
  61 static u8 crc7_byte(u8 crc, u8 data)
  62 {
  63         return crc7_syndrome_table[(crc << 1) ^ data];
  64 }
  65
  66 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  67 {
  68         while (len--)
  69                 crc = crc7_byte(crc, *buffer++);
  70         return crc;
  71 }
  72
  73 /********************************************
  74  *
  75  *      Spi protocol Function
  76  *
  77  ********************************************/
  78
  79 #define CMD_DMA_WRITE                           0xc1
  80 #define CMD_DMA_READ                            0xc2
  81 #define CMD_INTERNAL_WRITE                      0xc3
  82 #define CMD_INTERNAL_READ                       0xc4
  83 #define CMD_TERMINATE                           0xc5
  84 #define CMD_REPEAT                              0xc6
  85 #define CMD_DMA_EXT_WRITE                       0xc7
  86 #define CMD_DMA_EXT_READ                        0xc8
  87 #define CMD_SINGLE_WRITE                        0xc9
  88 #define CMD_SINGLE_READ                         0xca
  89 #define CMD_RESET                               0xcf
  90
  91 #define N_OK                                    1
  92 #define N_FAIL                                  0
  93 #define N_RESET                                 -1
  94 #define N_RETRY                                 -2
  95
  96 #define DATA_PKT_SZ_256                         256
  97 #define DATA_PKT_SZ_512                         512
  98 #define DATA_PKT_SZ_1K                          1024
  99 #define DATA_PKT_SZ_4K                          (4 * 1024)
 100 #define DATA_PKT_SZ_8K                          (8 * 1024)
 101 #define DATA_PKT_SZ                             DATA_PKT_SZ_8K
 102
 103 #define USE_SPI_DMA                             0
 104
 105 static int wilc_bus_probe(struct spi_device *spi)
 106 {
 107         int ret;
 108         struct wilc *wilc;
 109         struct gpio_desc *gpio;
 110
 111         gpio = gpiod_get(&spi->dev, "irq", GPIOD_IN);
 112         if (IS_ERR(gpio)) {
 113                 /* get the GPIO descriptor from hardcode GPIO number */
 114                 gpio = gpio_to_desc(GPIO_NUM);
 115                 if (!gpio)
 116                         dev_err(&spi->dev, "failed to get the irq gpio\n");
 117         }
 118
 119         ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, &wilc_hif_spi);
 120         if (ret)
 121                 return ret;
 122
 123         spi_set_drvdata(spi, wilc);
 124         wilc->dev = &spi->dev;
 125         wilc->gpio_irq = gpio;
 126
 127         return 0;
 128 }
 129
 130 static int wilc_bus_remove(struct spi_device *spi)
 131 {
 132         struct wilc *wilc = spi_get_drvdata(spi);
 133
 134         /* free the GPIO in module remove */
 135         if (wilc->gpio_irq)
 136                 gpiod_put(wilc->gpio_irq);
 137         wilc_netdev_cleanup(wilc);
 138         return 0;
 139 }
 140
 141 static const struct of_device_id wilc_of_match[] = {
 142         { .compatible = "microchip,wilc1000-spi", },
 143         { /* sentinel */ }
 144 };
 145 MODULE_DEVICE_TABLE(of, wilc_of_match);
 146
 147 static struct spi_driver wilc_spi_driver = {
 148         .driver = {
 149                 .name = MODALIAS,
 150                 .of_match_table = wilc_of_match,
 151         },
 152         .probe =  wilc_bus_probe,
 153         .remove = wilc_bus_remove,
 154 };
 155 module_spi_driver(wilc_spi_driver);
 156 MODULE_LICENSE("GPL");
 157
 158 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 159 {
 160         struct spi_device *spi = to_spi_device(wilc->dev);
 161         int ret;
 162         struct spi_message msg;
 163
 164         if (len > 0 && b) {
 165                 struct spi_transfer tr = {
 166                         .tx_buf = b,
 167                         .len = len,
 168                         .delay_usecs = 0,
 169                 };
 170                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 171
 172                 if (!r_buffer)
 173                         return -ENOMEM;
 174
 175                 tr.rx_buf = r_buffer;
 176                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 177
 178                 memset(&msg, 0, sizeof(msg));
 179                 spi_message_init(&msg);
 180                 msg.spi = spi;
 181                 msg.is_dma_mapped = USE_SPI_DMA;
 182                 spi_message_add_tail(&tr, &msg);
 183
 184                 ret = spi_sync(spi, &msg);
 185                 if (ret < 0)
 186                         dev_err(&spi->dev, "SPI transaction failed\n");
 187
 188                 kfree(r_buffer);
 189         } else {
 190                 dev_err(&spi->dev,
 191                         "can't write data with the following length: %d\n",
 192                         len);
 193                 ret = -EINVAL;
 194         }
 195
 196         return ret;
 197 }
 198
 199 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 200 {
 201         struct spi_device *spi = to_spi_device(wilc->dev);
 202         int ret;
 203
 204         if (rlen > 0) {
 205                 struct spi_message msg;
 206                 struct spi_transfer tr = {
 207                         .rx_buf = rb,
 208                         .len = rlen,
 209                         .delay_usecs = 0,
 210
 211                 };
 212                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 213
 214                 if (!t_buffer)
 215                         return -ENOMEM;
 216
 217                 tr.tx_buf = t_buffer;
 218
 219                 memset(&msg, 0, sizeof(msg));
 220                 spi_message_init(&msg);
 221                 msg.spi = spi;
 222                 msg.is_dma_mapped = USE_SPI_DMA;
 223                 spi_message_add_tail(&tr, &msg);
 224
 225                 ret = spi_sync(spi, &msg);
 226                 if (ret < 0)
 227                         dev_err(&spi->dev, "SPI transaction failed\n");
 228                 kfree(t_buffer);
 229         } else {
 230                 dev_err(&spi->dev,
 231                         "can't read data with the following length: %u\n",
 232                         rlen);
 233                 ret = -EINVAL;
 234         }
 235
 236         return ret;
 237 }
 238
 239 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 240 {
 241         struct spi_device *spi = to_spi_device(wilc->dev);
 242         int ret;
 243
 244         if (rlen > 0) {
 245                 struct spi_message msg;
 246                 struct spi_transfer tr = {
 247                         .rx_buf = rb,
 248                         .tx_buf = wb,
 249                         .len = rlen,
 250                         .bits_per_word = 8,
 251                         .delay_usecs = 0,
 252
 253                 };
 254
 255                 memset(&msg, 0, sizeof(msg));
 256                 spi_message_init(&msg);
 257                 msg.spi = spi;
 258                 msg.is_dma_mapped = USE_SPI_DMA;
 259
 260                 spi_message_add_tail(&tr, &msg);
 261                 ret = spi_sync(spi, &msg);
 262                 if (ret < 0)
 263                         dev_err(&spi->dev, "SPI transaction failed\n");
 264         } else {
 265                 dev_err(&spi->dev,
 266                         "can't read data with the following length: %u\n",
 267                         rlen);
 268                 ret = -EINVAL;
 269         }
 270
 271         return ret;
 272 }
 273
 274 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 275                             u8 clockless)
 276 {
 277         struct spi_device *spi = to_spi_device(wilc->dev);
 278         u8 wb[32], rb[32];
 279         u8 wix, rix;
 280         u32 len2;
 281         u8 rsp;
 282         int len = 0;
 283         int result = N_OK;
 284         int retry;
 285         u8 crc[2];
 286
 287         wb[0] = cmd;
 288         switch (cmd) {
 289         case CMD_SINGLE_READ: /* single word (4 bytes) read */
 290                 wb[1] = (u8)(adr >> 16);
 291                 wb[2] = (u8)(adr >> 8);
 292                 wb[3] = (u8)adr;
 293                 len = 5;
 294                 break;
 295
 296         case CMD_INTERNAL_READ: /* internal register read */
 297                 wb[1] = (u8)(adr >> 8);
 298                 if (clockless == 1)
 299                         wb[1] |= BIT(7);
 300                 wb[2] = (u8)adr;
 301                 wb[3] = 0x00;
 302                 len = 5;
 303                 break;
 304
 305         case CMD_TERMINATE:
 306                 wb[1] = 0x00;
 307                 wb[2] = 0x00;
 308                 wb[3] = 0x00;
 309                 len = 5;
 310                 break;
 311
 312         case CMD_REPEAT:
 313                 wb[1] = 0x00;
 314                 wb[2] = 0x00;
 315                 wb[3] = 0x00;
 316                 len = 5;
 317                 break;
 318
 319         case CMD_RESET:
 320                 wb[1] = 0xff;
 321                 wb[2] = 0xff;
 322                 wb[3] = 0xff;
 323                 len = 5;
 324                 break;
 325
 326         case CMD_DMA_WRITE: /* dma write */
 327         case CMD_DMA_READ:  /* dma read */
 328                 wb[1] = (u8)(adr >> 16);
 329                 wb[2] = (u8)(adr >> 8);
 330                 wb[3] = (u8)adr;
 331                 wb[4] = (u8)(sz >> 8);
 332                 wb[5] = (u8)(sz);
 333                 len = 7;
 334                 break;
 335
 336         case CMD_DMA_EXT_WRITE: /* dma extended write */
 337         case CMD_DMA_EXT_READ:  /* dma extended read */
 338                 wb[1] = (u8)(adr >> 16);
 339                 wb[2] = (u8)(adr >> 8);
 340                 wb[3] = (u8)adr;
 341                 wb[4] = (u8)(sz >> 16);
 342                 wb[5] = (u8)(sz >> 8);
 343                 wb[6] = (u8)(sz);
 344                 len = 8;
 345                 break;
 346
 347         case CMD_INTERNAL_WRITE: /* internal register write */
 348                 wb[1] = (u8)(adr >> 8);
 349                 if (clockless == 1)
 350                         wb[1] |= BIT(7);
 351                 wb[2] = (u8)(adr);
 352                 wb[3] = b[3];
 353                 wb[4] = b[2];
 354                 wb[5] = b[1];
 355                 wb[6] = b[0];
 356                 len = 8;
 357                 break;
 358
 359         case CMD_SINGLE_WRITE: /* single word write */
 360                 wb[1] = (u8)(adr >> 16);
 361                 wb[2] = (u8)(adr >> 8);
 362                 wb[3] = (u8)(adr);
 363                 wb[4] = b[3];
 364                 wb[5] = b[2];
 365                 wb[6] = b[1];
 366                 wb[7] = b[0];
 367                 len = 9;
 368                 break;
 369
 370         default:
 371                 result = N_FAIL;
 372                 break;
 373         }
 374
 375         if (result != N_OK)
 376                 return result;
 377
 378         if (!g_spi.crc_off)
 379                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 380         else
 381                 len -= 1;
 382
 383 #define NUM_SKIP_BYTES (1)
 384 #define NUM_RSP_BYTES (2)
 385 #define NUM_DATA_HDR_BYTES (1)
 386 #define NUM_DATA_BYTES (4)
 387 #define NUM_CRC_BYTES (2)
 388 #define NUM_DUMMY_BYTES (3)
 389         if (cmd == CMD_RESET ||
 390             cmd == CMD_TERMINATE ||
 391             cmd == CMD_REPEAT) {
 392                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 393         } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 394                 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 395                         + NUM_DUMMY_BYTES;
 396                 if (!g_spi.crc_off)
 397                         len2 = len + tmp + NUM_CRC_BYTES;
 398                 else
 399                         len2 = len + tmp;
 400         } else {
 401                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 402         }
 403 #undef NUM_DUMMY_BYTES
 404
 405         if (len2 > ARRAY_SIZE(wb)) {
 406                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 407                         len2, ARRAY_SIZE(wb));
 408                 return N_FAIL;
 409         }
 410         /* zero spi write buffers. */
 411         for (wix = len; wix < len2; wix++)
 412                 wb[wix] = 0;
 413         rix = len;
 414
 415         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 416                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 417                 return N_FAIL;
 418         }
 419
 420         /*
 421          * Command/Control response
 422          */
 423         if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
 424                 rix++; /* skip 1 byte */
 425
 426         rsp = rb[rix++];
 427
 428         if (rsp != cmd) {
 429                 dev_err(&spi->dev,
 430                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 431                         cmd, rsp);
 432                 return N_FAIL;
 433         }
 434
 435         /*
 436          * State response
 437          */
 438         rsp = rb[rix++];
 439         if (rsp != 0x00) {
 440                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 441                         rsp);
 442                 return N_FAIL;
 443         }
 444
 445         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
 446             cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
 447                 /*
 448                  * Data Respnose header
 449                  */
 450                 retry = 100;
 451                 do {
 452                         /*
 453                          * ensure there is room in buffer later
 454                          * to read data and crc
 455                          */
 456                         if (rix < len2) {
 457                                 rsp = rb[rix++];
 458                         } else {
 459                                 retry = 0;
 460                                 break;
 461                         }
 462                         if (((rsp >> 4) & 0xf) == 0xf)
 463                                 break;
 464                 } while (retry--);
 465
 466                 if (retry <= 0) {
 467                         dev_err(&spi->dev,
 468                                 "Error, data read response (%02x)\n", rsp);
 469                         return N_RESET;
 470                 }
 471         }
 472
 473         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 474                 /*
 475                  * Read bytes
 476                  */
 477                 if ((rix + 3) < len2) {
 478                         b[0] = rb[rix++];
 479                         b[1] = rb[rix++];
 480                         b[2] = rb[rix++];
 481                         b[3] = rb[rix++];
 482                 } else {
 483                         dev_err(&spi->dev,
 484                                 "buffer overrun when reading data.\n");
 485                         return N_FAIL;
 486                 }
 487
 488                 if (!g_spi.crc_off) {
 489                         /*
 490                          * Read Crc
 491                          */
 492                         if ((rix + 1) < len2) {
 493                                 crc[0] = rb[rix++];
 494                                 crc[1] = rb[rix++];
 495                         } else {
 496                                 dev_err(&spi->dev,
 497                                         "buffer overrun when reading crc.\n");
 498                                 return N_FAIL;
 499                         }
 500                 }
 501         } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 502                 int ix;
 503
 504                 /* some data may be read in response to dummy bytes. */
 505                 for (ix = 0; (rix < len2) && (ix < sz); )
 506                         b[ix++] = rb[rix++];
 507
 508                 sz -= ix;
 509
 510                 if (sz > 0) {
 511                         int nbytes;
 512
 513                         if (sz <= (DATA_PKT_SZ - ix))
 514                                 nbytes = sz;
 515                         else
 516                                 nbytes = DATA_PKT_SZ - ix;
 517
 518                         /*
 519                          * Read bytes
 520                          */
 521                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 522                                 dev_err(&spi->dev,
 523                                         "Failed block read, bus err\n");
 524                                 return N_FAIL;
 525                         }
 526
 527                         /*
 528                          * Read Crc
 529                          */
 530                         if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
 531                                 dev_err(&spi->dev,
 532                                         "Failed block crc read, bus err\n");
 533                                 return N_FAIL;
 534                         }
 535
 536                         ix += nbytes;
 537                         sz -= nbytes;
 538                 }
 539
 540                 /*
 541                  * if any data in left unread,
 542                  * then read the rest using normal DMA code.
 543                  */
 544                 while (sz > 0) {
 545                         int nbytes;
 546
 547                         if (sz <= DATA_PKT_SZ)
 548                                 nbytes = sz;
 549                         else
 550                                 nbytes = DATA_PKT_SZ;
 551
 552                         /*
 553                          * read data response only on the next DMA cycles not
 554                          * the first DMA since data response header is already
 555                          * handled above for the first DMA.
 556                          */
 557                         /*
 558                          * Data Respnose header
 559                          */
 560                         retry = 10;
 561                         do {
 562                                 if (wilc_spi_rx(wilc, &rsp, 1)) {
 563                                         dev_err(&spi->dev,
 564                                                 "Failed resp read, bus err\n");
 565                                         result = N_FAIL;
 566                                         break;
 567                                 }
 568                                 if (((rsp >> 4) & 0xf) == 0xf)
 569                                         break;
 570                         } while (retry--);
 571
 572                         if (result == N_FAIL)
 573                                 break;
 574
 575                         /*
 576                          * Read bytes
 577                          */
 578                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 579                                 dev_err(&spi->dev,
 580                                         "Failed block read, bus err\n");
 581                                 result = N_FAIL;
 582                                 break;
 583                         }
 584
 585                         /*
 586                          * Read Crc
 587                          */
 588                         if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
 589                                 dev_err(&spi->dev,
 590                                         "Failed block crc read, bus err\n");
 591                                 result = N_FAIL;
 592                                 break;
 593                         }
 594
 595                         ix += nbytes;
 596                         sz -= nbytes;
 597                 }
 598         }
 599         return result;
 600 }
 601
 602 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 603 {
 604         struct spi_device *spi = to_spi_device(wilc->dev);
 605         int ix, nbytes;
 606         int result = 1;
 607         u8 cmd, order, crc[2] = {0};
 608
 609         /*
 610          * Data
 611          */
 612         ix = 0;
 613         do {
 614                 if (sz <= DATA_PKT_SZ) {
 615                         nbytes = sz;
 616                         order = 0x3;
 617                 } else {
 618                         nbytes = DATA_PKT_SZ;
 619                         if (ix == 0)
 620                                 order = 0x1;
 621                         else
 622                                 order = 0x02;
 623                 }
 624
 625                 /*
 626                  * Write command
 627                  */
 628                 cmd = 0xf0;
 629                 cmd |= order;
 630
 631                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 632                         dev_err(&spi->dev,
 633                                 "Failed data block cmd write, bus error...\n");
 634                         result = N_FAIL;
 635                         break;
 636                 }
 637
 638                 /*
 639                  * Write data
 640                  */
 641                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 642                         dev_err(&spi->dev,
 643                                 "Failed data block write, bus error...\n");
 644                         result = N_FAIL;
 645                         break;
 646                 }
 647
 648                 /*
 649                  * Write Crc
 650                  */
 651                 if (!g_spi.crc_off) {
 652                         if (wilc_spi_tx(wilc, crc, 2)) {
 653                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 654                                 result = N_FAIL;
 655                                 break;
 656                         }
 657                 }
 658
 659                 /*
 660                  * No need to wait for response
 661                  */
 662                 ix += nbytes;
 663                 sz -= nbytes;
 664         } while (sz);
 665
 666         return result;
 667 }
 668
 669 /********************************************
 670  *
 671  *      Spi Internal Read/Write Function
 672  *
 673  ********************************************/
 674
 675 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 676 {
 677         struct spi_device *spi = to_spi_device(wilc->dev);
 678         int result;
 679
 680         cpu_to_le32s(&dat);
 681         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 682                                   0);
 683         if (result != N_OK)
 684                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 685
 686         return result;
 687 }
 688
 689 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 690 {
 691         struct spi_device *spi = to_spi_device(wilc->dev);
 692         int result;
 693
 694         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 695                                   0);
 696         if (result != N_OK) {
 697                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 698                 return 0;
 699         }
 700
 701         le32_to_cpus(data);
 702
 703         return 1;
 704 }
 705
 706 /********************************************
 707  *
 708  *      Spi interfaces
 709  *
 710  ********************************************/
 711
 712 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 713 {
 714         struct spi_device *spi = to_spi_device(wilc->dev);
 715         int result = N_OK;
 716         u8 cmd = CMD_SINGLE_WRITE;
 717         u8 clockless = 0;
 718
 719         cpu_to_le32s(&data);
 720         if (addr < 0x30) {
 721                 /* Clockless register */
 722                 cmd = CMD_INTERNAL_WRITE;
 723                 clockless = 1;
 724         }
 725
 726         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 727         if (result != N_OK)
 728                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 729
 730         return result;
 731 }
 732
 733 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 734 {
 735         struct spi_device *spi = to_spi_device(wilc->dev);
 736         int result;
 737
 738         /*
 739          * has to be greated than 4
 740          */
 741         if (size <= 4)
 742                 return 0;
 743
 744         result = spi_cmd_complete(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size, 0);
 745         if (result != N_OK) {
 746                 dev_err(&spi->dev,
 747                         "Failed cmd, write block (%08x)...\n", addr);
 748                 return 0;
 749         }
 750
 751         /*
 752          * Data
 753          */
 754         result = spi_data_write(wilc, buf, size);
 755         if (result != N_OK)
 756                 dev_err(&spi->dev, "Failed block data write...\n");
 757
 758         return 1;
 759 }
 760
 761 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 762 {
 763         struct spi_device *spi = to_spi_device(wilc->dev);
 764         int result = N_OK;
 765         u8 cmd = CMD_SINGLE_READ;
 766         u8 clockless = 0;
 767
 768         if (addr < 0x30) {
 769                 /* Clockless register */
 770                 cmd = CMD_INTERNAL_READ;
 771                 clockless = 1;
 772         }
 773
 774         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 775         if (result != N_OK) {
 776                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 777                 return 0;
 778         }
 779
 780         le32_to_cpus(data);
 781
 782         return 1;
 783 }
 784
 785 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 786 {
 787         struct spi_device *spi = to_spi_device(wilc->dev);
 788         int result;
 789
 790         if (size <= 4)
 791                 return 0;
 792
 793         result = spi_cmd_complete(wilc, CMD_DMA_EXT_READ, addr, buf, size, 0);
 794         if (result != N_OK) {
 795                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 796                 return 0;
 797         }
 798
 799         return 1;
 800 }
 801
 802 /********************************************
 803  *
 804  *      Bus interfaces
 805  *
 806  ********************************************/
 807
 808 static int _wilc_spi_deinit(struct wilc *wilc)
 809 {
 810         /*
 811          * TODO:
 812          */
 813         return 1;
 814 }
 815
 816 static int wilc_spi_init(struct wilc *wilc, bool resume)
 817 {
 818         struct spi_device *spi = to_spi_device(wilc->dev);
 819         u32 reg;
 820         u32 chipid;
 821         static int isinit;
 822
 823         if (isinit) {
 824                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 825                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 826                         return 0;
 827                 }
 828                 return 1;
 829         }
 830
 831         memset(&g_spi, 0, sizeof(struct wilc_spi));
 832
 833         /*
 834          * configure protocol
 835          */
 836         g_spi.crc_off = 0;
 837
 838         /*
 839          * TODO: We can remove the CRC trials if there is a definite
 840          * way to reset
 841          */
 842         /* the SPI to it's initial value. */
 843         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 844                 /*
 845                  * Read failed. Try with CRC off. This might happen when module
 846                  * is removed but chip isn't reset
 847                  */
 848                 g_spi.crc_off = 1;
 849                 dev_err(&spi->dev,
 850                         "Failed read with CRC on, retrying with CRC off\n");
 851                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 852                         /*
 853                          * Read failed with both CRC on and off,
 854                          * something went bad
 855                          */
 856                         dev_err(&spi->dev, "Failed internal read protocol\n");
 857                         return 0;
 858                 }
 859         }
 860         if (g_spi.crc_off == 0) {
 861                 reg &= ~0xc; /* disable crc checking */
 862                 reg &= ~0x70;
 863                 reg |= (0x5 << 4);
 864                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 865                         dev_err(&spi->dev,
 866                                 "[wilc spi %d]: Failed internal write reg\n",
 867                                 __LINE__);
 868                         return 0;
 869                 }
 870                 g_spi.crc_off = 1;
 871         }
 872
 873         /*
 874          * make sure can read back chip id correctly
 875          */
 876         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 877                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 878                 return 0;
 879         }
 880
 881         g_spi.has_thrpt_enh = 1;
 882
 883         isinit = 1;
 884
 885         return 1;
 886 }
 887
 888 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 889 {
 890         struct spi_device *spi = to_spi_device(wilc->dev);
 891         int ret;
 892
 893         if (g_spi.has_thrpt_enh) {
 894                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 895                                         size);
 896                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 897         } else {
 898                 u32 tmp;
 899                 u32 byte_cnt;
 900
 901                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 902                                         &byte_cnt);
 903                 if (!ret) {
 904                         dev_err(&spi->dev,
 905                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 906                         return ret;
 907                 }
 908                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 909                 *size = tmp;
 910         }
 911
 912         return ret;
 913 }
 914
 915 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 916 {
 917         struct spi_device *spi = to_spi_device(wilc->dev);
 918         int ret;
 919         u32 tmp;
 920         u32 byte_cnt;
 921         int happened, j;
 922         u32 unknown_mask;
 923         u32 irq_flags;
 924         int k = IRG_FLAGS_OFFSET + 5;
 925
 926         if (g_spi.has_thrpt_enh) {
 927                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 928                                         int_status);
 929                 return ret;
 930         }
 931         ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
 932         if (!ret) {
 933                 dev_err(&spi->dev,
 934                         "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 935                 return ret;
 936         }
 937         tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 938
 939         j = 0;
 940         do {
 941                 happened = 0;
 942
 943                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 944                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 945
 946                 if (g_spi.nint > 5) {
 947                         wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
 948                         tmp |= (((irq_flags >> 0) & 0x7) << k);
 949                 }
 950
 951                 unknown_mask = ~((1ul << g_spi.nint) - 1);
 952
 953                 if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
 954                         dev_err(&spi->dev,
 955                                 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
 956                                 j, tmp, unknown_mask);
 957                                 happened = 1;
 958                 }
 959
 960                 j++;
 961         } while (happened);
 962
 963         *int_status = tmp;
 964
 965         return ret;
 966 }
 967
 968 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
 969 {
 970         struct spi_device *spi = to_spi_device(wilc->dev);
 971         int ret;
 972         u32 flags;
 973         u32 tbl_ctl;
 974
 975         if (g_spi.has_thrpt_enh) {
 976                 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
 977                                          val);
 978                 return ret;
 979         }
 980
 981         flags = val & (BIT(MAX_NUM_INT) - 1);
 982         if (flags) {
 983                 int i;
 984
 985                 ret = 1;
 986                 for (i = 0; i < g_spi.nint; i++) {
 987                         /*
 988                          * No matter what you write 1 or 0,
 989                          * it will clear interrupt.
 990                          */
 991                         if (flags & 1)
 992                                 ret = wilc_spi_write_reg(wilc,
 993                                                          0x10c8 + i * 4, 1);
 994                         if (!ret)
 995                                 break;
 996                         flags >>= 1;
 997                 }
 998                 if (!ret) {
 999                         dev_err(&spi->dev,
1000                                 "Failed wilc_spi_write_reg, set reg %x ...\n",
1001                                 0x10c8 + i * 4);
1002                         return ret;
1003                 }
1004                 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1005                         if (flags & 1)
1006                                 dev_err(&spi->dev,
1007                                         "Unexpected interrupt cleared %d...\n",
1008                                         i);
1009                         flags >>= 1;
1010                 }
1011         }
1012
1013         tbl_ctl = 0;
1014         /* select VMM table 0 */
1015         if (val & SEL_VMM_TBL0)
1016                 tbl_ctl |= BIT(0);
1017         /* select VMM table 1 */
1018         if (val & SEL_VMM_TBL1)
1019                 tbl_ctl |= BIT(1);
1020
1021         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1022         if (!ret) {
1023                 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1024                 return ret;
1025         }
1026
1027         if (val & EN_VMM) {
1028                 /*
1029                  * enable vmm transfer.
1030                  */
1031                 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1032                 if (!ret) {
1033                         dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1034                         return ret;
1035                 }
1036         }
1037
1038         return ret;
1039 }
1040
1041 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1042 {
1043         struct spi_device *spi = to_spi_device(wilc->dev);
1044         u32 reg;
1045         int ret, i;
1046
1047         if (nint > MAX_NUM_INT) {
1048                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1049                 return 0;
1050         }
1051
1052         g_spi.nint = nint;
1053
1054         /*
1055          * interrupt pin mux select
1056          */
1057         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1058         if (!ret) {
1059                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1060                         WILC_PIN_MUX_0);
1061                 return 0;
1062         }
1063         reg |= BIT(8);
1064         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1065         if (!ret) {
1066                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1067                         WILC_PIN_MUX_0);
1068                 return 0;
1069         }
1070
1071         /*
1072          * interrupt enable
1073          */
1074         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1075         if (!ret) {
1076                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1077                         WILC_INTR_ENABLE);
1078                 return 0;
1079         }
1080
1081         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1082                 reg |= (BIT((27 + i)));
1083
1084         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1085         if (!ret) {
1086                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1087                         WILC_INTR_ENABLE);
1088                 return 0;
1089         }
1090         if (nint) {
1091                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1092                 if (!ret) {
1093                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1094                                 WILC_INTR2_ENABLE);
1095                         return 0;
1096                 }
1097
1098                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1099                         reg |= BIT(i);
1100
1101                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1102                 if (!ret) {
1103                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1104                                 WILC_INTR2_ENABLE);
1105                         return 0;
1106                 }
1107         }
1108
1109         return 1;
1110 }
1111
1112 /* Global spi HIF function table */
1113 static const struct wilc_hif_func wilc_hif_spi = {
1114         .hif_init = wilc_spi_init,
1115         .hif_deinit = _wilc_spi_deinit,
1116         .hif_read_reg = wilc_spi_read_reg,
1117         .hif_write_reg = wilc_spi_write_reg,
1118         .hif_block_rx = wilc_spi_read,
1119         .hif_block_tx = wilc_spi_write,
1120         .hif_read_int = wilc_spi_read_int,
1121         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1122         .hif_read_size = wilc_spi_read_size,
1123         .hif_block_tx_ext = wilc_spi_write,
1124         .hif_block_rx_ext = wilc_spi_read,
1125         .hif_sync_ext = wilc_spi_sync_ext,
1126 };