1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
6 * Purpose: MAC routines
13 * vt6655_mac_is_reg_bits_off - Test if All test Bits Off
14 * vt6655_mac_set_short_retry_limit - Set 802.11 Short Retry limit
15 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
16 * vt6655_mac_set_loopback_mode - Set MAC Loopback Mode
17 * vt6655_mac_save_context - Save Context of MAC Registers
18 * vt6655_mac_restore_context - Restore Context of MAC Registers
19 * MACbSoftwareReset - Software Reset MAC
20 * vt6655_mac_safe_rx_off - Turn Off MAC Rx
21 * vt6655_mac_safe_tx_off - Turn Off MAC Tx
22 * vt6655_mac_safe_stop - Stop MAC function
23 * MACbShutdown - Shut down MAC
24 * MACvInitialize - Initialize MAC
25 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
26 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
27 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
28 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
31 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
32 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
33 * MACvEnableBusSusEn()
34 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
40 void vt6655_mac_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
42 unsigned char reg_value;
44 reg_value = ioread8(iobase + reg_offset);
45 iowrite8(reg_value | bit_mask, iobase + reg_offset);
48 void vt6655_mac_word_reg_bits_on(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
50 unsigned short reg_value;
52 reg_value = ioread16(iobase + reg_offset);
53 iowrite16(reg_value | (bit_mask), iobase + reg_offset);
56 void vt6655_mac_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u8 bit_mask)
58 unsigned char reg_value;
60 reg_value = ioread8(iobase + reg_offset);
61 iowrite8(reg_value & ~(bit_mask), iobase + reg_offset);
64 void vt6655_mac_word_reg_bits_off(void __iomem *iobase, const u8 reg_offset, const u16 bit_mask)
66 unsigned short reg_value;
68 reg_value = ioread16(iobase + reg_offset);
69 iowrite16(reg_value & ~(bit_mask), iobase + reg_offset);
72 static void vt6655_mac_clear_stck_ds(void __iomem *iobase)
76 reg_value = ioread8(iobase + MAC_REG_STICKHW);
77 reg_value = reg_value & 0xFC;
78 iowrite8(reg_value, iobase + MAC_REG_STICKHW);
83 * Test if all test bits off
87 * io_base - Base Address for MAC
88 * reg_offset - Offset of MAC Register
93 * Return Value: true if all test bits Off; otherwise false
96 static bool vt6655_mac_is_reg_bits_off(struct vnt_private *priv,
97 unsigned char reg_offset,
100 void __iomem *io_base = priv->port_offset;
102 return !(ioread8(io_base + reg_offset) & mask);
107 * Set 802.11 Short Retry Limit
111 * io_base - Base Address for MAC
112 * retry_limit - Retry Limit
119 void vt6655_mac_set_short_retry_limit(struct vnt_private *priv, unsigned char retry_limit)
121 void __iomem *io_base = priv->port_offset;
123 iowrite8(retry_limit, io_base + MAC_REG_SRT);
128 * Set 802.11 Long Retry Limit
132 * io_base - Base Address for MAC
133 * byRetryLimit- Retry Limit
140 void MACvSetLongRetryLimit(struct vnt_private *priv,
141 unsigned char byRetryLimit)
143 void __iomem *io_base = priv->port_offset;
145 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
150 * Set MAC Loopback mode
154 * io_base - Base Address for MAC
155 * loopback_mode - Loopback Mode
162 static void vt6655_mac_set_loopback_mode(struct vnt_private *priv, u8 loopback_mode)
164 void __iomem *io_base = priv->port_offset;
168 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | loopback_mode, io_base + MAC_REG_TEST);
173 * Save MAC registers to context buffer
177 * io_base - Base Address for MAC
179 * cxt_buf - Context buffer
184 static void vt6655_mac_save_context(struct vnt_private *priv, u8 *cxt_buf)
186 void __iomem *io_base = priv->port_offset;
188 /* read page0 register */
189 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
191 VT6655_MAC_SELECT_PAGE1(io_base);
193 /* read page1 register */
194 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
195 MAC_MAX_CONTEXT_SIZE_PAGE1);
197 VT6655_MAC_SELECT_PAGE0(io_base);
202 * Restore MAC registers from context buffer
206 * io_base - Base Address for MAC
207 * cxt_buf - Context buffer
214 static void vt6655_mac_restore_context(struct vnt_private *priv, u8 *cxt_buf)
216 void __iomem *io_base = priv->port_offset;
218 VT6655_MAC_SELECT_PAGE1(io_base);
220 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
221 MAC_MAX_CONTEXT_SIZE_PAGE1);
223 VT6655_MAC_SELECT_PAGE0(io_base);
225 /* restore RCR,TCR,IMR... */
226 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
227 MAC_REG_ISR - MAC_REG_RCR);
229 /* restore MAC Config. */
230 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
231 MAC_REG_PAGE1SEL - MAC_REG_LRT);
233 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
235 /* restore PS Config. */
236 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
237 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
239 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
240 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
241 io_base + MAC_REG_TXDMAPTR0);
242 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
243 io_base + MAC_REG_AC0DMAPTR);
244 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
245 io_base + MAC_REG_BCNDMAPTR);
246 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
247 io_base + MAC_REG_RXDMAPTR0);
248 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
249 io_base + MAC_REG_RXDMAPTR1);
258 * io_base - Base Address for MAC
262 * Return Value: true if Reset Success; otherwise false
265 bool MACbSoftwareReset(struct vnt_private *priv)
267 void __iomem *io_base = priv->port_offset;
270 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
271 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
273 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
274 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
277 if (ww == W_MAX_TIMEOUT)
284 * save some important register's value, then do reset, then restore
289 * io_base - Base Address for MAC
293 * Return Value: true if success; otherwise false
296 static void vt6655_mac_save_soft_reset(struct vnt_private *priv)
298 u8 tmp_reg_data[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
301 * save some important register's value, then do
302 * reset, then restore register's value
304 /* save MAC context */
305 vt6655_mac_save_context(priv, tmp_reg_data);
307 MACbSoftwareReset(priv);
308 /* restore MAC context, except CR0 */
309 vt6655_mac_restore_context(priv, tmp_reg_data);
318 * io_base - Base Address for MAC
322 * Return Value: true if success; otherwise false
325 static bool vt6655_mac_safe_rx_off(struct vnt_private *priv)
327 void __iomem *io_base = priv->port_offset;
330 /* turn off wow temp for turn off Rx safely */
332 /* Clear RX DMA0,1 */
333 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
334 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
335 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
336 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
339 if (ww == W_MAX_TIMEOUT) {
340 pr_debug(" DBG_PORT80(0x10)\n");
343 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
344 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
347 if (ww == W_MAX_TIMEOUT) {
348 pr_debug(" DBG_PORT80(0x11)\n");
352 /* try to safe shutdown RX */
353 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
354 /* W_MAX_TIMEOUT is the timeout period */
355 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
356 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
359 if (ww == W_MAX_TIMEOUT) {
360 pr_debug(" DBG_PORT80(0x12)\n");
372 * io_base - Base Address for MAC
376 * Return Value: true if success; otherwise false
379 static bool vt6655_mac_safe_tx_off(struct vnt_private *priv)
381 void __iomem *io_base = priv->port_offset;
386 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
388 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
390 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
391 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
394 if (ww == W_MAX_TIMEOUT) {
395 pr_debug(" DBG_PORT80(0x20)\n");
398 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
399 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
402 if (ww == W_MAX_TIMEOUT) {
403 pr_debug(" DBG_PORT80(0x21)\n");
407 /* try to safe shutdown TX */
408 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
410 /* W_MAX_TIMEOUT is the timeout period */
411 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
412 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
415 if (ww == W_MAX_TIMEOUT) {
416 pr_debug(" DBG_PORT80(0x24)\n");
428 * io_base - Base Address for MAC
432 * Return Value: true if success; otherwise false
435 static bool vt6655_mac_safe_stop(struct vnt_private *priv)
437 void __iomem *io_base = priv->port_offset;
439 vt6655_mac_reg_bits_off(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
441 if (!vt6655_mac_safe_rx_off(priv)) {
442 pr_debug(" vt6655_mac_safe_rx_off == false)\n");
443 vt6655_mac_save_soft_reset(priv);
446 if (!vt6655_mac_safe_tx_off(priv)) {
447 pr_debug(" vt6655_mac_safe_tx_off == false)\n");
448 vt6655_mac_save_soft_reset(priv);
452 vt6655_mac_reg_bits_off(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
463 * io_base - Base Address for MAC
467 * Return Value: true if success; otherwise false
470 bool MACbShutdown(struct vnt_private *priv)
472 void __iomem *io_base = priv->port_offset;
473 /* disable MAC IMR */
474 iowrite32(0, io_base + MAC_REG_IMR);
475 vt6655_mac_set_loopback_mode(priv, MAC_LB_INTERNAL);
476 /* stop the adapter */
477 if (!vt6655_mac_safe_stop(priv)) {
478 vt6655_mac_set_loopback_mode(priv, MAC_LB_NONE);
481 vt6655_mac_set_loopback_mode(priv, MAC_LB_NONE);
491 * io_base - Base Address for MAC
498 void MACvInitialize(struct vnt_private *priv)
500 void __iomem *io_base = priv->port_offset;
501 /* clear sticky bits */
502 vt6655_mac_clear_stck_ds(io_base);
503 /* disable force PME-enable */
504 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
508 MACbSoftwareReset(priv);
510 /* reset TSF counter */
511 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
512 /* enable TSF counter */
513 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
518 * Set the chip with current rx descriptor address
522 * io_base - Base Address for MAC
523 * curr_desc_addr - Descriptor Address
530 void vt6655_mac_set_curr_rx_0_desc_addr(struct vnt_private *priv, u32 curr_desc_addr)
532 void __iomem *io_base = priv->port_offset;
534 unsigned char org_dma_ctl;
536 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
537 if (org_dma_ctl & DMACTL_RUN)
538 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
540 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
541 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
545 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
546 if (org_dma_ctl & DMACTL_RUN)
547 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
552 * Set the chip with current rx descriptor address
556 * io_base - Base Address for MAC
557 * curr_desc_addr - Descriptor Address
564 void vt6655_mac_set_curr_rx_1_desc_addr(struct vnt_private *priv, u32 curr_desc_addr)
566 void __iomem *io_base = priv->port_offset;
568 unsigned char org_dma_ctl;
570 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
571 if (org_dma_ctl & DMACTL_RUN)
572 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
574 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
575 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
579 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
580 if (org_dma_ctl & DMACTL_RUN)
581 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
586 * Set the chip with current tx0 descriptor address
590 * io_base - Base Address for MAC
591 * curr_desc_addr - Descriptor Address
598 static void vt6655_mac_set_curr_tx_0_desc_addr_ex(struct vnt_private *priv, u32 curr_desc_addr)
600 void __iomem *io_base = priv->port_offset;
602 unsigned char org_dma_ctl;
604 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
605 if (org_dma_ctl & DMACTL_RUN)
606 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
608 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
609 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
613 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
614 if (org_dma_ctl & DMACTL_RUN)
615 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
620 * Set the chip with current AC0 descriptor address
624 * io_base - Base Address for MAC
625 * curr_desc_addr - Descriptor Address
632 /* TxDMA1 = AC0DMA */
633 static void vt6655_mac_set_curr_ac_0_desc_addr_ex(struct vnt_private *priv, u32 curr_desc_addr)
635 void __iomem *io_base = priv->port_offset;
637 unsigned char org_dma_ctl;
639 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
640 if (org_dma_ctl & DMACTL_RUN)
641 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
643 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
644 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
647 if (ww == W_MAX_TIMEOUT)
648 pr_debug(" DBG_PORT80(0x26)\n");
649 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
650 if (org_dma_ctl & DMACTL_RUN)
651 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
654 void vt6655_mac_set_curr_tx_desc_addr(int tx_type, struct vnt_private *priv, u32 curr_desc_addr)
656 if (tx_type == TYPE_AC0DMA)
657 vt6655_mac_set_curr_ac_0_desc_addr_ex(priv, curr_desc_addr);
658 else if (tx_type == TYPE_TXDMA0)
659 vt6655_mac_set_curr_tx_0_desc_addr_ex(priv, curr_desc_addr);
664 * Micro Second Delay via MAC
668 * io_base - Base Address for MAC
669 * uDelay - Delay time (timer resolution is 4 us)
676 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
678 void __iomem *io_base = priv->port_offset;
679 unsigned char byValue;
682 iowrite8(0, io_base + MAC_REG_TMCTL0);
683 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
684 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
685 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
686 for (uu = 0; uu < uDelay; uu++) {
687 byValue = ioread8(io_base + MAC_REG_TMCTL0);
688 if ((byValue == 0) ||
689 (byValue & TMCTL_TSUSP)) {
690 iowrite8(0, io_base + MAC_REG_TMCTL0);
695 iowrite8(0, io_base + MAC_REG_TMCTL0);
700 * Micro Second One shot timer via MAC
704 * io_base - Base Address for MAC
705 * uDelay - Delay time
712 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
713 unsigned int uDelayTime)
715 void __iomem *io_base = priv->port_offset;
717 iowrite8(0, io_base + MAC_REG_TMCTL1);
718 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
719 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
722 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
725 void __iomem *io_base = priv->port_offset;
729 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
730 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
731 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
734 bool MACbPSWakeup(struct vnt_private *priv)
736 void __iomem *io_base = priv->port_offset;
739 if (vt6655_mac_is_reg_bits_off(priv, MAC_REG_PSCTL, PSCTL_PS))
743 vt6655_mac_reg_bits_off(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
745 /* Check if SyncFlushOK */
746 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
747 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
750 if (ww == W_MAX_TIMEOUT) {
751 pr_debug(" DBG_PORT80(0x33)\n");
759 * Set the Key by MISCFIFO
763 * io_base - Base Address for MAC
772 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
773 unsigned int uEntryIdx, unsigned int uKeyIdx,
774 unsigned char *pbyAddr, u32 *pdwKey,
775 unsigned char local_id)
777 void __iomem *io_base = priv->port_offset;
778 unsigned short offset;
785 offset = MISCFIFO_KEYETRY0;
786 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
791 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
792 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
793 offset, data, wKeyCtl);
795 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
796 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
797 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
801 data |= *(pbyAddr + 3);
803 data |= *(pbyAddr + 2);
805 data |= *(pbyAddr + 1);
808 pr_debug("2. offset: %d, Data: %X\n", offset, data);
810 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
811 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
812 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
815 offset += (uKeyIdx * 4);
816 for (ii = 0; ii < 4; ii++) {
817 /* always push 128 bits */
818 pr_debug("3.(%d) offset: %d, Data: %X\n",
819 ii, offset + ii, *pdwKey);
820 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
821 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
822 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
828 * Disable the Key Entry by MISCFIFO
832 * io_base - Base Address for MAC
840 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
842 void __iomem *io_base = priv->port_offset;
843 unsigned short offset;
845 offset = MISCFIFO_KEYETRY0;
846 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
848 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
849 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
850 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);