1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
6 * Purpose: MAC routines
13 * MACbIsRegBitsOff - Test if All test Bits Off
14 * MACbIsIntDisable - Test if MAC interrupt disable
15 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
16 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
17 * MACvSetLoopbackMode - Set MAC Loopback Mode
18 * MACvSaveContext - Save Context of MAC Registers
19 * MACvRestoreContext - Restore Context of MAC Registers
20 * MACbSoftwareReset - Software Reset MAC
21 * MACbSafeRxOff - Turn Off MAC Rx
22 * MACbSafeTxOff - Turn Off MAC Tx
23 * MACbSafeStop - Stop MAC function
24 * MACbShutdown - Shut down MAC
25 * MACvInitialize - Initialize MAC
26 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
27 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
28 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
29 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
32 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
33 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
34 * MACvEnableBusSusEn()
35 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
43 * Test if all test bits off
47 * io_base - Base Address for MAC
48 * byRegOfs - Offset of MAC Register
49 * byTestBits - Test bits
53 * Return Value: true if all test bits Off; otherwise false
56 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
57 unsigned char byTestBits)
59 void __iomem *io_base = priv->port_offset;
61 return !(ioread8(io_base + byRegOfs) & byTestBits);
66 * Test if MAC interrupt disable
70 * io_base - Base Address for MAC
74 * Return Value: true if interrupt is disable; otherwise false
77 bool MACbIsIntDisable(struct vnt_private *priv)
79 void __iomem *io_base = priv->port_offset;
81 if (ioread32(io_base + MAC_REG_IMR))
89 * Set 802.11 Short Retry Limit
93 * io_base - Base Address for MAC
94 * byRetryLimit- Retry Limit
101 void MACvSetShortRetryLimit(struct vnt_private *priv,
102 unsigned char byRetryLimit)
104 void __iomem *io_base = priv->port_offset;
106 iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
111 * Set 802.11 Long Retry Limit
115 * io_base - Base Address for MAC
116 * byRetryLimit- Retry Limit
123 void MACvSetLongRetryLimit(struct vnt_private *priv,
124 unsigned char byRetryLimit)
126 void __iomem *io_base = priv->port_offset;
128 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
133 * Set MAC Loopback mode
137 * io_base - Base Address for MAC
138 * byLoopbackMode - Loopback Mode
145 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
147 void __iomem *io_base = priv->port_offset;
149 byLoopbackMode <<= 6;
151 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
152 io_base + MAC_REG_TEST);
157 * Save MAC registers to context buffer
161 * io_base - Base Address for MAC
163 * cxt_buf - Context buffer
168 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
170 void __iomem *io_base = priv->port_offset;
172 /* read page0 register */
173 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
175 MACvSelectPage1(io_base);
177 /* read page1 register */
178 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
179 MAC_MAX_CONTEXT_SIZE_PAGE1);
181 MACvSelectPage0(io_base);
186 * Restore MAC registers from context buffer
190 * io_base - Base Address for MAC
191 * cxt_buf - Context buffer
198 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
200 void __iomem *io_base = priv->port_offset;
202 MACvSelectPage1(io_base);
204 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
205 MAC_MAX_CONTEXT_SIZE_PAGE1);
207 MACvSelectPage0(io_base);
209 /* restore RCR,TCR,IMR... */
210 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
211 MAC_REG_ISR - MAC_REG_RCR);
213 /* restore MAC Config. */
214 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
215 MAC_REG_PAGE1SEL - MAC_REG_LRT);
217 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
219 /* restore PS Config. */
220 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
221 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
223 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
224 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
225 io_base + MAC_REG_TXDMAPTR0);
226 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
227 io_base + MAC_REG_AC0DMAPTR);
228 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
229 io_base + MAC_REG_BCNDMAPTR);
230 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
231 io_base + MAC_REG_RXDMAPTR0);
232 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
233 io_base + MAC_REG_RXDMAPTR1);
242 * io_base - Base Address for MAC
246 * Return Value: true if Reset Success; otherwise false
249 bool MACbSoftwareReset(struct vnt_private *priv)
251 void __iomem *io_base = priv->port_offset;
254 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
255 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
257 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
258 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
261 if (ww == W_MAX_TIMEOUT)
268 * save some important register's value, then do reset, then restore
273 * io_base - Base Address for MAC
277 * Return Value: true if success; otherwise false
280 bool MACbSafeSoftwareReset(struct vnt_private *priv)
282 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
286 * save some important register's value, then do
287 * reset, then restore register's value
289 /* save MAC context */
290 MACvSaveContext(priv, abyTmpRegData);
292 bRetVal = MACbSoftwareReset(priv);
293 /* restore MAC context, except CR0 */
294 MACvRestoreContext(priv, abyTmpRegData);
305 * io_base - Base Address for MAC
309 * Return Value: true if success; otherwise false
312 bool MACbSafeRxOff(struct vnt_private *priv)
314 void __iomem *io_base = priv->port_offset;
317 /* turn off wow temp for turn off Rx safely */
319 /* Clear RX DMA0,1 */
320 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
321 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
322 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
323 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
326 if (ww == W_MAX_TIMEOUT) {
327 pr_debug(" DBG_PORT80(0x10)\n");
330 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
331 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
334 if (ww == W_MAX_TIMEOUT) {
335 pr_debug(" DBG_PORT80(0x11)\n");
339 /* try to safe shutdown RX */
340 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
341 /* W_MAX_TIMEOUT is the timeout period */
342 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
343 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
346 if (ww == W_MAX_TIMEOUT) {
347 pr_debug(" DBG_PORT80(0x12)\n");
359 * io_base - Base Address for MAC
363 * Return Value: true if success; otherwise false
366 bool MACbSafeTxOff(struct vnt_private *priv)
368 void __iomem *io_base = priv->port_offset;
373 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
375 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
377 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
378 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
381 if (ww == W_MAX_TIMEOUT) {
382 pr_debug(" DBG_PORT80(0x20)\n");
385 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
386 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
389 if (ww == W_MAX_TIMEOUT) {
390 pr_debug(" DBG_PORT80(0x21)\n");
394 /* try to safe shutdown TX */
395 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
397 /* W_MAX_TIMEOUT is the timeout period */
398 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
399 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
402 if (ww == W_MAX_TIMEOUT) {
403 pr_debug(" DBG_PORT80(0x24)\n");
415 * io_base - Base Address for MAC
419 * Return Value: true if success; otherwise false
422 bool MACbSafeStop(struct vnt_private *priv)
424 void __iomem *io_base = priv->port_offset;
426 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
428 if (!MACbSafeRxOff(priv)) {
429 pr_debug(" MACbSafeRxOff == false)\n");
430 MACbSafeSoftwareReset(priv);
433 if (!MACbSafeTxOff(priv)) {
434 pr_debug(" MACbSafeTxOff == false)\n");
435 MACbSafeSoftwareReset(priv);
439 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
450 * io_base - Base Address for MAC
454 * Return Value: true if success; otherwise false
457 bool MACbShutdown(struct vnt_private *priv)
459 void __iomem *io_base = priv->port_offset;
460 /* disable MAC IMR */
461 MACvIntDisable(io_base);
462 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
463 /* stop the adapter */
464 if (!MACbSafeStop(priv)) {
465 MACvSetLoopbackMode(priv, MAC_LB_NONE);
468 MACvSetLoopbackMode(priv, MAC_LB_NONE);
478 * io_base - Base Address for MAC
485 void MACvInitialize(struct vnt_private *priv)
487 void __iomem *io_base = priv->port_offset;
488 /* clear sticky bits */
489 MACvClearStckDS(io_base);
490 /* disable force PME-enable */
491 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
495 MACbSoftwareReset(priv);
497 /* reset TSF counter */
498 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
499 /* enable TSF counter */
500 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
505 * Set the chip with current rx descriptor address
509 * io_base - Base Address for MAC
510 * curr_desc_addr - Descriptor Address
517 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
519 void __iomem *io_base = priv->port_offset;
521 unsigned char org_dma_ctl;
523 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
524 if (org_dma_ctl & DMACTL_RUN)
525 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
527 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
528 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
532 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
533 if (org_dma_ctl & DMACTL_RUN)
534 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
539 * Set the chip with current rx descriptor address
543 * io_base - Base Address for MAC
544 * curr_desc_addr - Descriptor Address
551 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
553 void __iomem *io_base = priv->port_offset;
555 unsigned char org_dma_ctl;
557 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
558 if (org_dma_ctl & DMACTL_RUN)
559 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
561 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
562 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
566 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
567 if (org_dma_ctl & DMACTL_RUN)
568 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
573 * Set the chip with current tx0 descriptor address
577 * io_base - Base Address for MAC
578 * curr_desc_addr - Descriptor Address
585 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
588 void __iomem *io_base = priv->port_offset;
590 unsigned char org_dma_ctl;
592 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
593 if (org_dma_ctl & DMACTL_RUN)
594 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
596 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
597 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
601 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
602 if (org_dma_ctl & DMACTL_RUN)
603 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
608 * Set the chip with current AC0 descriptor address
612 * io_base - Base Address for MAC
613 * curr_desc_addr - Descriptor Address
620 /* TxDMA1 = AC0DMA */
621 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
624 void __iomem *io_base = priv->port_offset;
626 unsigned char org_dma_ctl;
628 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
629 if (org_dma_ctl & DMACTL_RUN)
630 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
632 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
633 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
636 if (ww == W_MAX_TIMEOUT)
637 pr_debug(" DBG_PORT80(0x26)\n");
638 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
639 if (org_dma_ctl & DMACTL_RUN)
640 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
643 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
646 if (iTxType == TYPE_AC0DMA)
647 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
648 else if (iTxType == TYPE_TXDMA0)
649 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
654 * Micro Second Delay via MAC
658 * io_base - Base Address for MAC
659 * uDelay - Delay time (timer resolution is 4 us)
666 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
668 void __iomem *io_base = priv->port_offset;
669 unsigned char byValue;
672 iowrite8(0, io_base + MAC_REG_TMCTL0);
673 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
674 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
675 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
676 for (uu = 0; uu < uDelay; uu++) {
677 byValue = ioread8(io_base + MAC_REG_TMCTL0);
678 if ((byValue == 0) ||
679 (byValue & TMCTL_TSUSP)) {
680 iowrite8(0, io_base + MAC_REG_TMCTL0);
685 iowrite8(0, io_base + MAC_REG_TMCTL0);
690 * Micro Second One shot timer via MAC
694 * io_base - Base Address for MAC
695 * uDelay - Delay time
702 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
703 unsigned int uDelayTime)
705 void __iomem *io_base = priv->port_offset;
707 iowrite8(0, io_base + MAC_REG_TMCTL1);
708 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
709 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
712 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
715 void __iomem *io_base = priv->port_offset;
719 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
720 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
721 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
724 bool MACbPSWakeup(struct vnt_private *priv)
726 void __iomem *io_base = priv->port_offset;
729 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
733 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
735 /* Check if SyncFlushOK */
736 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
737 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
740 if (ww == W_MAX_TIMEOUT) {
741 pr_debug(" DBG_PORT80(0x33)\n");
749 * Set the Key by MISCFIFO
753 * io_base - Base Address for MAC
762 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
763 unsigned int uEntryIdx, unsigned int uKeyIdx,
764 unsigned char *pbyAddr, u32 *pdwKey,
765 unsigned char local_id)
767 void __iomem *io_base = priv->port_offset;
768 unsigned short offset;
775 offset = MISCFIFO_KEYETRY0;
776 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
781 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
782 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
783 offset, data, wKeyCtl);
785 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
786 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
787 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
791 data |= *(pbyAddr + 3);
793 data |= *(pbyAddr + 2);
795 data |= *(pbyAddr + 1);
798 pr_debug("2. offset: %d, Data: %X\n", offset, data);
800 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
801 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
802 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
805 offset += (uKeyIdx * 4);
806 for (ii = 0; ii < 4; ii++) {
807 /* always push 128 bits */
808 pr_debug("3.(%d) offset: %d, Data: %X\n",
809 ii, offset + ii, *pdwKey);
810 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
811 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
812 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
818 * Disable the Key Entry by MISCFIFO
822 * io_base - Base Address for MAC
830 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
832 void __iomem *io_base = priv->port_offset;
833 unsigned short offset;
835 offset = MISCFIFO_KEYETRY0;
836 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
838 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
839 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
840 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);