1 /* SPDX-License-Identifier: GPL-2.0 */
5 #define PIO2_CARDS_MAX 32
7 #define PIO2_VARIANT_LENGTH 5
9 #define PIO2_NUM_CHANNELS 32
10 #define PIO2_NUM_IRQS 11
11 #define PIO2_NUM_CNTRS 6
13 #define PIO2_REGS_SIZE 0x40
15 #define PIO2_REGS_DATA0 0x0
16 #define PIO2_REGS_DATA1 0x1
17 #define PIO2_REGS_DATA2 0x2
18 #define PIO2_REGS_DATA3 0x3
20 static const int PIO2_REGS_DATA[4] = { PIO2_REGS_DATA0, PIO2_REGS_DATA1,
21 PIO2_REGS_DATA2, PIO2_REGS_DATA3 };
23 #define PIO2_REGS_INT_STAT0 0x8
24 #define PIO2_REGS_INT_STAT1 0x9
25 #define PIO2_REGS_INT_STAT2 0xa
26 #define PIO2_REGS_INT_STAT3 0xb
28 static const int PIO2_REGS_INT_STAT[4] = { PIO2_REGS_INT_STAT0,
31 PIO2_REGS_INT_STAT3 };
33 #define PIO2_REGS_INT_STAT_CNTR 0xc
34 #define PIO2_REGS_INT_MASK0 0x10
35 #define PIO2_REGS_INT_MASK1 0x11
36 #define PIO2_REGS_INT_MASK2 0x12
37 #define PIO2_REGS_INT_MASK3 0x13
38 #define PIO2_REGS_INT_MASK4 0x14
39 #define PIO2_REGS_INT_MASK5 0x15
40 #define PIO2_REGS_INT_MASK6 0x16
41 #define PIO2_REGS_INT_MASK7 0x17
43 static const int PIO2_REGS_INT_MASK[8] = { PIO2_REGS_INT_MASK0,
50 PIO2_REGS_INT_MASK7 };
52 #define PIO2_REGS_CTRL 0x18
53 #define PIO2_REGS_VME_VECTOR 0x19
54 #define PIO2_REGS_CNTR0 0x20
55 #define PIO2_REGS_CNTR1 0x22
56 #define PIO2_REGS_CNTR2 0x24
57 #define PIO2_REGS_CTRL_WRD0 0x26
58 #define PIO2_REGS_CNTR3 0x28
59 #define PIO2_REGS_CNTR4 0x2a
60 #define PIO2_REGS_CNTR5 0x2c
61 #define PIO2_REGS_CTRL_WRD1 0x2e
63 #define PIO2_REGS_ID 0x30
65 /* PIO2_REGS_DATAx (0x0 - 0x3) */
67 static const int PIO2_CHANNEL_BANK[32] = { 0, 0, 0, 0, 0, 0, 0, 0,
68 1, 1, 1, 1, 1, 1, 1, 1,
69 2, 2, 2, 2, 2, 2, 2, 2,
70 3, 3, 3, 3, 3, 3, 3, 3 };
72 #define PIO2_CHANNEL0_BIT BIT(0)
73 #define PIO2_CHANNEL1_BIT BIT(1)
74 #define PIO2_CHANNEL2_BIT BIT(2)
75 #define PIO2_CHANNEL3_BIT BIT(3)
76 #define PIO2_CHANNEL4_BIT BIT(4)
77 #define PIO2_CHANNEL5_BIT BIT(5)
78 #define PIO2_CHANNEL6_BIT BIT(6)
79 #define PIO2_CHANNEL7_BIT BIT(7)
80 #define PIO2_CHANNEL8_BIT BIT(0)
81 #define PIO2_CHANNEL9_BIT BIT(1)
82 #define PIO2_CHANNEL10_BIT BIT(2)
83 #define PIO2_CHANNEL11_BIT BIT(3)
84 #define PIO2_CHANNEL12_BIT BIT(4)
85 #define PIO2_CHANNEL13_BIT BIT(5)
86 #define PIO2_CHANNEL14_BIT BIT(6)
87 #define PIO2_CHANNEL15_BIT BIT(7)
88 #define PIO2_CHANNEL16_BIT BIT(0)
89 #define PIO2_CHANNEL17_BIT BIT(1)
90 #define PIO2_CHANNEL18_BIT BIT(2)
91 #define PIO2_CHANNEL19_BIT BIT(3)
92 #define PIO2_CHANNEL20_BIT BIT(4)
93 #define PIO2_CHANNEL21_BIT BIT(5)
94 #define PIO2_CHANNEL22_BIT BIT(6)
95 #define PIO2_CHANNEL23_BIT BIT(7)
96 #define PIO2_CHANNEL24_BIT BIT(0)
97 #define PIO2_CHANNEL25_BIT BIT(1)
98 #define PIO2_CHANNEL26_BIT BIT(2)
99 #define PIO2_CHANNEL27_BIT BIT(3)
100 #define PIO2_CHANNEL28_BIT BIT(4)
101 #define PIO2_CHANNEL29_BIT BIT(5)
102 #define PIO2_CHANNEL30_BIT BIT(6)
103 #define PIO2_CHANNEL31_BIT BIT(7)
105 static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT,
106 PIO2_CHANNEL2_BIT, PIO2_CHANNEL3_BIT,
107 PIO2_CHANNEL4_BIT, PIO2_CHANNEL5_BIT,
108 PIO2_CHANNEL6_BIT, PIO2_CHANNEL7_BIT,
109 PIO2_CHANNEL8_BIT, PIO2_CHANNEL9_BIT,
110 PIO2_CHANNEL10_BIT, PIO2_CHANNEL11_BIT,
111 PIO2_CHANNEL12_BIT, PIO2_CHANNEL13_BIT,
112 PIO2_CHANNEL14_BIT, PIO2_CHANNEL15_BIT,
113 PIO2_CHANNEL16_BIT, PIO2_CHANNEL17_BIT,
114 PIO2_CHANNEL18_BIT, PIO2_CHANNEL19_BIT,
115 PIO2_CHANNEL20_BIT, PIO2_CHANNEL21_BIT,
116 PIO2_CHANNEL22_BIT, PIO2_CHANNEL23_BIT,
117 PIO2_CHANNEL24_BIT, PIO2_CHANNEL25_BIT,
118 PIO2_CHANNEL26_BIT, PIO2_CHANNEL27_BIT,
119 PIO2_CHANNEL28_BIT, PIO2_CHANNEL29_BIT,
120 PIO2_CHANNEL30_BIT, PIO2_CHANNEL31_BIT
123 /* PIO2_REGS_INT_STAT_CNTR (0xc) */
124 #define PIO2_COUNTER0 BIT(0)
125 #define PIO2_COUNTER1 BIT(1)
126 #define PIO2_COUNTER2 BIT(2)
127 #define PIO2_COUNTER3 BIT(3)
128 #define PIO2_COUNTER4 BIT(4)
129 #define PIO2_COUNTER5 BIT(5)
131 static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1,
132 PIO2_COUNTER2, PIO2_COUNTER3,
133 PIO2_COUNTER4, PIO2_COUNTER5 };
135 /* PIO2_REGS_CTRL (0x18) */
136 #define PIO2_VME_INT_MASK 0x7
137 #define PIO2_LED BIT(6)
138 #define PIO2_LOOP BIT(7)
140 /* PIO2_REGS_VME_VECTOR (0x19) */
141 #define PIO2_VME_VECTOR_SPUR 0x0
142 #define PIO2_VME_VECTOR_BANK0 0x1
143 #define PIO2_VME_VECTOR_BANK1 0x2
144 #define PIO2_VME_VECTOR_BANK2 0x3
145 #define PIO2_VME_VECTOR_BANK3 0x4
146 #define PIO2_VME_VECTOR_CNTR0 0x5
147 #define PIO2_VME_VECTOR_CNTR1 0x6
148 #define PIO2_VME_VECTOR_CNTR2 0x7
149 #define PIO2_VME_VECTOR_CNTR3 0x8
150 #define PIO2_VME_VECTOR_CNTR4 0x9
151 #define PIO2_VME_VECTOR_CNTR5 0xa
153 #define PIO2_VME_VECTOR_MASK 0xf0
155 static const int PIO2_VECTOR_BANK[4] = { PIO2_VME_VECTOR_BANK0,
156 PIO2_VME_VECTOR_BANK1,
157 PIO2_VME_VECTOR_BANK2,
158 PIO2_VME_VECTOR_BANK3 };
160 static const int PIO2_VECTOR_CNTR[6] = { PIO2_VME_VECTOR_CNTR0,
161 PIO2_VME_VECTOR_CNTR1,
162 PIO2_VME_VECTOR_CNTR2,
163 PIO2_VME_VECTOR_CNTR3,
164 PIO2_VME_VECTOR_CNTR4,
165 PIO2_VME_VECTOR_CNTR5 };
167 /* PIO2_REGS_CNTRx (0x20 - 0x24 & 0x28 - 0x2c) */
169 static const int PIO2_CNTR_DATA[6] = { PIO2_REGS_CNTR0, PIO2_REGS_CNTR1,
170 PIO2_REGS_CNTR2, PIO2_REGS_CNTR3,
171 PIO2_REGS_CNTR4, PIO2_REGS_CNTR5 };
173 /* PIO2_REGS_CTRL_WRDx (0x26 & 0x2e) */
175 static const int PIO2_CNTR_CTRL[6] = { PIO2_REGS_CTRL_WRD0,
180 PIO2_REGS_CTRL_WRD1 };
182 #define PIO2_CNTR_SC_DEV0 0
183 #define PIO2_CNTR_SC_DEV1 (1 << 6)
184 #define PIO2_CNTR_SC_DEV2 (2 << 6)
185 #define PIO2_CNTR_SC_RDBACK (3 << 6)
187 static const int PIO2_CNTR_SC_DEV[6] = { PIO2_CNTR_SC_DEV0, PIO2_CNTR_SC_DEV1,
188 PIO2_CNTR_SC_DEV2, PIO2_CNTR_SC_DEV0,
189 PIO2_CNTR_SC_DEV1, PIO2_CNTR_SC_DEV2 };
191 #define PIO2_CNTR_RW_LATCH 0
192 #define PIO2_CNTR_RW_LSB (1 << 4)
193 #define PIO2_CNTR_RW_MSB (2 << 4)
194 #define PIO2_CNTR_RW_BOTH (3 << 4)
196 #define PIO2_CNTR_MODE0 0
197 #define PIO2_CNTR_MODE1 (1 << 1)
198 #define PIO2_CNTR_MODE2 (2 << 1)
199 #define PIO2_CNTR_MODE3 (3 << 1)
200 #define PIO2_CNTR_MODE4 (4 << 1)
201 #define PIO2_CNTR_MODE5 (5 << 1)
203 #define PIO2_CNTR_BCD 1
205 enum pio2_bank_config { NOFIT, INPUT, OUTPUT, BOTH };
206 enum pio2_int_config { NONE = 0, LOW2HIGH = 1, HIGH2LOW = 2, EITHER = 4 };
208 /* Bank configuration structure */
209 struct pio2_io_bank {
210 enum pio2_bank_config config;
212 enum pio2_int_config irq[8];
215 /* Counter configuration structure */
230 struct vme_dev *vdev;
231 struct vme_resource *window;
234 struct pio2_io_bank bank[4];
236 struct pio2_cntr cntr[6];
239 int pio2_cntr_reset(struct pio2_card *card);
241 int pio2_gpio_reset(struct pio2_card *card);
242 int pio2_gpio_init(struct pio2_card *card);
243 void pio2_gpio_exit(struct pio2_card *card);
245 #endif /* _VME_PIO2_H_ */