1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
32 struct spi_info *spi = &chip->spi;
34 spi->err_code = err_code;
37 static int spi_init(struct rtsx_chip *chip)
41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
42 CS_POLARITY_LOW | DTO_MSB_FIRST
43 | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
47 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
53 return STATUS_SUCCESS;
56 static int spi_set_init_para(struct rtsx_chip *chip)
58 struct spi_info *spi = &chip->spi;
61 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
62 (u8)(spi->clk_div >> 8));
66 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
72 retval = switch_clock(chip, spi->spi_clock);
73 if (retval != STATUS_SUCCESS) {
77 retval = select_card(chip, SPI_CARD);
78 if (retval != STATUS_SUCCESS) {
82 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
87 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
95 retval = spi_init(chip);
96 if (retval != STATUS_SUCCESS) {
100 return STATUS_SUCCESS;
103 static int sf_polling_status(struct rtsx_chip *chip, int msec)
109 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
110 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
111 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
112 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
115 retval = rtsx_send_cmd(chip, 0, msec);
117 rtsx_clear_spi_error(chip);
118 spi_set_err_code(chip, SPI_BUSY_ERR);
122 return STATUS_SUCCESS;
125 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
127 struct spi_info *spi = &chip->spi;
131 return STATUS_SUCCESS;
135 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
136 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
137 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
138 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
139 SPI_TRANSFER0_START | SPI_C_MODE0);
140 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
143 retval = rtsx_send_cmd(chip, 0, 100);
145 rtsx_clear_spi_error(chip);
146 spi_set_err_code(chip, SPI_HW_ERR);
150 return STATUS_SUCCESS;
153 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
155 struct spi_info *spi = &chip->spi;
159 return STATUS_SUCCESS;
163 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
164 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
165 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
166 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
167 SPI_TRANSFER0_START | SPI_C_MODE0);
168 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
171 retval = rtsx_send_cmd(chip, 0, 100);
173 rtsx_clear_spi_error(chip);
174 spi_set_err_code(chip, SPI_HW_ERR);
178 return STATUS_SUCCESS;
181 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
184 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
185 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
186 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
187 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
188 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
190 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
191 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
193 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
195 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
196 SPI_TRANSFER0_START | SPI_CADO_MODE0);
198 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
199 SPI_TRANSFER0_START | SPI_CDO_MODE0);
201 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
205 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
211 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
212 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
213 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
215 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
216 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
218 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
220 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
221 SPI_TRANSFER0_START | SPI_CA_MODE0);
223 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
224 SPI_TRANSFER0_START | SPI_C_MODE0);
226 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
229 retval = rtsx_send_cmd(chip, 0, 100);
231 rtsx_clear_spi_error(chip);
232 spi_set_err_code(chip, SPI_HW_ERR);
236 return STATUS_SUCCESS;
239 static int spi_init_eeprom(struct rtsx_chip *chip)
249 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
253 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
258 retval = switch_clock(chip, clk);
259 if (retval != STATUS_SUCCESS) {
263 retval = select_card(chip, SPI_CARD);
264 if (retval != STATUS_SUCCESS) {
268 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
273 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
281 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
282 CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
286 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
292 return STATUS_SUCCESS;
295 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
301 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
302 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
303 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
304 SPI_TRANSFER0_START | SPI_CA_MODE0);
305 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
308 retval = rtsx_send_cmd(chip, 0, 100);
313 return STATUS_SUCCESS;
316 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
320 retval = spi_init_eeprom(chip);
321 if (retval != STATUS_SUCCESS) {
325 retval = spi_eeprom_program_enable(chip);
326 if (retval != STATUS_SUCCESS) {
332 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
333 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
334 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
335 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
336 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
337 SPI_TRANSFER0_START | SPI_CA_MODE0);
338 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
341 retval = rtsx_send_cmd(chip, 0, 100);
346 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
351 return STATUS_SUCCESS;
354 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
358 retval = spi_init_eeprom(chip);
359 if (retval != STATUS_SUCCESS) {
363 retval = spi_eeprom_program_enable(chip);
364 if (retval != STATUS_SUCCESS) {
370 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
371 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
372 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
373 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
374 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
375 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
376 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
377 SPI_TRANSFER0_START | SPI_CA_MODE0);
378 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
381 retval = rtsx_send_cmd(chip, 0, 100);
386 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
391 return STATUS_SUCCESS;
394 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
399 retval = spi_init_eeprom(chip);
400 if (retval != STATUS_SUCCESS) {
406 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
407 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
408 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
409 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
410 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
411 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
412 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
413 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
414 SPI_TRANSFER0_START | SPI_CADI_MODE0);
415 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
418 retval = rtsx_send_cmd(chip, 0, 100);
424 retval = rtsx_read_register(chip, SPI_DATA, &data);
432 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
437 return STATUS_SUCCESS;
440 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
444 retval = spi_init_eeprom(chip);
445 if (retval != STATUS_SUCCESS) {
449 retval = spi_eeprom_program_enable(chip);
450 if (retval != STATUS_SUCCESS) {
456 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
457 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
458 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
459 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
460 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
461 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
462 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
463 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
464 SPI_TRANSFER0_START | SPI_CA_MODE0);
465 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
468 retval = rtsx_send_cmd(chip, 0, 100);
473 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
478 return STATUS_SUCCESS;
481 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
483 struct spi_info *spi = &chip->spi;
485 dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__,
487 rtsx_stor_set_xfer_buf(&spi->err_code,
488 min_t(int, scsi_bufflen(srb), 1), srb);
489 scsi_set_resid(srb, scsi_bufflen(srb) - 1);
491 return STATUS_SUCCESS;
494 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
496 struct spi_info *spi = &chip->spi;
498 spi_set_err_code(chip, SPI_NO_ERR);
501 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
503 spi->spi_clock = srb->cmnd[3];
505 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
506 spi->write_en = srb->cmnd[6];
508 dev_dbg(rtsx_dev(chip), "%s: ", __func__);
509 dev_dbg(rtsx_dev(chip), "spi_clock = %d, ", spi->spi_clock);
510 dev_dbg(rtsx_dev(chip), "clk_div = %d, ", spi->clk_div);
511 dev_dbg(rtsx_dev(chip), "write_en = %d\n", spi->write_en);
513 return STATUS_SUCCESS;
516 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
522 spi_set_err_code(chip, SPI_NO_ERR);
524 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
526 spi_set_err_code(chip, SPI_INVALID_COMMAND);
530 retval = spi_set_init_para(chip);
531 if (retval != STATUS_SUCCESS) {
532 spi_set_err_code(chip, SPI_HW_ERR);
538 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
541 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
542 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
543 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
544 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
545 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
546 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
547 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
548 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
552 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
553 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
555 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
556 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
560 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
561 SPI_TRANSFER0_START | SPI_CADI_MODE0);
563 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
564 SPI_TRANSFER0_START | SPI_CDI_MODE0);
568 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
571 retval = rtsx_send_cmd(chip, 0, 100);
573 rtsx_clear_spi_error(chip);
574 spi_set_err_code(chip, SPI_HW_ERR);
579 buf = kmalloc(len, GFP_KERNEL);
584 retval = rtsx_read_ppbuf(chip, buf, len);
585 if (retval != STATUS_SUCCESS) {
586 spi_set_err_code(chip, SPI_READ_ERR);
591 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
592 scsi_set_resid(srb, 0);
597 return STATUS_SUCCESS;
600 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
603 unsigned int index = 0, offset = 0;
609 spi_set_err_code(chip, SPI_NO_ERR);
612 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
613 << 8) | srb->cmnd[6];
614 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
615 slow_read = srb->cmnd[9];
617 retval = spi_set_init_para(chip);
618 if (retval != STATUS_SUCCESS) {
619 spi_set_err_code(chip, SPI_HW_ERR);
623 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
629 u16 pagelen = SF_PAGE_LEN - (u8)addr;
636 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
638 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
641 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
643 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
645 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
647 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
648 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
650 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
652 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
654 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
656 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
657 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
660 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
662 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
665 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
666 SPI_TRANSFER0_START | SPI_CADI_MODE0);
667 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
668 SPI_TRANSFER0_END, SPI_TRANSFER0_END);
670 rtsx_send_cmd_no_wait(chip);
672 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
673 DMA_FROM_DEVICE, 10000);
676 rtsx_clear_spi_error(chip);
677 spi_set_err_code(chip, SPI_HW_ERR);
681 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
688 scsi_set_resid(srb, 0);
691 return STATUS_SUCCESS;
694 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
697 u8 ins, program_mode;
701 unsigned int index = 0, offset = 0;
703 spi_set_err_code(chip, SPI_NO_ERR);
706 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
707 << 8) | srb->cmnd[6];
708 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
709 program_mode = srb->cmnd[9];
711 retval = spi_set_init_para(chip);
712 if (retval != STATUS_SUCCESS) {
713 spi_set_err_code(chip, SPI_HW_ERR);
717 if (program_mode == BYTE_PROGRAM) {
718 buf = kmalloc(4, GFP_KERNEL);
724 retval = sf_enable_write(chip, SPI_WREN);
725 if (retval != STATUS_SUCCESS) {
730 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
735 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
736 0x01, PINGPONG_BUFFER);
737 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
739 sf_program(chip, ins, 1, addr, 1);
741 retval = rtsx_send_cmd(chip, 0, 100);
744 rtsx_clear_spi_error(chip);
745 spi_set_err_code(chip, SPI_HW_ERR);
749 retval = sf_polling_status(chip, 100);
750 if (retval != STATUS_SUCCESS) {
761 } else if (program_mode == AAI_PROGRAM) {
764 retval = sf_enable_write(chip, SPI_WREN);
765 if (retval != STATUS_SUCCESS) {
769 buf = kmalloc(4, GFP_KERNEL);
775 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
780 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
781 0x01, PINGPONG_BUFFER);
782 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
785 sf_program(chip, ins, 1, addr, 1);
788 sf_program(chip, ins, 0, 0, 1);
791 retval = rtsx_send_cmd(chip, 0, 100);
794 rtsx_clear_spi_error(chip);
795 spi_set_err_code(chip, SPI_HW_ERR);
799 retval = sf_polling_status(chip, 100);
800 if (retval != STATUS_SUCCESS) {
810 retval = sf_disable_write(chip, SPI_WRDI);
811 if (retval != STATUS_SUCCESS) {
815 retval = sf_polling_status(chip, 100);
816 if (retval != STATUS_SUCCESS) {
819 } else if (program_mode == PAGE_PROGRAM) {
820 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
826 u16 pagelen = SF_PAGE_LEN - (u8)addr;
831 retval = sf_enable_write(chip, SPI_WREN);
832 if (retval != STATUS_SUCCESS) {
839 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
840 sf_program(chip, ins, 1, addr, pagelen);
842 rtsx_send_cmd_no_wait(chip);
844 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
845 &offset, FROM_XFER_BUF);
847 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
851 rtsx_clear_spi_error(chip);
852 spi_set_err_code(chip, SPI_HW_ERR);
856 retval = sf_polling_status(chip, 100);
857 if (retval != STATUS_SUCCESS) {
868 spi_set_err_code(chip, SPI_INVALID_COMMAND);
872 return STATUS_SUCCESS;
875 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
881 spi_set_err_code(chip, SPI_NO_ERR);
884 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
885 << 8) | srb->cmnd[6];
886 erase_mode = srb->cmnd[9];
888 retval = spi_set_init_para(chip);
889 if (retval != STATUS_SUCCESS) {
890 spi_set_err_code(chip, SPI_HW_ERR);
894 if (erase_mode == PAGE_ERASE) {
895 retval = sf_enable_write(chip, SPI_WREN);
896 if (retval != STATUS_SUCCESS) {
900 retval = sf_erase(chip, ins, 1, addr);
901 if (retval != STATUS_SUCCESS) {
904 } else if (erase_mode == CHIP_ERASE) {
905 retval = sf_enable_write(chip, SPI_WREN);
906 if (retval != STATUS_SUCCESS) {
910 retval = sf_erase(chip, ins, 0, 0);
911 if (retval != STATUS_SUCCESS) {
915 spi_set_err_code(chip, SPI_INVALID_COMMAND);
919 return STATUS_SUCCESS;
922 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
925 u8 ins, status, ewsr;
928 status = srb->cmnd[4];
931 retval = spi_set_init_para(chip);
932 if (retval != STATUS_SUCCESS) {
933 spi_set_err_code(chip, SPI_HW_ERR);
937 retval = sf_enable_write(chip, ewsr);
938 if (retval != STATUS_SUCCESS) {
944 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
947 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
948 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
949 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
950 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
951 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
952 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
953 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
954 SPI_TRANSFER0_START | SPI_CDO_MODE0);
955 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
958 retval = rtsx_send_cmd(chip, 0, 100);
959 if (retval != STATUS_SUCCESS) {
960 rtsx_clear_spi_error(chip);
961 spi_set_err_code(chip, SPI_HW_ERR);
965 return STATUS_SUCCESS;