drivers/staging/rts5208/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "sd.h"
  31 #include "xd.h"
  32 #include "ms.h"
  33
  34 static void rtsx_calibration(struct rtsx_chip *chip)
  35 {
  36         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  37         wait_timeout(10);
  38         rtsx_write_phy_register(chip, 0x00, 0x0280);
  39         rtsx_write_phy_register(chip, 0x01, 0x7112);
  40         rtsx_write_phy_register(chip, 0x01, 0x7110);
  41         rtsx_write_phy_register(chip, 0x01, 0x7112);
  42         rtsx_write_phy_register(chip, 0x01, 0x7113);
  43         rtsx_write_phy_register(chip, 0x00, 0x0288);
  44 }
  45
  46 void rtsx_enable_card_int(struct rtsx_chip *chip)
  47 {
  48         u32 reg = rtsx_readl(chip, RTSX_BIER);
  49         int i;
  50
  51         for (i = 0; i <= chip->max_lun; i++) {
  52                 if (chip->lun2card[i] & XD_CARD)
  53                         reg |= XD_INT_EN;
  54                 if (chip->lun2card[i] & SD_CARD)
  55                         reg |= SD_INT_EN;
  56                 if (chip->lun2card[i] & MS_CARD)
  57                         reg |= MS_INT_EN;
  58         }
  59         if (chip->hw_bypass_sd)
  60                 reg &= ~((u32)SD_INT_EN);
  61
  62         rtsx_writel(chip, RTSX_BIER, reg);
  63 }
  64
  65 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  66 {
  67         u32 reg = 0;
  68 #ifndef DISABLE_CARD_INT
  69         int i;
  70 #endif
  71
  72         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  73
  74 #ifndef DISABLE_CARD_INT
  75         for (i = 0; i <= chip->max_lun; i++) {
  76                 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
  77                         i, chip->lun2card[i]);
  78
  79                 if (chip->lun2card[i] & XD_CARD)
  80                         reg |= XD_INT_EN;
  81                 if (chip->lun2card[i] & SD_CARD)
  82                         reg |= SD_INT_EN;
  83                 if (chip->lun2card[i] & MS_CARD)
  84                         reg |= MS_INT_EN;
  85         }
  86         if (chip->hw_bypass_sd)
  87                 reg &= ~((u32)SD_INT_EN);
  88 #endif
  89
  90         if (chip->ic_version >= IC_VER_C)
  91                 reg |= DELINK_INT_EN;
  92 #ifdef SUPPORT_OCP
  93         reg |= OC_INT_EN;
  94 #endif
  95         if (!chip->adma_mode)
  96                 reg |= DATA_DONE_INT_EN;
  97
  98         /* Enable Bus Interrupt */
  99         rtsx_writel(chip, RTSX_BIER, reg);
 100
 101         dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
 102 }
 103
 104 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 105 {
 106         rtsx_writel(chip, RTSX_BIER, 0);
 107 }
 108
 109 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 110 {
 111         int retval;
 112
 113         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 114                 if (chip->asic_code) {
 115                         retval = rtsx_write_register(chip, CARD_PULL_CTL5,
 116                                                      0xFF,
 117                                                      MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 118                         if (retval) {
 119                                 rtsx_trace(chip);
 120                                 return retval;
 121                         }
 122                 } else {
 123                         retval = rtsx_write_register(chip, FPGA_PULL_CTL,
 124                                                      0xFF,
 125                                                      FPGA_SD_PULL_CTL_EN);
 126                         if (retval) {
 127                                 rtsx_trace(chip);
 128                                 return retval;
 129                         }
 130                 }
 131                 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
 132                                              CARD_SHARE_48_SD);
 133                 if (retval) {
 134                         rtsx_trace(chip);
 135                         return retval;
 136                 }
 137
 138                 /* Enable SDIO internal clock */
 139                 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
 140                 if (retval) {
 141                         rtsx_trace(chip);
 142                         return retval;
 143                 }
 144
 145                 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
 146                                              SDIO_BUS_CTRL | SDIO_CD_CTRL);
 147                 if (retval) {
 148                         rtsx_trace(chip);
 149                         return retval;
 150                 }
 151
 152                 chip->sd_int = 1;
 153                 chip->sd_io = 1;
 154         } else {
 155                 chip->need_reset |= SD_CARD;
 156         }
 157
 158         return STATUS_SUCCESS;
 159 }
 160
 161 #ifdef HW_AUTO_SWITCH_SD_BUS
 162 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 163 {
 164         u8 tmp;
 165         bool sw_bypass_sd = false;
 166         int retval;
 167
 168         if (chip->driver_first_load) {
 169                 if (CHECK_PID(chip, 0x5288)) {
 170                         retval = rtsx_read_register(chip, 0xFE5A, &tmp);
 171                         if (retval) {
 172                                 rtsx_trace(chip);
 173                                 return retval;
 174                         }
 175                         if (tmp & 0x08)
 176                                 sw_bypass_sd = true;
 177                 } else if (CHECK_PID(chip, 0x5208)) {
 178                         retval = rtsx_read_register(chip, 0xFE70, &tmp);
 179                         if (retval) {
 180                                 rtsx_trace(chip);
 181                                 return retval;
 182                         }
 183                         if (tmp & 0x80)
 184                                 sw_bypass_sd = true;
 185                 }
 186         } else {
 187                 if (chip->sdio_in_charge)
 188                         sw_bypass_sd = true;
 189         }
 190         dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
 191                 chip->sdio_in_charge);
 192         dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
 193                 chip->driver_first_load);
 194         dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
 195                 sw_bypass_sd);
 196
 197         if (sw_bypass_sd) {
 198                 u8 cd_toggle_mask = 0;
 199
 200                 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
 201                 if (retval) {
 202                         rtsx_trace(chip);
 203                         return retval;
 204                 }
 205                 cd_toggle_mask = 0x08;
 206
 207                 if (tmp & cd_toggle_mask) {
 208                         /* Disable sdio_bus_auto_switch */
 209                         if (CHECK_PID(chip, 0x5288)) {
 210                                 retval = rtsx_write_register(chip, 0xFE5A,
 211                                                              0x08, 0x00);
 212                                 if (retval) {
 213                                         rtsx_trace(chip);
 214                                         return retval;
 215                                 }
 216                         } else if (CHECK_PID(chip, 0x5208)) {
 217                                 retval = rtsx_write_register(chip, 0xFE70,
 218                                                              0x80, 0x00);
 219                                 if (retval) {
 220                                         rtsx_trace(chip);
 221                                         return retval;
 222                                 }
 223                         }
 224
 225                         retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
 226                                                      tmp);
 227                         if (retval) {
 228                                 rtsx_trace(chip);
 229                                 return retval;
 230                         }
 231
 232                         chip->need_reset |= SD_CARD;
 233                 } else {
 234                         dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
 235
 236                         if (chip->asic_code) {
 237                                 retval = sd_pull_ctl_enable(chip);
 238                                 if (retval != STATUS_SUCCESS) {
 239                                         rtsx_trace(chip);
 240                                         return STATUS_FAIL;
 241                                 }
 242                         } else {
 243                                 retval = rtsx_write_register(chip,
 244                                                              FPGA_PULL_CTL,
 245                                                              FPGA_SD_PULL_CTL_BIT | 0x20,
 246                                                              0);
 247                                 if (retval) {
 248                                         rtsx_trace(chip);
 249                                         return retval;
 250                                 }
 251                         }
 252                         retval = card_share_mode(chip, SD_CARD);
 253                         if (retval != STATUS_SUCCESS) {
 254                                 rtsx_trace(chip);
 255                                 return STATUS_FAIL;
 256                         }
 257
 258                         /* Enable sdio_bus_auto_switch */
 259                         if (CHECK_PID(chip, 0x5288)) {
 260                                 retval = rtsx_write_register(chip, 0xFE5A,
 261                                                              0x08, 0x08);
 262                                 if (retval) {
 263                                         rtsx_trace(chip);
 264                                         return retval;
 265                                 }
 266                         } else if (CHECK_PID(chip, 0x5208)) {
 267                                 retval = rtsx_write_register(chip, 0xFE70,
 268                                                              0x80, 0x80);
 269                                 if (retval) {
 270                                         rtsx_trace(chip);
 271                                         return retval;
 272                                 }
 273                         }
 274
 275                         chip->chip_insert_with_sdio = 1;
 276                         chip->sd_io = 1;
 277                 }
 278         } else {
 279                 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
 280                 if (retval) {
 281                         rtsx_trace(chip);
 282                         return retval;
 283                 }
 284
 285                 chip->need_reset |= SD_CARD;
 286         }
 287
 288         return STATUS_SUCCESS;
 289 }
 290 #endif
 291
 292 static int rtsx_reset_aspm(struct rtsx_chip *chip)
 293 {
 294         int ret;
 295
 296         if (chip->dynamic_aspm) {
 297                 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
 298                         return STATUS_SUCCESS;
 299
 300                 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
 301                                         chip->aspm_l0s_l1_en);
 302                 if (ret != STATUS_SUCCESS) {
 303                         rtsx_trace(chip);
 304                         return STATUS_FAIL;
 305                 }
 306
 307                 return STATUS_SUCCESS;
 308         }
 309
 310         if (CHECK_PID(chip, 0x5208)) {
 311                 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 312                 if (ret) {
 313                         rtsx_trace(chip);
 314                         return ret;
 315                 }
 316         }
 317         ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 318         if (ret != STATUS_SUCCESS) {
 319                 rtsx_trace(chip);
 320                 return STATUS_FAIL;
 321         }
 322
 323         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 324         if (CHK_SDIO_EXIST(chip)) {
 325                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 326                 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
 327                                         0xC0, 0xFF, chip->aspm_l0s_l1_en);
 328                 if (ret != STATUS_SUCCESS) {
 329                         rtsx_trace(chip);
 330                         return STATUS_FAIL;
 331                 }
 332         }
 333
 334         chip->aspm_enabled = 1;
 335
 336         return STATUS_SUCCESS;
 337 }
 338
 339 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
 340 {
 341         int ret;
 342
 343         if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
 344                 rtsx_enable_bus_int(chip);
 345                 return STATUS_SUCCESS;
 346         }
 347
 348         if (chip->phy_debug_mode) {
 349                 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
 350                 if (ret) {
 351                         rtsx_trace(chip);
 352                         return ret;
 353                 }
 354                 rtsx_disable_bus_int(chip);
 355         } else {
 356                 rtsx_enable_bus_int(chip);
 357         }
 358
 359         if (chip->ic_version >= IC_VER_D) {
 360                 u16 reg;
 361
 362                 ret = rtsx_read_phy_register(chip, 0x00, &reg);
 363                 if (ret != STATUS_SUCCESS) {
 364                         rtsx_trace(chip);
 365                         return STATUS_FAIL;
 366                 }
 367
 368                 reg &= 0xFE7F;
 369                 reg |= 0x80;
 370                 ret = rtsx_write_phy_register(chip, 0x00, reg);
 371                 if (ret != STATUS_SUCCESS) {
 372                         rtsx_trace(chip);
 373                         return STATUS_FAIL;
 374                 }
 375
 376                 ret = rtsx_read_phy_register(chip, 0x1C, &reg);
 377                 if (ret != STATUS_SUCCESS) {
 378                         rtsx_trace(chip);
 379                         return STATUS_FAIL;
 380                 }
 381
 382                 reg &= 0xFFF7;
 383                 ret = rtsx_write_phy_register(chip, 0x1C, reg);
 384                 if (ret != STATUS_SUCCESS) {
 385                         rtsx_trace(chip);
 386                         return STATUS_FAIL;
 387                 }
 388         }
 389
 390         if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
 391                 rtsx_calibration(chip);
 392
 393         return STATUS_SUCCESS;
 394 }
 395
 396 int rtsx_reset_chip(struct rtsx_chip *chip)
 397 {
 398         int retval;
 399
 400         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 401
 402         rtsx_disable_aspm(chip);
 403
 404         retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 405         if (retval) {
 406                 rtsx_trace(chip);
 407                 return retval;
 408         }
 409
 410         /* Disable card clock */
 411         retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
 412         if (retval) {
 413                 rtsx_trace(chip);
 414                 return retval;
 415         }
 416
 417 #ifdef SUPPORT_OCP
 418         /* SSC power on, OCD power on */
 419         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 420                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
 421                 if (retval) {
 422                         rtsx_trace(chip);
 423                         return retval;
 424                 }
 425         } else {
 426                 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 427                                              MS_OC_POWER_DOWN);
 428                 if (retval) {
 429                         rtsx_trace(chip);
 430                         return retval;
 431                 }
 432         }
 433
 434         retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
 435                                      OCP_TIME_800);
 436         if (retval) {
 437                 rtsx_trace(chip);
 438                 return retval;
 439         }
 440         retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
 441                                      OCP_THD_244_946);
 442         if (retval) {
 443                 rtsx_trace(chip);
 444                 return retval;
 445         }
 446         retval = rtsx_write_register(chip, OCPCTL, 0xFF,
 447                                      CARD_OC_INT_EN | CARD_DETECT_EN);
 448         if (retval) {
 449                 rtsx_trace(chip);
 450                 return retval;
 451         }
 452 #else
 453         /* OC power down */
 454         retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
 455                                      OC_POWER_DOWN);
 456         if (retval) {
 457                 rtsx_trace(chip);
 458                 return retval;
 459         }
 460 #endif
 461
 462         if (!CHECK_PID(chip, 0x5288)) {
 463                 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 464                 if (retval) {
 465                         rtsx_trace(chip);
 466                         return retval;
 467                 }
 468         }
 469
 470         /* Turn off LED */
 471         retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
 472         if (retval) {
 473                 rtsx_trace(chip);
 474                 return retval;
 475         }
 476
 477         /* Reset delink mode */
 478         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
 479         if (retval) {
 480                 rtsx_trace(chip);
 481                 return retval;
 482         }
 483
 484         /* Card driving select */
 485         retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
 486                                      chip->card_drive_sel);
 487         if (retval) {
 488                 rtsx_trace(chip);
 489                 return retval;
 490         }
 491
 492 #ifdef LED_AUTO_BLINK
 493         retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
 494                                      LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 495         if (retval) {
 496                 rtsx_trace(chip);
 497                 return retval;
 498         }
 499 #endif
 500
 501         if (chip->asic_code) {
 502                 /* Enable SSC Clock */
 503                 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
 504                                              SSC_8X_EN | SSC_SEL_4M);
 505                 if (retval) {
 506                         rtsx_trace(chip);
 507                         return retval;
 508                 }
 509                 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
 510                 if (retval) {
 511                         rtsx_trace(chip);
 512                         return retval;
 513                 }
 514         }
 515
 516         /*
 517          * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 518          *    0xFE5B
 519          *    bit[1]    u_cd_rst_core_en        rst_value = 0
 520          *    bit[2]    u_force_rst_core_en     rst_value = 0
 521          *    bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 522          *    bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 523          */
 524         retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 525         if (retval) {
 526                 rtsx_trace(chip);
 527                 return retval;
 528         }
 529
 530         /* Enable ASPM */
 531         if (chip->aspm_l0s_l1_en) {
 532                 retval = rtsx_reset_aspm(chip);
 533                 if (retval != STATUS_SUCCESS) {
 534                         rtsx_trace(chip);
 535                         return STATUS_FAIL;
 536                 }
 537         } else {
 538                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 539                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 540                         if (retval != STATUS_SUCCESS) {
 541                                 rtsx_trace(chip);
 542                                 return STATUS_FAIL;
 543                         }
 544                 }
 545                 retval = rtsx_write_config_byte(chip, LCTLR,
 546                                                 chip->aspm_l0s_l1_en);
 547                 if (retval != STATUS_SUCCESS) {
 548                         rtsx_trace(chip);
 549                         return STATUS_FAIL;
 550                 }
 551         }
 552
 553         retval = rtsx_write_config_byte(chip, 0x81, 1);
 554         if (retval != STATUS_SUCCESS) {
 555                 rtsx_trace(chip);
 556                 return STATUS_FAIL;
 557         }
 558
 559         if (CHK_SDIO_EXIST(chip)) {
 560                 retval = rtsx_write_cfg_dw(chip,
 561                                            CHECK_PID(chip, 0x5288) ? 2 : 1,
 562                                            0xC0, 0xFF00, 0x0100);
 563
 564                 if (retval != STATUS_SUCCESS) {
 565                         rtsx_trace(chip);
 566                         return STATUS_FAIL;
 567                 }
 568         }
 569
 570         if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
 571                 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 572                 if (retval != STATUS_SUCCESS) {
 573                         rtsx_trace(chip);
 574                         return STATUS_FAIL;
 575                 }
 576
 577                 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 578                 if (retval != STATUS_SUCCESS) {
 579                         rtsx_trace(chip);
 580                         return STATUS_FAIL;
 581                 }
 582         }
 583
 584         retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
 585                                      LINK_RDY_INT);
 586         if (retval) {
 587                 rtsx_trace(chip);
 588                 return retval;
 589         }
 590
 591         retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 592         if (retval) {
 593                 rtsx_trace(chip);
 594                 return retval;
 595         }
 596
 597         retval = rtsx_enable_pcie_intr(chip);
 598         if (retval != STATUS_SUCCESS) {
 599                 rtsx_trace(chip);
 600                 return STATUS_FAIL;
 601         }
 602
 603         chip->need_reset = 0;
 604
 605         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 606
 607         if (chip->hw_bypass_sd)
 608                 goto nextcard;
 609         dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
 610                 chip->int_reg);
 611         if (chip->int_reg & SD_EXIST) {
 612 #ifdef HW_AUTO_SWITCH_SD_BUS
 613                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 614                         retval = rtsx_pre_handle_sdio_old(chip);
 615                 else
 616                         retval = rtsx_pre_handle_sdio_new(chip);
 617
 618                 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
 619                         (unsigned int)(chip->need_reset));
 620 #else  /* HW_AUTO_SWITCH_SD_BUS */
 621                 retval = rtsx_pre_handle_sdio_old(chip);
 622 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 623                 if (retval != STATUS_SUCCESS) {
 624                         rtsx_trace(chip);
 625                         return STATUS_FAIL;
 626                 }
 627
 628         } else {
 629                 chip->sd_io = 0;
 630                 retval = rtsx_write_register(chip, SDIO_CTRL,
 631                                              SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 632                 if (retval) {
 633                         rtsx_trace(chip);
 634                         return retval;
 635                 }
 636         }
 637
 638 nextcard:
 639         if (chip->int_reg & XD_EXIST)
 640                 chip->need_reset |= XD_CARD;
 641         if (chip->int_reg & MS_EXIST)
 642                 chip->need_reset |= MS_CARD;
 643         if (chip->int_reg & CARD_EXIST) {
 644                 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
 645                                              SSC_RSTB);
 646                 if (retval) {
 647                         rtsx_trace(chip);
 648                         return retval;
 649                 }
 650         }
 651
 652         dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
 653                 (unsigned int)(chip->need_reset));
 654
 655         retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
 656         if (retval) {
 657                 rtsx_trace(chip);
 658                 return retval;
 659         }
 660
 661         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 662                 /* Turn off main power when entering S3/S4 state */
 663                 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
 664                                              0x03);
 665                 if (retval) {
 666                         rtsx_trace(chip);
 667                         return retval;
 668                 }
 669         }
 670
 671         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 672                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
 673                 if (retval) {
 674                         rtsx_trace(chip);
 675                         return retval;
 676                 }
 677                 if (chip->aux_pwr_exist) {
 678                         retval = rtsx_write_register(chip, PME_FORCE_CTL,
 679                                                      0xFF, 0x33);
 680                         if (retval) {
 681                                 rtsx_trace(chip);
 682                                 return retval;
 683                         }
 684                 }
 685         } else {
 686                 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
 687                 if (retval) {
 688                         rtsx_trace(chip);
 689                         return retval;
 690                 }
 691                 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
 692                 if (retval) {
 693                         rtsx_trace(chip);
 694                         return retval;
 695                 }
 696         }
 697
 698         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
 699                 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
 700                 if (retval) {
 701                         rtsx_trace(chip);
 702                         return retval;
 703                 }
 704         }
 705
 706         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 707                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 708                 if (retval != STATUS_SUCCESS) {
 709                         rtsx_trace(chip);
 710                         return STATUS_FAIL;
 711                 }
 712         }
 713
 714         if (chip->ft2_fast_mode) {
 715                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 716                                              MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 717                 if (retval) {
 718                         rtsx_trace(chip);
 719                         return retval;
 720                 }
 721                 udelay(chip->pmos_pwr_on_interval);
 722                 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
 723                                              MS_POWER_ON | SD_POWER_ON);
 724                 if (retval) {
 725                         rtsx_trace(chip);
 726                         return retval;
 727                 }
 728
 729                 wait_timeout(200);
 730         }
 731
 732         /* Reset card */
 733         rtsx_reset_detected_cards(chip, 0);
 734
 735         chip->driver_first_load = 0;
 736
 737         return STATUS_SUCCESS;
 738 }
 739
 740 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 741 {
 742         bool fake_para = false;
 743         int i;
 744
 745         for (i = 0; i < 4; i++) {
 746                 u8 tmp = (u8)(sd_speed_prior >> (i * 8));
 747
 748                 if ((tmp < 0x01) || (tmp > 0x04)) {
 749                         fake_para = true;
 750                         break;
 751                 }
 752         }
 753
 754         return !fake_para;
 755 }
 756
 757 static inline int check_sd_current_prior(u32 sd_current_prior)
 758 {
 759         bool fake_para = false;
 760         int i;
 761
 762         for (i = 0; i < 4; i++) {
 763                 u8 tmp = (u8)(sd_current_prior >> (i * 8));
 764
 765                 if (tmp > 0x03) {
 766                         fake_para = true;
 767                         break;
 768                 }
 769         }
 770
 771         return !fake_para;
 772 }
 773
 774 static int rts5208_init(struct rtsx_chip *chip)
 775 {
 776         int retval;
 777         u16 reg = 0;
 778         u8 val = 0;
 779
 780         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 781         if (retval) {
 782                 rtsx_trace(chip);
 783                 return retval;
 784         }
 785         retval = rtsx_read_register(chip, CLK_SEL, &val);
 786         if (retval) {
 787                 rtsx_trace(chip);
 788                 return retval;
 789         }
 790         chip->asic_code = val == 0 ? 1 : 0;
 791
 792         if (chip->asic_code) {
 793                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 794                 if (retval != STATUS_SUCCESS) {
 795                         rtsx_trace(chip);
 796                         return STATUS_FAIL;
 797                 }
 798
 799                 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
 800                         reg);
 801                 chip->ic_version = (reg >> 4) & 0x07;
 802                 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
 803
 804         } else {
 805                 retval = rtsx_read_register(chip, 0xFE80, &val);
 806                 if (retval) {
 807                         rtsx_trace(chip);
 808                         return retval;
 809                 }
 810                 chip->ic_version = val;
 811                 chip->phy_debug_mode = 0;
 812         }
 813
 814         retval = rtsx_read_register(chip, PDINFO, &val);
 815         if (retval) {
 816                 rtsx_trace(chip);
 817                 return retval;
 818         }
 819         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 820         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 821
 822         retval = rtsx_read_register(chip, 0xFE50, &val);
 823         if (retval) {
 824                 rtsx_trace(chip);
 825                 return retval;
 826         }
 827         chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
 828
 829         rtsx_read_config_byte(chip, 0x0E, &val);
 830         if (val & 0x80)
 831                 SET_SDIO_EXIST(chip);
 832         else
 833                 CLR_SDIO_EXIST(chip);
 834
 835         if (chip->use_hw_setting) {
 836                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 837                 if (retval) {
 838                         rtsx_trace(chip);
 839                         return retval;
 840                 }
 841                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 842         }
 843
 844         return STATUS_SUCCESS;
 845 }
 846
 847 static int rts5288_init(struct rtsx_chip *chip)
 848 {
 849         int retval;
 850         u8 val = 0, max_func;
 851         u32 lval = 0;
 852
 853         retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
 854         if (retval) {
 855                 rtsx_trace(chip);
 856                 return retval;
 857         }
 858         retval = rtsx_read_register(chip, CLK_SEL, &val);
 859         if (retval) {
 860                 rtsx_trace(chip);
 861                 return retval;
 862         }
 863         chip->asic_code = val == 0 ? 1 : 0;
 864
 865         chip->ic_version = 0;
 866         chip->phy_debug_mode = 0;
 867
 868         retval = rtsx_read_register(chip, PDINFO, &val);
 869         if (retval) {
 870                 rtsx_trace(chip);
 871                 return retval;
 872         }
 873         dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
 874         chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
 875
 876         retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
 877         if (retval) {
 878                 rtsx_trace(chip);
 879                 return retval;
 880         }
 881         dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
 882         chip->baro_pkg = val & 0x04 ? QFN : LQFP;
 883
 884         retval = rtsx_read_register(chip, 0xFE5A, &val);
 885         if (retval) {
 886                 rtsx_trace(chip);
 887                 return retval;
 888         }
 889         chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
 890
 891         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 892         if (retval != STATUS_SUCCESS) {
 893                 rtsx_trace(chip);
 894                 return STATUS_FAIL;
 895         }
 896
 897         max_func = (u8)((lval >> 29) & 0x07);
 898         dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
 899         if (max_func == 0x02)
 900                 SET_SDIO_EXIST(chip);
 901         else
 902                 CLR_SDIO_EXIST(chip);
 903
 904         if (chip->use_hw_setting) {
 905                 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
 906                 if (retval) {
 907                         rtsx_trace(chip);
 908                         return retval;
 909                 }
 910                 chip->auto_delink_en = val & 0x80 ? 1 : 0;
 911
 912                 if (CHECK_BARO_PKG(chip, LQFP))
 913                         chip->lun_mode = SD_MS_1LUN;
 914                 else
 915                         chip->lun_mode = DEFAULT_SINGLE;
 916         }
 917
 918         return STATUS_SUCCESS;
 919 }
 920
 921 int rtsx_init_chip(struct rtsx_chip *chip)
 922 {
 923         struct sd_info *sd_card = &chip->sd_card;
 924         struct xd_info *xd_card = &chip->xd_card;
 925         struct ms_info *ms_card = &chip->ms_card;
 926         int retval;
 927         unsigned int i;
 928
 929         dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 930                 chip->vendor_id, chip->product_id);
 931
 932         chip->ic_version = 0;
 933
 934 #ifdef _MSG_TRACE
 935         chip->msg_idx = 0;
 936 #endif
 937
 938         memset(xd_card, 0, sizeof(struct xd_info));
 939         memset(sd_card, 0, sizeof(struct sd_info));
 940         memset(ms_card, 0, sizeof(struct ms_info));
 941
 942         chip->xd_reset_counter = 0;
 943         chip->sd_reset_counter = 0;
 944         chip->ms_reset_counter = 0;
 945
 946         chip->xd_show_cnt = MAX_SHOW_CNT;
 947         chip->sd_show_cnt = MAX_SHOW_CNT;
 948         chip->ms_show_cnt = MAX_SHOW_CNT;
 949
 950         chip->sd_io = 0;
 951         chip->auto_delink_cnt = 0;
 952         chip->auto_delink_allowed = 1;
 953         rtsx_set_stat(chip, RTSX_STAT_INIT);
 954
 955         chip->aspm_enabled = 0;
 956         chip->chip_insert_with_sdio = 0;
 957         chip->sdio_aspm = 0;
 958         chip->sdio_idle = 0;
 959         chip->sdio_counter = 0;
 960         chip->cur_card = 0;
 961         chip->phy_debug_mode = 0;
 962         chip->sdio_func_exist = 0;
 963         memset(chip->sdio_raw_data, 0, 12);
 964
 965         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 966                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 967                 chip->rw_fail_cnt[i] = 0;
 968         }
 969
 970         if (!check_sd_speed_prior(chip->sd_speed_prior))
 971                 chip->sd_speed_prior = 0x01040203;
 972
 973         dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
 974                 chip->sd_speed_prior);
 975
 976         if (!check_sd_current_prior(chip->sd_current_prior))
 977                 chip->sd_current_prior = 0x00010203;
 978
 979         dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
 980                 chip->sd_current_prior);
 981
 982         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 983                 chip->sd_ddr_tx_phase = 0;
 984
 985         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 986                 chip->mmc_ddr_tx_phase = 0;
 987
 988         retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
 989         if (retval) {
 990                 rtsx_trace(chip);
 991                 return retval;
 992         }
 993         wait_timeout(200);
 994         retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
 995         if (retval) {
 996                 rtsx_trace(chip);
 997                 return retval;
 998         }
 999         dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1000                 chip->use_hw_setting);
1001
1002         if (CHECK_PID(chip, 0x5208)) {
1003                 retval = rts5208_init(chip);
1004                 if (retval != STATUS_SUCCESS) {
1005                         rtsx_trace(chip);
1006                         return STATUS_FAIL;
1007                 }
1008
1009         } else if (CHECK_PID(chip, 0x5288)) {
1010                 retval = rts5288_init(chip);
1011                 if (retval != STATUS_SUCCESS) {
1012                         rtsx_trace(chip);
1013                         return STATUS_FAIL;
1014                 }
1015         }
1016
1017         if (chip->ss_en == 2)
1018                 chip->ss_en = 0;
1019
1020         dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1021         dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1022         dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1023                 chip->phy_debug_mode);
1024         dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1025                 chip->aux_pwr_exist);
1026         dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1027                 chip->sdio_func_exist);
1028         dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1029                 chip->hw_bypass_sd);
1030         dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1031                 chip->aspm_l0s_l1_en);
1032         dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1033         dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1034                 chip->auto_delink_en);
1035         dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1036         dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1037
1038         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1039                 chip->card2lun[SD_CARD] = 0;
1040                 chip->card2lun[MS_CARD] = 1;
1041                 chip->card2lun[XD_CARD] = 0xFF;
1042                 chip->lun2card[0] = SD_CARD;
1043                 chip->lun2card[1] = MS_CARD;
1044                 chip->max_lun = 1;
1045                 SET_SDIO_IGNORED(chip);
1046         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1047                 chip->card2lun[SD_CARD] = 0;
1048                 chip->card2lun[MS_CARD] = 0;
1049                 chip->card2lun[XD_CARD] = 0xFF;
1050                 chip->lun2card[0] = SD_CARD | MS_CARD;
1051                 chip->max_lun = 0;
1052         } else {
1053                 chip->card2lun[XD_CARD] = 0;
1054                 chip->card2lun[SD_CARD] = 0;
1055                 chip->card2lun[MS_CARD] = 0;
1056                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1057                 chip->max_lun = 0;
1058         }
1059
1060         retval = rtsx_reset_chip(chip);
1061         if (retval != STATUS_SUCCESS) {
1062                 rtsx_trace(chip);
1063                 return STATUS_FAIL;
1064         }
1065
1066         return STATUS_SUCCESS;
1067 }
1068
1069 void rtsx_release_chip(struct rtsx_chip *chip)
1070 {
1071         xd_free_l2p_tbl(chip);
1072         ms_free_l2p_tbl(chip);
1073         chip->card_exist = 0;
1074         chip->card_ready = 0;
1075 }
1076
1077 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1078 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1079 {
1080         if (chip->card_exist && chip->blink_led) {
1081                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1082                         chip->led_toggle_counter++;
1083                 } else {
1084                         chip->led_toggle_counter = 0;
1085                         toggle_gpio(chip, LED_GPIO);
1086                 }
1087         }
1088 }
1089 #endif
1090
1091 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1092 {
1093         bool reg_changed, maybe_support_aspm;
1094         u32 tmp = 0;
1095         u8 reg0 = 0, reg1 = 0;
1096
1097         maybe_support_aspm = false;
1098         reg_changed = false;
1099         rtsx_read_config_byte(chip, LCTLR, &reg0);
1100         if (chip->aspm_level[0] != reg0) {
1101                 reg_changed = true;
1102                 chip->aspm_level[0] = reg0;
1103         }
1104         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1105                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1106                 reg1 = (u8)tmp;
1107                 if (chip->aspm_level[1] != reg1) {
1108                         reg_changed = true;
1109                         chip->aspm_level[1] = reg1;
1110                 }
1111
1112                 if ((reg0 & 0x03) && (reg1 & 0x03))
1113                         maybe_support_aspm = true;
1114
1115         } else {
1116                 if (reg0 & 0x03)
1117                         maybe_support_aspm = true;
1118         }
1119
1120         if (reg_changed) {
1121                 if (maybe_support_aspm)
1122                         chip->aspm_l0s_l1_en = 0x03;
1123
1124                 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1125                         chip->aspm_level[0], chip->aspm_level[1]);
1126
1127                 if (chip->aspm_l0s_l1_en) {
1128                         chip->aspm_enabled = 1;
1129                 } else {
1130                         chip->aspm_enabled = 0;
1131                         chip->sdio_aspm = 0;
1132                 }
1133                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1134                                     0x30 | chip->aspm_level[0] |
1135                                     (chip->aspm_level[1] << 2));
1136         }
1137 }
1138
1139 static void rtsx_manage_ocp(struct rtsx_chip *chip)
1140 {
1141 #ifdef SUPPORT_OCP
1142         if (!chip->ocp_int)
1143                 return;
1144
1145         rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1146
1147         if (chip->card_exist & SD_CARD)
1148                 sd_power_off_card3v3(chip);
1149         else if (chip->card_exist & MS_CARD)
1150                 ms_power_off_card3v3(chip);
1151         else if (chip->card_exist & XD_CARD)
1152                 xd_power_off_card3v3(chip);
1153
1154         chip->ocp_int = 0;
1155 #endif
1156 }
1157
1158 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1159 {
1160 #ifdef SUPPORT_SD_LOCK
1161         struct sd_info *sd_card = &chip->sd_card;
1162         u8 val;
1163
1164         if (!sd_card->sd_erase_status)
1165                 return;
1166
1167         if (chip->card_exist & SD_CARD) {
1168                 rtsx_read_register(chip, 0xFD30, &val);
1169                 if (val & 0x02) {
1170                         sd_card->sd_erase_status = SD_NOT_ERASE;
1171                         sd_card->sd_lock_notify = 1;
1172                         chip->need_reinit |= SD_CARD;
1173                 }
1174         } else {
1175                 sd_card->sd_erase_status = SD_NOT_ERASE;
1176         }
1177 #endif
1178 }
1179
1180 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1181 {
1182         u32 val;
1183
1184         if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1185                 return false;
1186
1187         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1188                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1189                 if (val & 0x07)
1190                         return false;
1191         }
1192
1193         return true;
1194 }
1195
1196 static void rtsx_manage_ss(struct rtsx_chip *chip)
1197 {
1198         if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1199                 return;
1200
1201         if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1202                 chip->ss_counter = 0;
1203                 return;
1204         }
1205
1206         if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1207                 chip->ss_counter++;
1208         else
1209                 rtsx_exclusive_enter_ss(chip);
1210 }
1211
1212 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1213 {
1214         u8 data;
1215
1216         if (!CHECK_PID(chip, 0x5208))
1217                 return;
1218
1219         rtsx_monitor_aspm_config(chip);
1220
1221 #ifdef SUPPORT_SDIO_ASPM
1222         if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1223             !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1224                 return;
1225
1226         if (chip->sd_io) {
1227                 dynamic_configure_sdio_aspm(chip);
1228                 return;
1229         }
1230
1231         if (chip->sdio_aspm)
1232                 return;
1233
1234         dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1235         data = 0x30 | (chip->aspm_level[1] << 2);
1236         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1237         chip->sdio_aspm = 1;
1238 #endif
1239 }
1240
1241 static void rtsx_manage_idle(struct rtsx_chip *chip)
1242 {
1243         if (chip->idle_counter < IDLE_MAX_COUNT) {
1244                 chip->idle_counter++;
1245                 return;
1246         }
1247
1248         if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1249                 return;
1250
1251         dev_dbg(rtsx_dev(chip), "Idle state!\n");
1252         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1253
1254 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1255         chip->led_toggle_counter = 0;
1256 #endif
1257         rtsx_force_power_on(chip, SSC_PDCTL);
1258
1259         turn_off_led(chip, LED_GPIO);
1260
1261         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1262                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1263 }
1264
1265 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1266 {
1267 #ifdef SUPPORT_OCP
1268         u8 sd_oc, ms_oc;
1269
1270         sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1271         ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1272
1273         if (sd_oc || ms_oc)
1274                 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1275                         chip->ocp_stat);
1276
1277         if (sd_oc && (chip->card_exist & SD_CARD)) {
1278                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1279                 card_power_off(chip, SD_CARD);
1280                 chip->card_fail |= SD_CARD;
1281         }
1282
1283         if (ms_oc && (chip->card_exist & MS_CARD)) {
1284                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1285                 card_power_off(chip, MS_CARD);
1286                 chip->card_fail |= MS_CARD;
1287         }
1288 #endif
1289 }
1290
1291 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1292 {
1293 #ifdef SUPPORT_OCP
1294         if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1295                 return;
1296
1297         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1298                 chip->ocp_stat);
1299
1300         if (chip->card_exist & SD_CARD) {
1301                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1302                 chip->card_fail |= SD_CARD;
1303         } else if (chip->card_exist & MS_CARD) {
1304                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1305                 chip->card_fail |= MS_CARD;
1306         } else if (chip->card_exist & XD_CARD) {
1307                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1308                 chip->card_fail |= XD_CARD;
1309         }
1310         card_power_off(chip, SD_CARD);
1311 #endif
1312 }
1313
1314 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1315                                int stage3_cnt)
1316 {
1317         u8 val;
1318
1319         rtsx_set_stat(chip, RTSX_STAT_DELINK);
1320
1321         if (chip->asic_code && CHECK_PID(chip, 0x5208))
1322                 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1323
1324         if (chip->card_exist)
1325                 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1326         else
1327                 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1328
1329         if (enter_L1)
1330                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1331
1332         if (chip->card_exist)
1333                 val = 0x02;
1334         else
1335                 val = 0x0A;
1336
1337         rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1338
1339         if (enter_L1)
1340                 rtsx_enter_L1(chip);
1341
1342         if (chip->card_exist)
1343                 chip->auto_delink_cnt = stage3_cnt + 1;
1344 }
1345
1346 static void rtsx_delink_stage(struct rtsx_chip *chip)
1347 {
1348         int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1349         int enter_L1;
1350
1351         if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1352             chip->card_ready || chip->card_ejected || chip->sd_io) {
1353                 chip->auto_delink_cnt = 0;
1354                 return;
1355         }
1356
1357         enter_L1 = chip->auto_delink_in_L1 &&
1358                 (chip->aspm_l0s_l1_en || chip->ss_en);
1359
1360         delink_stage1_cnt = chip->delink_stage1_step;
1361         delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1362         delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1363
1364         if (chip->auto_delink_cnt > delink_stage3_cnt)
1365                 return;
1366
1367         if (chip->auto_delink_cnt == delink_stage1_cnt)
1368                 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1369
1370         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1371                 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1372
1373                 if (enter_L1)
1374                         rtsx_exit_L1(chip);
1375
1376                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1377                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1378
1379                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1380         }
1381
1382         chip->auto_delink_cnt++;
1383 }
1384
1385 void rtsx_polling_func(struct rtsx_chip *chip)
1386 {
1387         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1388                 return;
1389
1390         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1391                 goto delink_stage;
1392
1393         if (chip->polling_config) {
1394                 u8 val;
1395
1396                 rtsx_read_config_byte(chip, 0, &val);
1397         }
1398
1399         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1400                 return;
1401
1402         rtsx_manage_ocp(chip);
1403
1404         rtsx_manage_sd_lock(chip);
1405
1406         rtsx_init_cards(chip);
1407
1408         rtsx_manage_ss(chip);
1409
1410         rtsx_manage_aspm(chip);
1411
1412         rtsx_manage_idle(chip);
1413
1414         switch (rtsx_get_stat(chip)) {
1415         case RTSX_STAT_RUN:
1416 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1417                 rtsx_blink_led(chip);
1418 #endif
1419                 do_remaining_work(chip);
1420                 break;
1421
1422         case RTSX_STAT_IDLE:
1423                 if (chip->sd_io && !chip->sd_int)
1424                         try_to_switch_sdio_ctrl(chip);
1425
1426                 rtsx_enable_aspm(chip);
1427                 break;
1428
1429         default:
1430                 break;
1431         }
1432
1433         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1434                 rtsx_manage_2lun_mode(chip);
1435         else
1436                 rtsx_manage_1lun_mode(chip);
1437
1438 delink_stage:
1439         rtsx_delink_stage(chip);
1440 }
1441
1442 /**
1443  * rtsx_stop_cmd - stop command transfer and DMA transfer
1444  * @chip: Realtek's card reader chip
1445  * @card: flash card type
1446  *
1447  * Stop command transfer and DMA transfer.
1448  * This function is called in error handler.
1449  */
1450 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1451 {
1452         int i;
1453
1454         for (i = 0; i <= 8; i++) {
1455                 int addr = RTSX_HCBAR + i * 4;
1456                 u32 reg;
1457
1458                 reg = rtsx_readl(chip, addr);
1459                 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1460         }
1461         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1462         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1463
1464         for (i = 0; i < 16; i++) {
1465                 u16 addr = 0xFE20 + (u16)i;
1466                 u8 val;
1467
1468                 rtsx_read_register(chip, addr, &val);
1469                 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1470         }
1471
1472         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1473         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1474 }
1475
1476 #define MAX_RW_REG_CNT          1024
1477
1478 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1479 {
1480         int i;
1481         u32 val = 3 << 30;
1482
1483         val |= (u32)(addr & 0x3FFF) << 16;
1484         val |= (u32)mask << 8;
1485         val |= (u32)data;
1486
1487         rtsx_writel(chip, RTSX_HAIMR, val);
1488
1489         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1490                 val = rtsx_readl(chip, RTSX_HAIMR);
1491                 if ((val & (1 << 31)) == 0) {
1492                         if (data != (u8)val) {
1493                                 rtsx_trace(chip);
1494                                 return STATUS_FAIL;
1495                         }
1496
1497                         return STATUS_SUCCESS;
1498                 }
1499         }
1500
1501         rtsx_trace(chip);
1502         return STATUS_TIMEDOUT;
1503 }
1504
1505 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1506 {
1507         u32 val = 2 << 30;
1508         int i;
1509
1510         if (data)
1511                 *data = 0;
1512
1513         val |= (u32)(addr & 0x3FFF) << 16;
1514
1515         rtsx_writel(chip, RTSX_HAIMR, val);
1516
1517         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1518                 val = rtsx_readl(chip, RTSX_HAIMR);
1519                 if ((val & (1 << 31)) == 0)
1520                         break;
1521         }
1522
1523         if (i >= MAX_RW_REG_CNT) {
1524                 rtsx_trace(chip);
1525                 return STATUS_TIMEDOUT;
1526         }
1527
1528         if (data)
1529                 *data = (u8)(val & 0xFF);
1530
1531         return STATUS_SUCCESS;
1532 }
1533
1534 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1535                       u32 val)
1536 {
1537         int retval;
1538         u8 mode = 0, tmp;
1539         int i;
1540
1541         for (i = 0; i < 4; i++) {
1542                 if (mask & 0xFF) {
1543                         retval = rtsx_write_register(chip, CFGDATA0 + i,
1544                                                      0xFF,
1545                                                      (u8)(val & mask & 0xFF));
1546                         if (retval) {
1547                                 rtsx_trace(chip);
1548                                 return retval;
1549                         }
1550                         mode |= (1 << i);
1551                 }
1552                 mask >>= 8;
1553                 val >>= 8;
1554         }
1555
1556         if (mode) {
1557                 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1558                 if (retval) {
1559                         rtsx_trace(chip);
1560                         return retval;
1561                 }
1562                 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1563                                              (u8)(addr >> 8));
1564                 if (retval) {
1565                         rtsx_trace(chip);
1566                         return retval;
1567                 }
1568
1569                 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1570                                              0x80 | mode | ((func_no & 0x03) << 4));
1571                 if (retval) {
1572                         rtsx_trace(chip);
1573                         return retval;
1574                 }
1575
1576                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1577                         retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1578                         if (retval) {
1579                                 rtsx_trace(chip);
1580                                 return retval;
1581                         }
1582                         if ((tmp & 0x80) == 0)
1583                                 break;
1584                 }
1585         }
1586
1587         return STATUS_SUCCESS;
1588 }
1589
1590 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1591 {
1592         int retval;
1593         int i;
1594         u8 tmp;
1595         u32 data = 0;
1596
1597         retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1598         if (retval) {
1599                 rtsx_trace(chip);
1600                 return retval;
1601         }
1602         retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1603         if (retval) {
1604                 rtsx_trace(chip);
1605                 return retval;
1606         }
1607         retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1608                                      0x80 | ((func_no & 0x03) << 4));
1609         if (retval) {
1610                 rtsx_trace(chip);
1611                 return retval;
1612         }
1613
1614         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1615                 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1616                 if (retval) {
1617                         rtsx_trace(chip);
1618                         return retval;
1619                 }
1620                 if ((tmp & 0x80) == 0)
1621                         break;
1622         }
1623
1624         for (i = 0; i < 4; i++) {
1625                 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1626                 if (retval) {
1627                         rtsx_trace(chip);
1628                         return retval;
1629                 }
1630                 data |= (u32)tmp << (i * 8);
1631         }
1632
1633         if (val)
1634                 *val = data;
1635
1636         return STATUS_SUCCESS;
1637 }
1638
1639 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1640                        int len)
1641 {
1642         u32 *data, *mask;
1643         u16 offset = addr % 4;
1644         u16 aligned_addr = addr - offset;
1645         int dw_len, i, j;
1646         int retval;
1647
1648         if (!buf) {
1649                 rtsx_trace(chip);
1650                 return STATUS_NOMEM;
1651         }
1652
1653         if ((len + offset) % 4)
1654                 dw_len = (len + offset) / 4 + 1;
1655         else
1656                 dw_len = (len + offset) / 4;
1657
1658         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1659
1660         data = vzalloc(dw_len * 4);
1661         if (!data) {
1662                 rtsx_trace(chip);
1663                 return STATUS_NOMEM;
1664         }
1665
1666         mask = vzalloc(dw_len * 4);
1667         if (!mask) {
1668                 vfree(data);
1669                 rtsx_trace(chip);
1670                 return STATUS_NOMEM;
1671         }
1672
1673         j = 0;
1674         for (i = 0; i < len; i++) {
1675                 mask[j] |= 0xFF << (offset * 8);
1676                 data[j] |= buf[i] << (offset * 8);
1677                 if (++offset == 4) {
1678                         j++;
1679                         offset = 0;
1680                 }
1681         }
1682
1683         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1684                              dw_len * 4);
1685         print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1686                              dw_len * 4);
1687
1688         for (i = 0; i < dw_len; i++) {
1689                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1690                                            mask[i], data[i]);
1691                 if (retval != STATUS_SUCCESS) {
1692                         vfree(data);
1693                         vfree(mask);
1694                         rtsx_trace(chip);
1695                         return STATUS_FAIL;
1696                 }
1697         }
1698
1699         vfree(data);
1700         vfree(mask);
1701
1702         return STATUS_SUCCESS;
1703 }
1704
1705 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1706                       int len)
1707 {
1708         u32 *data;
1709         u16 offset = addr % 4;
1710         u16 aligned_addr = addr - offset;
1711         int dw_len, i, j;
1712         int retval;
1713
1714         if ((len + offset) % 4)
1715                 dw_len = (len + offset) / 4 + 1;
1716         else
1717                 dw_len = (len + offset) / 4;
1718
1719         dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1720
1721         data = vmalloc(dw_len * 4);
1722         if (!data) {
1723                 rtsx_trace(chip);
1724                 return STATUS_NOMEM;
1725         }
1726
1727         for (i = 0; i < dw_len; i++) {
1728                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1729                                           data + i);
1730                 if (retval != STATUS_SUCCESS) {
1731                         vfree(data);
1732                         rtsx_trace(chip);
1733                         return STATUS_FAIL;
1734                 }
1735         }
1736
1737         if (buf) {
1738                 j = 0;
1739
1740                 for (i = 0; i < len; i++) {
1741                         buf[i] = (u8)(data[j] >> (offset * 8));
1742                         if (++offset == 4) {
1743                                 j++;
1744                                 offset = 0;
1745                         }
1746                 }
1747         }
1748
1749         vfree(data);
1750
1751         return STATUS_SUCCESS;
1752 }
1753
1754 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1755 {
1756         int retval;
1757         bool finished = false;
1758         int i;
1759         u8 tmp;
1760
1761         retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1762         if (retval) {
1763                 rtsx_trace(chip);
1764                 return retval;
1765         }
1766         retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1767         if (retval) {
1768                 rtsx_trace(chip);
1769                 return retval;
1770         }
1771         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1772         if (retval) {
1773                 rtsx_trace(chip);
1774                 return retval;
1775         }
1776         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1777         if (retval) {
1778                 rtsx_trace(chip);
1779                 return retval;
1780         }
1781
1782         for (i = 0; i < 100000; i++) {
1783                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1784                 if (retval) {
1785                         rtsx_trace(chip);
1786                         return retval;
1787                 }
1788                 if (!(tmp & 0x80)) {
1789                         finished = true;
1790                         break;
1791                 }
1792         }
1793
1794         if (!finished) {
1795                 rtsx_trace(chip);
1796                 return STATUS_FAIL;
1797         }
1798
1799         return STATUS_SUCCESS;
1800 }
1801
1802 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1803 {
1804         int retval;
1805         bool finished = false;
1806         int i;
1807         u16 data = 0;
1808         u8 tmp;
1809
1810         retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1811         if (retval) {
1812                 rtsx_trace(chip);
1813                 return retval;
1814         }
1815         retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1816         if (retval) {
1817                 rtsx_trace(chip);
1818                 return retval;
1819         }
1820
1821         for (i = 0; i < 100000; i++) {
1822                 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1823                 if (retval) {
1824                         rtsx_trace(chip);
1825                         return retval;
1826                 }
1827                 if (!(tmp & 0x80)) {
1828                         finished = true;
1829                         break;
1830                 }
1831         }
1832
1833         if (!finished) {
1834                 rtsx_trace(chip);
1835                 return STATUS_FAIL;
1836         }
1837
1838         retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1839         if (retval) {
1840                 rtsx_trace(chip);
1841                 return retval;
1842         }
1843         data = tmp;
1844         retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1845         if (retval) {
1846                 rtsx_trace(chip);
1847                 return retval;
1848         }
1849         data |= (u16)tmp << 8;
1850
1851         if (val)
1852                 *val = data;
1853
1854         return STATUS_SUCCESS;
1855 }
1856
1857 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1858 {
1859         int retval;
1860         int i;
1861         u8 data = 0;
1862
1863         retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1864         if (retval) {
1865                 rtsx_trace(chip);
1866                 return retval;
1867         }
1868
1869         for (i = 0; i < 100; i++) {
1870                 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1871                 if (retval) {
1872                         rtsx_trace(chip);
1873                         return retval;
1874                 }
1875                 if (!(data & 0x80))
1876                         break;
1877                 udelay(1);
1878         }
1879
1880         if (data & 0x80) {
1881                 rtsx_trace(chip);
1882                 return STATUS_TIMEDOUT;
1883         }
1884
1885         retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1886         if (retval) {
1887                 rtsx_trace(chip);
1888                 return retval;
1889         }
1890         if (val)
1891                 *val = data;
1892
1893         return STATUS_SUCCESS;
1894 }
1895
1896 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1897 {
1898         int retval;
1899         int i, j;
1900         u8 data = 0, tmp = 0xFF;
1901
1902         for (i = 0; i < 8; i++) {
1903                 if (val & (u8)(1 << i))
1904                         continue;
1905
1906                 tmp &= (~(u8)(1 << i));
1907                 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1908
1909                 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1910                 if (retval) {
1911                         rtsx_trace(chip);
1912                         return retval;
1913                 }
1914                 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1915                                              0xA0 | addr);
1916                 if (retval) {
1917                         rtsx_trace(chip);
1918                         return retval;
1919                 }
1920
1921                 for (j = 0; j < 100; j++) {
1922                         retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1923                         if (retval) {
1924                                 rtsx_trace(chip);
1925                                 return retval;
1926                         }
1927                         if (!(data & 0x80))
1928                                 break;
1929                         wait_timeout(3);
1930                 }
1931
1932                 if (data & 0x80) {
1933                         rtsx_trace(chip);
1934                         return STATUS_TIMEDOUT;
1935                 }
1936
1937                 wait_timeout(5);
1938         }
1939
1940         return STATUS_SUCCESS;
1941 }
1942
1943 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1944 {
1945         int retval;
1946         u16 value;
1947
1948         retval = rtsx_read_phy_register(chip, reg, &value);
1949         if (retval != STATUS_SUCCESS) {
1950                 rtsx_trace(chip);
1951                 return STATUS_FAIL;
1952         }
1953
1954         if (value & (1 << bit)) {
1955                 value &= ~(1 << bit);
1956                 retval = rtsx_write_phy_register(chip, reg, value);
1957                 if (retval != STATUS_SUCCESS) {
1958                         rtsx_trace(chip);
1959                         return STATUS_FAIL;
1960                 }
1961         }
1962
1963         return STATUS_SUCCESS;
1964 }
1965
1966 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1967 {
1968         int retval;
1969         u16 value;
1970
1971         retval = rtsx_read_phy_register(chip, reg, &value);
1972         if (retval != STATUS_SUCCESS) {
1973                 rtsx_trace(chip);
1974                 return STATUS_FAIL;
1975         }
1976
1977         if ((value & (1 << bit)) == 0) {
1978                 value |= (1 << bit);
1979                 retval = rtsx_write_phy_register(chip, reg, value);
1980                 if (retval != STATUS_SUCCESS) {
1981                         rtsx_trace(chip);
1982                         return STATUS_FAIL;
1983                 }
1984         }
1985
1986         return STATUS_SUCCESS;
1987 }
1988
1989 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1990 {
1991         u32 ultmp;
1992
1993         dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1994                 chip->product_id, dstate);
1995
1996         if (CHK_SDIO_EXIST(chip)) {
1997                 u8 func_no;
1998
1999                 if (CHECK_PID(chip, 0x5288))
2000                         func_no = 2;
2001                 else
2002                         func_no = 1;
2003
2004                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2005                 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2006                         (int)func_no, ultmp);
2007                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2008         }
2009
2010         rtsx_write_config_byte(chip, 0x44, dstate);
2011         rtsx_write_config_byte(chip, 0x45, 0);
2012 }
2013
2014 void rtsx_enter_L1(struct rtsx_chip *chip)
2015 {
2016         rtsx_handle_pm_dstate(chip, 2);
2017 }
2018
2019 void rtsx_exit_L1(struct rtsx_chip *chip)
2020 {
2021         rtsx_write_config_byte(chip, 0x44, 0);
2022         rtsx_write_config_byte(chip, 0x45, 0);
2023 }
2024
2025 void rtsx_enter_ss(struct rtsx_chip *chip)
2026 {
2027         dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2028
2029         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2030
2031         if (chip->power_down_in_ss) {
2032                 rtsx_power_off_card(chip);
2033                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2034         }
2035
2036         if (CHK_SDIO_EXIST(chip))
2037                 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2038                                   0xC0, 0xFF00, 0x0100);
2039
2040         if (chip->auto_delink_en) {
2041                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2042         } else {
2043                 if (!chip->phy_debug_mode) {
2044                         u32 tmp;
2045
2046                         tmp = rtsx_readl(chip, RTSX_BIER);
2047                         tmp |= CARD_INT;
2048                         rtsx_writel(chip, RTSX_BIER, tmp);
2049                 }
2050
2051                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2052         }
2053
2054         rtsx_enter_L1(chip);
2055
2056         RTSX_CLR_DELINK(chip);
2057         rtsx_set_stat(chip, RTSX_STAT_SS);
2058 }
2059
2060 void rtsx_exit_ss(struct rtsx_chip *chip)
2061 {
2062         dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2063
2064         rtsx_exit_L1(chip);
2065
2066         if (chip->power_down_in_ss) {
2067                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2068                 udelay(1000);
2069         }
2070
2071         if (RTSX_TST_DELINK(chip)) {
2072                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2073                 rtsx_reinit_cards(chip, 1);
2074                 RTSX_CLR_DELINK(chip);
2075         } else if (chip->power_down_in_ss) {
2076                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2077                 rtsx_reinit_cards(chip, 0);
2078         }
2079 }
2080
2081 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2082 {
2083         u32 status, int_enable;
2084         bool exit_ss = false;
2085 #ifdef SUPPORT_OCP
2086         u32 ocp_int = 0;
2087
2088         ocp_int = OC_INT;
2089 #endif
2090
2091         if (chip->ss_en) {
2092                 chip->ss_counter = 0;
2093                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2094                         exit_ss = true;
2095                         rtsx_exit_L1(chip);
2096                         rtsx_set_stat(chip, RTSX_STAT_RUN);
2097                 }
2098         }
2099
2100         int_enable = rtsx_readl(chip, RTSX_BIER);
2101         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2102
2103         if (((chip->int_reg & int_enable) == 0) ||
2104             (chip->int_reg == 0xFFFFFFFF))
2105                 return STATUS_FAIL;
2106
2107         status = chip->int_reg &= (int_enable | 0x7FFFFF);
2108
2109         if (status & CARD_INT) {
2110                 chip->auto_delink_cnt = 0;
2111
2112                 if (status & SD_INT) {
2113                         if (status & SD_EXIST) {
2114                                 set_bit(SD_NR, &chip->need_reset);
2115                         } else {
2116                                 set_bit(SD_NR, &chip->need_release);
2117                                 chip->sd_reset_counter = 0;
2118                                 chip->sd_show_cnt = 0;
2119                                 clear_bit(SD_NR, &chip->need_reset);
2120                         }
2121                 } else {
2122                         /*
2123                          * If multi-luns, it's possible that
2124                          * when plugging/unplugging one card
2125                          * there is another card which still
2126                          * exists in the slot. In this case,
2127                          * all existed cards should be reset.
2128                          */
2129                         if (exit_ss && (status & SD_EXIST))
2130                                 set_bit(SD_NR, &chip->need_reinit);
2131                 }
2132                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2133                         if (status & XD_INT) {
2134                                 if (status & XD_EXIST) {
2135                                         set_bit(XD_NR, &chip->need_reset);
2136                                 } else {
2137                                         set_bit(XD_NR, &chip->need_release);
2138                                         chip->xd_reset_counter = 0;
2139                                         chip->xd_show_cnt = 0;
2140                                         clear_bit(XD_NR, &chip->need_reset);
2141                                 }
2142                         } else {
2143                                 if (exit_ss && (status & XD_EXIST))
2144                                         set_bit(XD_NR, &chip->need_reinit);
2145                         }
2146                 }
2147                 if (status & MS_INT) {
2148                         if (status & MS_EXIST) {
2149                                 set_bit(MS_NR, &chip->need_reset);
2150                         } else {
2151                                 set_bit(MS_NR, &chip->need_release);
2152                                 chip->ms_reset_counter = 0;
2153                                 chip->ms_show_cnt = 0;
2154                                 clear_bit(MS_NR, &chip->need_reset);
2155                         }
2156                 } else {
2157                         if (exit_ss && (status & MS_EXIST))
2158                                 set_bit(MS_NR, &chip->need_reinit);
2159                 }
2160         }
2161
2162 #ifdef SUPPORT_OCP
2163         chip->ocp_int = ocp_int & status;
2164 #endif
2165
2166         if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2167                 chip->int_reg &= ~(u32)DATA_DONE_INT;
2168
2169         return STATUS_SUCCESS;
2170 }
2171
2172 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2173 {
2174         int retval;
2175
2176         dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2177
2178         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2179
2180         retval = rtsx_force_power_on(chip, SSC_PDCTL);
2181         if (retval != STATUS_SUCCESS)
2182                 return;
2183
2184         rtsx_release_cards(chip);
2185         rtsx_disable_bus_int(chip);
2186         turn_off_led(chip, LED_GPIO);
2187
2188 #ifdef HW_AUTO_SWITCH_SD_BUS
2189         if (chip->sd_io) {
2190                 chip->sdio_in_charge = 1;
2191                 if (CHECK_PID(chip, 0x5208)) {
2192                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2193                         /* Enable sdio_bus_auto_switch */
2194                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2195                 } else if (CHECK_PID(chip, 0x5288)) {
2196                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2197                         /* Enable sdio_bus_auto_switch */
2198                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2199                 }
2200         }
2201 #endif
2202
2203         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2204                 /* u_force_clkreq_0 */
2205                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2206         }
2207
2208         if (pm_stat == PM_S1) {
2209                 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2210                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2211                                     HOST_ENTER_S1);
2212         } else if (pm_stat == PM_S3) {
2213                 if (chip->s3_pwr_off_delay > 0)
2214                         wait_timeout(chip->s3_pwr_off_delay);
2215
2216                 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2217                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2218                                     HOST_ENTER_S3);
2219         }
2220
2221         if (chip->do_delink_before_power_down && chip->auto_delink_en)
2222                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2223
2224         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2225
2226         chip->cur_clk = 0;
2227         chip->cur_card = 0;
2228         chip->card_exist = 0;
2229 }
2230
2231 void rtsx_enable_aspm(struct rtsx_chip *chip)
2232 {
2233         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2234                 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2235                 chip->aspm_enabled = 1;
2236
2237                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2238                         rtsx_write_phy_register(chip, 0x07, 0);
2239                 if (CHECK_PID(chip, 0x5208)) {
2240                         rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2241                                             0x30 | chip->aspm_level[0]);
2242                 } else {
2243                         rtsx_write_config_byte(chip, LCTLR,
2244                                                chip->aspm_l0s_l1_en);
2245                 }
2246
2247                 if (CHK_SDIO_EXIST(chip)) {
2248                         u16 val = chip->aspm_l0s_l1_en | 0x0100;
2249
2250                         rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2251                                           0xC0, 0xFFF, val);
2252                 }
2253         }
2254 }
2255
2256 void rtsx_disable_aspm(struct rtsx_chip *chip)
2257 {
2258         if (CHECK_PID(chip, 0x5208))
2259                 rtsx_monitor_aspm_config(chip);
2260
2261         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2262                 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2263                 chip->aspm_enabled = 0;
2264
2265                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2266                         rtsx_write_phy_register(chip, 0x07, 0x0129);
2267                 if (CHECK_PID(chip, 0x5208))
2268                         rtsx_write_register(chip, ASPM_FORCE_CTL,
2269                                             0xF3, 0x30);
2270                 else
2271                         rtsx_write_config_byte(chip, LCTLR, 0x00);
2272
2273                 wait_timeout(1);
2274         }
2275 }
2276
2277 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2278 {
2279         int retval;
2280         int i, j;
2281         u16 reg_addr;
2282         u8 *ptr;
2283
2284         if (!buf) {
2285                 rtsx_trace(chip);
2286                 return STATUS_ERROR;
2287         }
2288
2289         ptr = buf;
2290         reg_addr = PPBUF_BASE2;
2291         for (i = 0; i < buf_len / 256; i++) {
2292                 rtsx_init_cmd(chip);
2293
2294                 for (j = 0; j < 256; j++)
2295                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2296
2297                 retval = rtsx_send_cmd(chip, 0, 250);
2298                 if (retval < 0) {
2299                         rtsx_trace(chip);
2300                         return STATUS_FAIL;
2301                 }
2302
2303                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2304                 ptr += 256;
2305         }
2306
2307         if (buf_len % 256) {
2308                 rtsx_init_cmd(chip);
2309
2310                 for (j = 0; j < buf_len % 256; j++)
2311                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2312
2313                 retval = rtsx_send_cmd(chip, 0, 250);
2314                 if (retval < 0) {
2315                         rtsx_trace(chip);
2316                         return STATUS_FAIL;
2317                 }
2318         }
2319
2320         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256);
2321
2322         return STATUS_SUCCESS;
2323 }
2324
2325 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2326 {
2327         int retval;
2328         int i, j;
2329         u16 reg_addr;
2330         u8 *ptr;
2331
2332         if (!buf) {
2333                 rtsx_trace(chip);
2334                 return STATUS_ERROR;
2335         }
2336
2337         ptr = buf;
2338         reg_addr = PPBUF_BASE2;
2339         for (i = 0; i < buf_len / 256; i++) {
2340                 rtsx_init_cmd(chip);
2341
2342                 for (j = 0; j < 256; j++) {
2343                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2344                                      *ptr);
2345                         ptr++;
2346                 }
2347
2348                 retval = rtsx_send_cmd(chip, 0, 250);
2349                 if (retval < 0) {
2350                         rtsx_trace(chip);
2351                         return STATUS_FAIL;
2352                 }
2353         }
2354
2355         if (buf_len % 256) {
2356                 rtsx_init_cmd(chip);
2357
2358                 for (j = 0; j < buf_len % 256; j++) {
2359                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2360                                      *ptr);
2361                         ptr++;
2362                 }
2363
2364                 retval = rtsx_send_cmd(chip, 0, 250);
2365                 if (retval < 0) {
2366                         rtsx_trace(chip);
2367                         return STATUS_FAIL;
2368                 }
2369         }
2370
2371         return STATUS_SUCCESS;
2372 }
2373
2374 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2375 {
2376         if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2377                 rtsx_trace(chip);
2378                 return STATUS_FAIL;
2379         }
2380
2381         return STATUS_SUCCESS;
2382 }
2383
2384 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2385 {
2386         int retval;
2387         u8 mask = 0;
2388
2389         if (ctl & SSC_PDCTL)
2390                 mask |= SSC_POWER_DOWN;
2391
2392 #ifdef SUPPORT_OCP
2393         if (ctl & OC_PDCTL) {
2394                 mask |= SD_OC_POWER_DOWN;
2395                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2396                         mask |= MS_OC_POWER_DOWN;
2397         }
2398 #endif
2399
2400         if (mask) {
2401                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2402                 if (retval != STATUS_SUCCESS) {
2403                         rtsx_trace(chip);
2404                         return STATUS_FAIL;
2405                 }
2406
2407                 if (CHECK_PID(chip, 0x5288))
2408                         wait_timeout(200);
2409         }
2410
2411         return STATUS_SUCCESS;
2412 }
2413
2414 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2415 {
2416         int retval;
2417         u8 mask = 0, val = 0;
2418
2419         if (ctl & SSC_PDCTL)
2420                 mask |= SSC_POWER_DOWN;
2421
2422 #ifdef SUPPORT_OCP
2423         if (ctl & OC_PDCTL) {
2424                 mask |= SD_OC_POWER_DOWN;
2425                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2426                         mask |= MS_OC_POWER_DOWN;
2427         }
2428 #endif
2429
2430         if (mask) {
2431                 val = mask;
2432                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2433                 if (retval != STATUS_SUCCESS) {
2434                         rtsx_trace(chip);
2435                         return STATUS_FAIL;
2436                 }
2437         }
2438
2439         return STATUS_SUCCESS;
2440 }