1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/vmalloc.h>
34 static void rtsx_calibration(struct rtsx_chip *chip)
36 rtsx_write_phy_register(chip, 0x1B, 0x135E);
38 rtsx_write_phy_register(chip, 0x00, 0x0280);
39 rtsx_write_phy_register(chip, 0x01, 0x7112);
40 rtsx_write_phy_register(chip, 0x01, 0x7110);
41 rtsx_write_phy_register(chip, 0x01, 0x7112);
42 rtsx_write_phy_register(chip, 0x01, 0x7113);
43 rtsx_write_phy_register(chip, 0x00, 0x0288);
46 void rtsx_enable_card_int(struct rtsx_chip *chip)
48 u32 reg = rtsx_readl(chip, RTSX_BIER);
51 for (i = 0; i <= chip->max_lun; i++) {
52 if (chip->lun2card[i] & XD_CARD)
54 if (chip->lun2card[i] & SD_CARD)
56 if (chip->lun2card[i] & MS_CARD)
59 if (chip->hw_bypass_sd)
60 reg &= ~((u32)SD_INT_EN);
62 rtsx_writel(chip, RTSX_BIER, reg);
65 void rtsx_enable_bus_int(struct rtsx_chip *chip)
68 #ifndef DISABLE_CARD_INT
72 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
74 #ifndef DISABLE_CARD_INT
75 for (i = 0; i <= chip->max_lun; i++) {
76 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
77 i, chip->lun2card[i]);
79 if (chip->lun2card[i] & XD_CARD)
81 if (chip->lun2card[i] & SD_CARD)
83 if (chip->lun2card[i] & MS_CARD)
86 if (chip->hw_bypass_sd)
87 reg &= ~((u32)SD_INT_EN);
90 if (chip->ic_version >= IC_VER_C)
96 reg |= DATA_DONE_INT_EN;
98 /* Enable Bus Interrupt */
99 rtsx_writel(chip, RTSX_BIER, reg);
101 dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
104 void rtsx_disable_bus_int(struct rtsx_chip *chip)
106 rtsx_writel(chip, RTSX_BIER, 0);
109 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
113 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
114 if (chip->asic_code) {
115 retval = rtsx_write_register(chip, CARD_PULL_CTL5,
117 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
123 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
125 FPGA_SD_PULL_CTL_EN);
131 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
138 /* Enable SDIO internal clock */
139 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
145 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
146 SDIO_BUS_CTRL | SDIO_CD_CTRL);
155 chip->need_reset |= SD_CARD;
158 return STATUS_SUCCESS;
161 #ifdef HW_AUTO_SWITCH_SD_BUS
162 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
165 bool sw_bypass_sd = false;
168 if (chip->driver_first_load) {
169 if (CHECK_PID(chip, 0x5288)) {
170 retval = rtsx_read_register(chip, 0xFE5A, &tmp);
177 } else if (CHECK_PID(chip, 0x5208)) {
178 retval = rtsx_read_register(chip, 0xFE70, &tmp);
187 if (chip->sdio_in_charge)
190 dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
191 chip->sdio_in_charge);
192 dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
193 chip->driver_first_load);
194 dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
198 u8 cd_toggle_mask = 0;
200 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
205 cd_toggle_mask = 0x08;
207 if (tmp & cd_toggle_mask) {
208 /* Disable sdio_bus_auto_switch */
209 if (CHECK_PID(chip, 0x5288)) {
210 retval = rtsx_write_register(chip, 0xFE5A,
216 } else if (CHECK_PID(chip, 0x5208)) {
217 retval = rtsx_write_register(chip, 0xFE70,
225 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
232 chip->need_reset |= SD_CARD;
234 dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
236 if (chip->asic_code) {
237 retval = sd_pull_ctl_enable(chip);
238 if (retval != STATUS_SUCCESS) {
243 retval = rtsx_write_register(chip,
245 FPGA_SD_PULL_CTL_BIT | 0x20,
252 retval = card_share_mode(chip, SD_CARD);
253 if (retval != STATUS_SUCCESS) {
258 /* Enable sdio_bus_auto_switch */
259 if (CHECK_PID(chip, 0x5288)) {
260 retval = rtsx_write_register(chip, 0xFE5A,
266 } else if (CHECK_PID(chip, 0x5208)) {
267 retval = rtsx_write_register(chip, 0xFE70,
275 chip->chip_insert_with_sdio = 1;
279 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
285 chip->need_reset |= SD_CARD;
288 return STATUS_SUCCESS;
292 static int rtsx_reset_aspm(struct rtsx_chip *chip)
296 if (chip->dynamic_aspm) {
297 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
298 return STATUS_SUCCESS;
300 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
301 chip->aspm_l0s_l1_en);
302 if (ret != STATUS_SUCCESS) {
307 return STATUS_SUCCESS;
310 if (CHECK_PID(chip, 0x5208)) {
311 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
317 ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
318 if (ret != STATUS_SUCCESS) {
323 chip->aspm_level[0] = chip->aspm_l0s_l1_en;
324 if (CHK_SDIO_EXIST(chip)) {
325 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
326 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
327 0xC0, 0xFF, chip->aspm_l0s_l1_en);
328 if (ret != STATUS_SUCCESS) {
334 chip->aspm_enabled = 1;
336 return STATUS_SUCCESS;
339 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
343 if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
344 rtsx_enable_bus_int(chip);
345 return STATUS_SUCCESS;
348 if (chip->phy_debug_mode) {
349 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
354 rtsx_disable_bus_int(chip);
356 rtsx_enable_bus_int(chip);
359 if (chip->ic_version >= IC_VER_D) {
362 ret = rtsx_read_phy_register(chip, 0x00, ®);
363 if (ret != STATUS_SUCCESS) {
370 ret = rtsx_write_phy_register(chip, 0x00, reg);
371 if (ret != STATUS_SUCCESS) {
376 ret = rtsx_read_phy_register(chip, 0x1C, ®);
377 if (ret != STATUS_SUCCESS) {
383 ret = rtsx_write_phy_register(chip, 0x1C, reg);
384 if (ret != STATUS_SUCCESS) {
390 if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
391 rtsx_calibration(chip);
393 return STATUS_SUCCESS;
396 int rtsx_reset_chip(struct rtsx_chip *chip)
400 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
402 rtsx_disable_aspm(chip);
404 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
410 /* Disable card clock */
411 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
418 /* SSC power on, OCD power on */
419 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
420 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
426 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
434 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
440 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
446 retval = rtsx_write_register(chip, OCPCTL, 0xFF,
447 CARD_OC_INT_EN | CARD_DETECT_EN);
454 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
462 if (!CHECK_PID(chip, 0x5288)) {
463 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
471 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
477 /* Reset delink mode */
478 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
484 /* Card driving select */
485 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
486 chip->card_drive_sel);
492 #ifdef LED_AUTO_BLINK
493 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
494 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
501 if (chip->asic_code) {
502 /* Enable SSC Clock */
503 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
504 SSC_8X_EN | SSC_SEL_4M);
509 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
517 * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
519 * bit[1] u_cd_rst_core_en rst_value = 0
520 * bit[2] u_force_rst_core_en rst_value = 0
521 * bit[5] u_mac_phy_rst_n_dbg rst_value = 1
522 * bit[4] u_non_sticky_rst_n_dbg rst_value = 0
524 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
531 if (chip->aspm_l0s_l1_en) {
532 retval = rtsx_reset_aspm(chip);
533 if (retval != STATUS_SUCCESS) {
538 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
539 retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
540 if (retval != STATUS_SUCCESS) {
545 retval = rtsx_write_config_byte(chip, LCTLR,
546 chip->aspm_l0s_l1_en);
547 if (retval != STATUS_SUCCESS) {
553 retval = rtsx_write_config_byte(chip, 0x81, 1);
554 if (retval != STATUS_SUCCESS) {
559 if (CHK_SDIO_EXIST(chip)) {
560 retval = rtsx_write_cfg_dw(chip,
561 CHECK_PID(chip, 0x5288) ? 2 : 1,
562 0xC0, 0xFF00, 0x0100);
564 if (retval != STATUS_SUCCESS) {
570 if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
571 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
572 if (retval != STATUS_SUCCESS) {
577 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
578 if (retval != STATUS_SUCCESS) {
584 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
591 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
597 retval = rtsx_enable_pcie_intr(chip);
598 if (retval != STATUS_SUCCESS) {
603 chip->need_reset = 0;
605 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
607 if (chip->hw_bypass_sd)
609 dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
611 if (chip->int_reg & SD_EXIST) {
612 #ifdef HW_AUTO_SWITCH_SD_BUS
613 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
614 retval = rtsx_pre_handle_sdio_old(chip);
616 retval = rtsx_pre_handle_sdio_new(chip);
618 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (rtsx_reset_chip)\n",
619 (unsigned int)(chip->need_reset));
620 #else /* HW_AUTO_SWITCH_SD_BUS */
621 retval = rtsx_pre_handle_sdio_old(chip);
622 #endif /* HW_AUTO_SWITCH_SD_BUS */
623 if (retval != STATUS_SUCCESS) {
630 retval = rtsx_write_register(chip, SDIO_CTRL,
631 SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
639 if (chip->int_reg & XD_EXIST)
640 chip->need_reset |= XD_CARD;
641 if (chip->int_reg & MS_EXIST)
642 chip->need_reset |= MS_CARD;
643 if (chip->int_reg & CARD_EXIST) {
644 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
652 dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
653 (unsigned int)(chip->need_reset));
655 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
661 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
662 /* Turn off main power when entering S3/S4 state */
663 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
671 if (chip->remote_wakeup_en && !chip->auto_delink_en) {
672 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
677 if (chip->aux_pwr_exist) {
678 retval = rtsx_write_register(chip, PME_FORCE_CTL,
686 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
691 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
698 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
699 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
706 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
707 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
708 if (retval != STATUS_SUCCESS) {
714 if (chip->ft2_fast_mode) {
715 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
716 MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
721 udelay(chip->pmos_pwr_on_interval);
722 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
723 MS_POWER_ON | SD_POWER_ON);
733 rtsx_reset_detected_cards(chip, 0);
735 chip->driver_first_load = 0;
737 return STATUS_SUCCESS;
740 static inline int check_sd_speed_prior(u32 sd_speed_prior)
742 bool fake_para = false;
745 for (i = 0; i < 4; i++) {
746 u8 tmp = (u8)(sd_speed_prior >> (i * 8));
748 if ((tmp < 0x01) || (tmp > 0x04)) {
757 static inline int check_sd_current_prior(u32 sd_current_prior)
759 bool fake_para = false;
762 for (i = 0; i < 4; i++) {
763 u8 tmp = (u8)(sd_current_prior >> (i * 8));
774 static int rts5208_init(struct rtsx_chip *chip)
780 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
785 retval = rtsx_read_register(chip, CLK_SEL, &val);
790 chip->asic_code = val == 0 ? 1 : 0;
792 if (chip->asic_code) {
793 retval = rtsx_read_phy_register(chip, 0x1C, ®);
794 if (retval != STATUS_SUCCESS) {
799 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
801 chip->ic_version = (reg >> 4) & 0x07;
802 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
805 retval = rtsx_read_register(chip, 0xFE80, &val);
810 chip->ic_version = val;
811 chip->phy_debug_mode = 0;
814 retval = rtsx_read_register(chip, PDINFO, &val);
819 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
820 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
822 retval = rtsx_read_register(chip, 0xFE50, &val);
827 chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
829 rtsx_read_config_byte(chip, 0x0E, &val);
831 SET_SDIO_EXIST(chip);
833 CLR_SDIO_EXIST(chip);
835 if (chip->use_hw_setting) {
836 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
841 chip->auto_delink_en = val & 0x80 ? 1 : 0;
844 return STATUS_SUCCESS;
847 static int rts5288_init(struct rtsx_chip *chip)
850 u8 val = 0, max_func;
853 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
858 retval = rtsx_read_register(chip, CLK_SEL, &val);
863 chip->asic_code = val == 0 ? 1 : 0;
865 chip->ic_version = 0;
866 chip->phy_debug_mode = 0;
868 retval = rtsx_read_register(chip, PDINFO, &val);
873 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
874 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
876 retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
881 dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
882 chip->baro_pkg = val & 0x04 ? QFN : LQFP;
884 retval = rtsx_read_register(chip, 0xFE5A, &val);
889 chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
891 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
892 if (retval != STATUS_SUCCESS) {
897 max_func = (u8)((lval >> 29) & 0x07);
898 dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
899 if (max_func == 0x02)
900 SET_SDIO_EXIST(chip);
902 CLR_SDIO_EXIST(chip);
904 if (chip->use_hw_setting) {
905 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
910 chip->auto_delink_en = val & 0x80 ? 1 : 0;
912 if (CHECK_BARO_PKG(chip, LQFP))
913 chip->lun_mode = SD_MS_1LUN;
915 chip->lun_mode = DEFAULT_SINGLE;
918 return STATUS_SUCCESS;
921 int rtsx_init_chip(struct rtsx_chip *chip)
923 struct sd_info *sd_card = &chip->sd_card;
924 struct xd_info *xd_card = &chip->xd_card;
925 struct ms_info *ms_card = &chip->ms_card;
929 dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
930 chip->vendor_id, chip->product_id);
932 chip->ic_version = 0;
938 memset(xd_card, 0, sizeof(struct xd_info));
939 memset(sd_card, 0, sizeof(struct sd_info));
940 memset(ms_card, 0, sizeof(struct ms_info));
942 chip->xd_reset_counter = 0;
943 chip->sd_reset_counter = 0;
944 chip->ms_reset_counter = 0;
946 chip->xd_show_cnt = MAX_SHOW_CNT;
947 chip->sd_show_cnt = MAX_SHOW_CNT;
948 chip->ms_show_cnt = MAX_SHOW_CNT;
951 chip->auto_delink_cnt = 0;
952 chip->auto_delink_allowed = 1;
953 rtsx_set_stat(chip, RTSX_STAT_INIT);
955 chip->aspm_enabled = 0;
956 chip->chip_insert_with_sdio = 0;
959 chip->sdio_counter = 0;
961 chip->phy_debug_mode = 0;
962 chip->sdio_func_exist = 0;
963 memset(chip->sdio_raw_data, 0, 12);
965 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
966 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
967 chip->rw_fail_cnt[i] = 0;
970 if (!check_sd_speed_prior(chip->sd_speed_prior))
971 chip->sd_speed_prior = 0x01040203;
973 dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
974 chip->sd_speed_prior);
976 if (!check_sd_current_prior(chip->sd_current_prior))
977 chip->sd_current_prior = 0x00010203;
979 dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
980 chip->sd_current_prior);
982 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
983 chip->sd_ddr_tx_phase = 0;
985 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
986 chip->mmc_ddr_tx_phase = 0;
988 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
994 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
999 dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
1000 chip->use_hw_setting);
1002 if (CHECK_PID(chip, 0x5208)) {
1003 retval = rts5208_init(chip);
1004 if (retval != STATUS_SUCCESS) {
1009 } else if (CHECK_PID(chip, 0x5288)) {
1010 retval = rts5288_init(chip);
1011 if (retval != STATUS_SUCCESS) {
1017 if (chip->ss_en == 2)
1020 dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
1021 dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
1022 dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
1023 chip->phy_debug_mode);
1024 dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
1025 chip->aux_pwr_exist);
1026 dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
1027 chip->sdio_func_exist);
1028 dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
1029 chip->hw_bypass_sd);
1030 dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
1031 chip->aspm_l0s_l1_en);
1032 dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
1033 dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
1034 chip->auto_delink_en);
1035 dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
1036 dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
1038 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1039 chip->card2lun[SD_CARD] = 0;
1040 chip->card2lun[MS_CARD] = 1;
1041 chip->card2lun[XD_CARD] = 0xFF;
1042 chip->lun2card[0] = SD_CARD;
1043 chip->lun2card[1] = MS_CARD;
1045 SET_SDIO_IGNORED(chip);
1046 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1047 chip->card2lun[SD_CARD] = 0;
1048 chip->card2lun[MS_CARD] = 0;
1049 chip->card2lun[XD_CARD] = 0xFF;
1050 chip->lun2card[0] = SD_CARD | MS_CARD;
1053 chip->card2lun[XD_CARD] = 0;
1054 chip->card2lun[SD_CARD] = 0;
1055 chip->card2lun[MS_CARD] = 0;
1056 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1060 retval = rtsx_reset_chip(chip);
1061 if (retval != STATUS_SUCCESS) {
1066 return STATUS_SUCCESS;
1069 void rtsx_release_chip(struct rtsx_chip *chip)
1071 xd_free_l2p_tbl(chip);
1072 ms_free_l2p_tbl(chip);
1073 chip->card_exist = 0;
1074 chip->card_ready = 0;
1077 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1078 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1080 if (chip->card_exist && chip->blink_led) {
1081 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1082 chip->led_toggle_counter++;
1084 chip->led_toggle_counter = 0;
1085 toggle_gpio(chip, LED_GPIO);
1091 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1093 bool reg_changed, maybe_support_aspm;
1095 u8 reg0 = 0, reg1 = 0;
1097 maybe_support_aspm = false;
1098 reg_changed = false;
1099 rtsx_read_config_byte(chip, LCTLR, ®0);
1100 if (chip->aspm_level[0] != reg0) {
1102 chip->aspm_level[0] = reg0;
1104 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1105 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1107 if (chip->aspm_level[1] != reg1) {
1109 chip->aspm_level[1] = reg1;
1112 if ((reg0 & 0x03) && (reg1 & 0x03))
1113 maybe_support_aspm = true;
1117 maybe_support_aspm = true;
1121 if (maybe_support_aspm)
1122 chip->aspm_l0s_l1_en = 0x03;
1124 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1125 chip->aspm_level[0], chip->aspm_level[1]);
1127 if (chip->aspm_l0s_l1_en) {
1128 chip->aspm_enabled = 1;
1130 chip->aspm_enabled = 0;
1131 chip->sdio_aspm = 0;
1133 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1134 0x30 | chip->aspm_level[0] |
1135 (chip->aspm_level[1] << 2));
1139 static void rtsx_manage_ocp(struct rtsx_chip *chip)
1145 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1147 if (chip->card_exist & SD_CARD)
1148 sd_power_off_card3v3(chip);
1149 else if (chip->card_exist & MS_CARD)
1150 ms_power_off_card3v3(chip);
1151 else if (chip->card_exist & XD_CARD)
1152 xd_power_off_card3v3(chip);
1158 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1160 #ifdef SUPPORT_SD_LOCK
1161 struct sd_info *sd_card = &chip->sd_card;
1164 if (!sd_card->sd_erase_status)
1167 if (chip->card_exist & SD_CARD) {
1168 rtsx_read_register(chip, 0xFD30, &val);
1170 sd_card->sd_erase_status = SD_NOT_ERASE;
1171 sd_card->sd_lock_notify = 1;
1172 chip->need_reinit |= SD_CARD;
1175 sd_card->sd_erase_status = SD_NOT_ERASE;
1180 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1184 if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1187 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1188 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1196 static void rtsx_manage_ss(struct rtsx_chip *chip)
1198 if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1201 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1202 chip->ss_counter = 0;
1206 if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1209 rtsx_exclusive_enter_ss(chip);
1212 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1216 if (!CHECK_PID(chip, 0x5208))
1219 rtsx_monitor_aspm_config(chip);
1221 #ifdef SUPPORT_SDIO_ASPM
1222 if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1223 !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1227 dynamic_configure_sdio_aspm(chip);
1231 if (chip->sdio_aspm)
1234 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1235 data = 0x30 | (chip->aspm_level[1] << 2);
1236 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1237 chip->sdio_aspm = 1;
1241 static void rtsx_manage_idle(struct rtsx_chip *chip)
1243 if (chip->idle_counter < IDLE_MAX_COUNT) {
1244 chip->idle_counter++;
1248 if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1251 dev_dbg(rtsx_dev(chip), "Idle state!\n");
1252 rtsx_set_stat(chip, RTSX_STAT_IDLE);
1254 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1255 chip->led_toggle_counter = 0;
1257 rtsx_force_power_on(chip, SSC_PDCTL);
1259 turn_off_led(chip, LED_GPIO);
1261 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1262 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1265 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1270 sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1271 ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1274 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1277 if (sd_oc && (chip->card_exist & SD_CARD)) {
1278 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1279 card_power_off(chip, SD_CARD);
1280 chip->card_fail |= SD_CARD;
1283 if (ms_oc && (chip->card_exist & MS_CARD)) {
1284 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1285 card_power_off(chip, MS_CARD);
1286 chip->card_fail |= MS_CARD;
1291 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1294 if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1297 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1300 if (chip->card_exist & SD_CARD) {
1301 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1302 chip->card_fail |= SD_CARD;
1303 } else if (chip->card_exist & MS_CARD) {
1304 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1305 chip->card_fail |= MS_CARD;
1306 } else if (chip->card_exist & XD_CARD) {
1307 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1308 chip->card_fail |= XD_CARD;
1310 card_power_off(chip, SD_CARD);
1314 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1319 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1321 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1322 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1324 if (chip->card_exist)
1325 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1327 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1330 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1332 if (chip->card_exist)
1337 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1340 rtsx_enter_L1(chip);
1342 if (chip->card_exist)
1343 chip->auto_delink_cnt = stage3_cnt + 1;
1346 static void rtsx_delink_stage(struct rtsx_chip *chip)
1348 int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1351 if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1352 chip->card_ready || chip->card_ejected || chip->sd_io) {
1353 chip->auto_delink_cnt = 0;
1357 enter_L1 = chip->auto_delink_in_L1 &&
1358 (chip->aspm_l0s_l1_en || chip->ss_en);
1360 delink_stage1_cnt = chip->delink_stage1_step;
1361 delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1362 delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1364 if (chip->auto_delink_cnt > delink_stage3_cnt)
1367 if (chip->auto_delink_cnt == delink_stage1_cnt)
1368 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1370 if (chip->auto_delink_cnt == delink_stage2_cnt) {
1371 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1376 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1377 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1379 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1382 chip->auto_delink_cnt++;
1385 void rtsx_polling_func(struct rtsx_chip *chip)
1387 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1390 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1393 if (chip->polling_config) {
1396 rtsx_read_config_byte(chip, 0, &val);
1399 if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1402 rtsx_manage_ocp(chip);
1404 rtsx_manage_sd_lock(chip);
1406 rtsx_init_cards(chip);
1408 rtsx_manage_ss(chip);
1410 rtsx_manage_aspm(chip);
1412 rtsx_manage_idle(chip);
1414 switch (rtsx_get_stat(chip)) {
1416 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1417 rtsx_blink_led(chip);
1419 do_remaining_work(chip);
1422 case RTSX_STAT_IDLE:
1423 if (chip->sd_io && !chip->sd_int)
1424 try_to_switch_sdio_ctrl(chip);
1426 rtsx_enable_aspm(chip);
1433 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1434 rtsx_manage_2lun_mode(chip);
1436 rtsx_manage_1lun_mode(chip);
1439 rtsx_delink_stage(chip);
1443 * rtsx_stop_cmd - stop command transfer and DMA transfer
1444 * @chip: Realtek's card reader chip
1445 * @card: flash card type
1447 * Stop command transfer and DMA transfer.
1448 * This function is called in error handler.
1450 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1454 for (i = 0; i <= 8; i++) {
1455 int addr = RTSX_HCBAR + i * 4;
1458 reg = rtsx_readl(chip, addr);
1459 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1461 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1462 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1464 for (i = 0; i < 16; i++) {
1465 u16 addr = 0xFE20 + (u16)i;
1468 rtsx_read_register(chip, addr, &val);
1469 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1472 rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1473 rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1476 #define MAX_RW_REG_CNT 1024
1478 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1483 val |= (u32)(addr & 0x3FFF) << 16;
1484 val |= (u32)mask << 8;
1487 rtsx_writel(chip, RTSX_HAIMR, val);
1489 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1490 val = rtsx_readl(chip, RTSX_HAIMR);
1491 if ((val & (1 << 31)) == 0) {
1492 if (data != (u8)val) {
1497 return STATUS_SUCCESS;
1502 return STATUS_TIMEDOUT;
1505 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1513 val |= (u32)(addr & 0x3FFF) << 16;
1515 rtsx_writel(chip, RTSX_HAIMR, val);
1517 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1518 val = rtsx_readl(chip, RTSX_HAIMR);
1519 if ((val & (1 << 31)) == 0)
1523 if (i >= MAX_RW_REG_CNT) {
1525 return STATUS_TIMEDOUT;
1529 *data = (u8)(val & 0xFF);
1531 return STATUS_SUCCESS;
1534 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1541 for (i = 0; i < 4; i++) {
1543 retval = rtsx_write_register(chip, CFGDATA0 + i,
1545 (u8)(val & mask & 0xFF));
1557 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1562 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1569 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1570 0x80 | mode | ((func_no & 0x03) << 4));
1576 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1577 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1582 if ((tmp & 0x80) == 0)
1587 return STATUS_SUCCESS;
1590 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1597 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1602 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1607 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1608 0x80 | ((func_no & 0x03) << 4));
1614 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1615 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1620 if ((tmp & 0x80) == 0)
1624 for (i = 0; i < 4; i++) {
1625 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1630 data |= (u32)tmp << (i * 8);
1636 return STATUS_SUCCESS;
1639 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1643 u16 offset = addr % 4;
1644 u16 aligned_addr = addr - offset;
1650 return STATUS_NOMEM;
1653 if ((len + offset) % 4)
1654 dw_len = (len + offset) / 4 + 1;
1656 dw_len = (len + offset) / 4;
1658 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1660 data = vzalloc(dw_len * 4);
1663 return STATUS_NOMEM;
1666 mask = vzalloc(dw_len * 4);
1670 return STATUS_NOMEM;
1674 for (i = 0; i < len; i++) {
1675 mask[j] |= 0xFF << (offset * 8);
1676 data[j] |= buf[i] << (offset * 8);
1677 if (++offset == 4) {
1683 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1685 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1688 for (i = 0; i < dw_len; i++) {
1689 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1691 if (retval != STATUS_SUCCESS) {
1702 return STATUS_SUCCESS;
1705 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1709 u16 offset = addr % 4;
1710 u16 aligned_addr = addr - offset;
1714 if ((len + offset) % 4)
1715 dw_len = (len + offset) / 4 + 1;
1717 dw_len = (len + offset) / 4;
1719 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1721 data = vmalloc(dw_len * 4);
1724 return STATUS_NOMEM;
1727 for (i = 0; i < dw_len; i++) {
1728 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1730 if (retval != STATUS_SUCCESS) {
1740 for (i = 0; i < len; i++) {
1741 buf[i] = (u8)(data[j] >> (offset * 8));
1742 if (++offset == 4) {
1751 return STATUS_SUCCESS;
1754 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1757 bool finished = false;
1761 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1766 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1771 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1776 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1782 for (i = 0; i < 100000; i++) {
1783 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1788 if (!(tmp & 0x80)) {
1799 return STATUS_SUCCESS;
1802 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1805 bool finished = false;
1810 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1815 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1821 for (i = 0; i < 100000; i++) {
1822 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1827 if (!(tmp & 0x80)) {
1838 retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1844 retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1849 data |= (u16)tmp << 8;
1854 return STATUS_SUCCESS;
1857 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1863 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1869 for (i = 0; i < 100; i++) {
1870 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1882 return STATUS_TIMEDOUT;
1885 retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1893 return STATUS_SUCCESS;
1896 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1900 u8 data = 0, tmp = 0xFF;
1902 for (i = 0; i < 8; i++) {
1903 if (val & (u8)(1 << i))
1906 tmp &= (~(u8)(1 << i));
1907 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1909 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1914 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1921 for (j = 0; j < 100; j++) {
1922 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1934 return STATUS_TIMEDOUT;
1940 return STATUS_SUCCESS;
1943 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1948 retval = rtsx_read_phy_register(chip, reg, &value);
1949 if (retval != STATUS_SUCCESS) {
1954 if (value & (1 << bit)) {
1955 value &= ~(1 << bit);
1956 retval = rtsx_write_phy_register(chip, reg, value);
1957 if (retval != STATUS_SUCCESS) {
1963 return STATUS_SUCCESS;
1966 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1971 retval = rtsx_read_phy_register(chip, reg, &value);
1972 if (retval != STATUS_SUCCESS) {
1977 if ((value & (1 << bit)) == 0) {
1978 value |= (1 << bit);
1979 retval = rtsx_write_phy_register(chip, reg, value);
1980 if (retval != STATUS_SUCCESS) {
1986 return STATUS_SUCCESS;
1989 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1993 dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1994 chip->product_id, dstate);
1996 if (CHK_SDIO_EXIST(chip)) {
1999 if (CHECK_PID(chip, 0x5288))
2004 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
2005 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
2006 (int)func_no, ultmp);
2007 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
2010 rtsx_write_config_byte(chip, 0x44, dstate);
2011 rtsx_write_config_byte(chip, 0x45, 0);
2014 void rtsx_enter_L1(struct rtsx_chip *chip)
2016 rtsx_handle_pm_dstate(chip, 2);
2019 void rtsx_exit_L1(struct rtsx_chip *chip)
2021 rtsx_write_config_byte(chip, 0x44, 0);
2022 rtsx_write_config_byte(chip, 0x45, 0);
2025 void rtsx_enter_ss(struct rtsx_chip *chip)
2027 dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
2029 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
2031 if (chip->power_down_in_ss) {
2032 rtsx_power_off_card(chip);
2033 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2036 if (CHK_SDIO_EXIST(chip))
2037 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2038 0xC0, 0xFF00, 0x0100);
2040 if (chip->auto_delink_en) {
2041 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
2043 if (!chip->phy_debug_mode) {
2046 tmp = rtsx_readl(chip, RTSX_BIER);
2048 rtsx_writel(chip, RTSX_BIER, tmp);
2051 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
2054 rtsx_enter_L1(chip);
2056 RTSX_CLR_DELINK(chip);
2057 rtsx_set_stat(chip, RTSX_STAT_SS);
2060 void rtsx_exit_ss(struct rtsx_chip *chip)
2062 dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
2066 if (chip->power_down_in_ss) {
2067 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
2071 if (RTSX_TST_DELINK(chip)) {
2072 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2073 rtsx_reinit_cards(chip, 1);
2074 RTSX_CLR_DELINK(chip);
2075 } else if (chip->power_down_in_ss) {
2076 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
2077 rtsx_reinit_cards(chip, 0);
2081 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
2083 u32 status, int_enable;
2084 bool exit_ss = false;
2092 chip->ss_counter = 0;
2093 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
2096 rtsx_set_stat(chip, RTSX_STAT_RUN);
2100 int_enable = rtsx_readl(chip, RTSX_BIER);
2101 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
2103 if (((chip->int_reg & int_enable) == 0) ||
2104 (chip->int_reg == 0xFFFFFFFF))
2107 status = chip->int_reg &= (int_enable | 0x7FFFFF);
2109 if (status & CARD_INT) {
2110 chip->auto_delink_cnt = 0;
2112 if (status & SD_INT) {
2113 if (status & SD_EXIST) {
2114 set_bit(SD_NR, &chip->need_reset);
2116 set_bit(SD_NR, &chip->need_release);
2117 chip->sd_reset_counter = 0;
2118 chip->sd_show_cnt = 0;
2119 clear_bit(SD_NR, &chip->need_reset);
2123 * If multi-luns, it's possible that
2124 * when plugging/unplugging one card
2125 * there is another card which still
2126 * exists in the slot. In this case,
2127 * all existed cards should be reset.
2129 if (exit_ss && (status & SD_EXIST))
2130 set_bit(SD_NR, &chip->need_reinit);
2132 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2133 if (status & XD_INT) {
2134 if (status & XD_EXIST) {
2135 set_bit(XD_NR, &chip->need_reset);
2137 set_bit(XD_NR, &chip->need_release);
2138 chip->xd_reset_counter = 0;
2139 chip->xd_show_cnt = 0;
2140 clear_bit(XD_NR, &chip->need_reset);
2143 if (exit_ss && (status & XD_EXIST))
2144 set_bit(XD_NR, &chip->need_reinit);
2147 if (status & MS_INT) {
2148 if (status & MS_EXIST) {
2149 set_bit(MS_NR, &chip->need_reset);
2151 set_bit(MS_NR, &chip->need_release);
2152 chip->ms_reset_counter = 0;
2153 chip->ms_show_cnt = 0;
2154 clear_bit(MS_NR, &chip->need_reset);
2157 if (exit_ss && (status & MS_EXIST))
2158 set_bit(MS_NR, &chip->need_reinit);
2163 chip->ocp_int = ocp_int & status;
2166 if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2167 chip->int_reg &= ~(u32)DATA_DONE_INT;
2169 return STATUS_SUCCESS;
2172 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2176 dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2178 rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2180 retval = rtsx_force_power_on(chip, SSC_PDCTL);
2181 if (retval != STATUS_SUCCESS)
2184 rtsx_release_cards(chip);
2185 rtsx_disable_bus_int(chip);
2186 turn_off_led(chip, LED_GPIO);
2188 #ifdef HW_AUTO_SWITCH_SD_BUS
2190 chip->sdio_in_charge = 1;
2191 if (CHECK_PID(chip, 0x5208)) {
2192 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2193 /* Enable sdio_bus_auto_switch */
2194 rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2195 } else if (CHECK_PID(chip, 0x5288)) {
2196 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2197 /* Enable sdio_bus_auto_switch */
2198 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2203 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2204 /* u_force_clkreq_0 */
2205 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2208 if (pm_stat == PM_S1) {
2209 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2210 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2212 } else if (pm_stat == PM_S3) {
2213 if (chip->s3_pwr_off_delay > 0)
2214 wait_timeout(chip->s3_pwr_off_delay);
2216 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2217 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2221 if (chip->do_delink_before_power_down && chip->auto_delink_en)
2222 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2224 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2228 chip->card_exist = 0;
2231 void rtsx_enable_aspm(struct rtsx_chip *chip)
2233 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2234 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2235 chip->aspm_enabled = 1;
2237 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2238 rtsx_write_phy_register(chip, 0x07, 0);
2239 if (CHECK_PID(chip, 0x5208)) {
2240 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2241 0x30 | chip->aspm_level[0]);
2243 rtsx_write_config_byte(chip, LCTLR,
2244 chip->aspm_l0s_l1_en);
2247 if (CHK_SDIO_EXIST(chip)) {
2248 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2250 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2256 void rtsx_disable_aspm(struct rtsx_chip *chip)
2258 if (CHECK_PID(chip, 0x5208))
2259 rtsx_monitor_aspm_config(chip);
2261 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2262 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2263 chip->aspm_enabled = 0;
2265 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2266 rtsx_write_phy_register(chip, 0x07, 0x0129);
2267 if (CHECK_PID(chip, 0x5208))
2268 rtsx_write_register(chip, ASPM_FORCE_CTL,
2271 rtsx_write_config_byte(chip, LCTLR, 0x00);
2277 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2286 return STATUS_ERROR;
2290 reg_addr = PPBUF_BASE2;
2291 for (i = 0; i < buf_len / 256; i++) {
2292 rtsx_init_cmd(chip);
2294 for (j = 0; j < 256; j++)
2295 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2297 retval = rtsx_send_cmd(chip, 0, 250);
2303 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2307 if (buf_len % 256) {
2308 rtsx_init_cmd(chip);
2310 for (j = 0; j < buf_len % 256; j++)
2311 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2313 retval = rtsx_send_cmd(chip, 0, 250);
2320 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256);
2322 return STATUS_SUCCESS;
2325 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2334 return STATUS_ERROR;
2338 reg_addr = PPBUF_BASE2;
2339 for (i = 0; i < buf_len / 256; i++) {
2340 rtsx_init_cmd(chip);
2342 for (j = 0; j < 256; j++) {
2343 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2348 retval = rtsx_send_cmd(chip, 0, 250);
2355 if (buf_len % 256) {
2356 rtsx_init_cmd(chip);
2358 for (j = 0; j < buf_len % 256; j++) {
2359 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2364 retval = rtsx_send_cmd(chip, 0, 250);
2371 return STATUS_SUCCESS;
2374 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2376 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2381 return STATUS_SUCCESS;
2384 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2389 if (ctl & SSC_PDCTL)
2390 mask |= SSC_POWER_DOWN;
2393 if (ctl & OC_PDCTL) {
2394 mask |= SD_OC_POWER_DOWN;
2395 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2396 mask |= MS_OC_POWER_DOWN;
2401 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2402 if (retval != STATUS_SUCCESS) {
2407 if (CHECK_PID(chip, 0x5288))
2411 return STATUS_SUCCESS;
2414 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2417 u8 mask = 0, val = 0;
2419 if (ctl & SSC_PDCTL)
2420 mask |= SSC_POWER_DOWN;
2423 if (ctl & OC_PDCTL) {
2424 mask |= SD_OC_POWER_DOWN;
2425 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2426 mask |= MS_OC_POWER_DOWN;
2432 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2433 if (retval != STATUS_SUCCESS) {
2439 return STATUS_SUCCESS;