1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
15 #ifndef __RTL8822B_TRX_H__
16 #define __RTL8822B_TRX_H__
18 #include "../halmac/halmac_tx_desc_nic.h"
19 #include "../halmac/halmac_rx_desc_nic.h"
21 #define TX_DESC_SIZE 64
23 #define RX_DRV_INFO_SIZE_UNIT 8
25 #define TX_DESC_NEXT_DESC_OFFSET 48
26 #define USB_HWDESC_HEADER_LEN 48
28 #define RX_DESC_SIZE 24
29 #define MAX_RECEIVE_BUFFER_SIZE 8192
31 #define SET_EARLYMODE_PKTNUM(__paddr, __val) \
32 SET_BITS_TO_LE_4BYTE(__paddr, 0, 4, __val)
33 #define SET_EARLYMODE_LEN0(__paddr, __val) \
34 SET_BITS_TO_LE_4BYTE(__paddr, 4, 15, __val)
35 #define SET_EARLYMODE_LEN1(__paddr, __val) \
36 SET_BITS_TO_LE_4BYTE(__paddr, 16, 2, __val)
37 #define SET_EARLYMODE_LEN1_1(__paddr, __val) \
38 SET_BITS_TO_LE_4BYTE(__paddr, 19, 13, __val)
39 #define SET_EARLYMODE_LEN1_2(__paddr, __val) \
40 SET_BITS_TO_LE_4BYTE(__paddr + 4, 0, 2, __val)
41 #define SET_EARLYMODE_LEN2(__paddr, __val) \
42 SET_BITS_TO_LE_4BYTE(__paddr + 4, 2, 15, __val)
43 #define SET_EARLYMODE_LEN2_1(__paddr, __val) \
44 SET_BITS_TO_LE_4BYTE(__paddr, 2, 4, __val)
45 #define SET_EARLYMODE_LEN2_2(__paddr, __val) \
46 SET_BITS_TO_LE_4BYTE(__paddr + 4, 0, 8, __val)
47 #define SET_EARLYMODE_LEN3(__paddr, __val) \
48 SET_BITS_TO_LE_4BYTE(__paddr + 4, 17, 15, __val)
49 #define SET_EARLYMODE_LEN4(__paddr, __val) \
50 SET_BITS_TO_LE_4BYTE(__paddr + 4, 20, 12, __val)
52 /* TX/RX buffer descriptor */
54 /* for Txfilldescroptor8822be, fill the desc content. */
55 #define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pdesc, __offset, __val) \
56 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 0, 16, __val)
57 #define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pdesc, __offset, __val) \
58 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16), 31, 1, __val)
59 #define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pdesc, __offset, __val) \
60 SET_BITS_TO_LE_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32, __val)
61 #define SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(pbd, off, val, dma64) \
62 (dma64 ? SET_BITS_TO_LE_4BYTE((pbd) + ((off) * 16) + 8, 0, 32, val) : 0)
63 #define GET_TXBUFFER_DESC_ADDR_LOW(__pdesc, __offset) \
64 LE_BITS_TO_4BYTE((__pdesc) + ((__offset) * 16) + 4, 0, 32)
65 #define GET_TXBUFFER_DESC_ADDR_HIGH(pbd, off, dma64) \
66 (dma64 ? LE_BITS_TO_4BYTE((pbd) + ((off) * 16) + 8, 0, 32) : 0)
69 #define SET_TX_BUFF_DESC_LEN_0(__pdesc, __val) \
70 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
71 #define SET_TX_BUFF_DESC_PSB(__pdesc, __val) \
72 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 15, __val)
73 #define SET_TX_BUFF_DESC_OWN(__pdesc, __val) \
74 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
77 #define SET_TX_BUFF_DESC_ADDR_LOW_0(__pdesc, __val) \
78 SET_BITS_TO_LE_4BYTE((__pdesc) + 4, 0, 32, __val)
80 #define SET_TX_BUFF_DESC_ADDR_HIGH_0(bdesc, val, dma64) \
81 SET_TXBUFFER_DESC_ADD_HIGH_WITH_OFFSET(bdesc, 0, val, dma64)
82 /* Dword 3 / RESERVED 0 */
87 #define SET_RX_BUFFER_DESC_DATA_LENGTH(__rx_status_desc, __val) \
88 SET_BITS_TO_LE_4BYTE(__rx_status_desc, 0, 14, __val)
89 #define SET_RX_BUFFER_DESC_LS(__rx_status_desc, __val) \
90 SET_BITS_TO_LE_4BYTE(__rx_status_desc, 15, 1, __val)
91 #define SET_RX_BUFFER_DESC_FS(__rx_status_desc, __val) \
92 SET_BITS_TO_LE_4BYTE(__rx_status_desc, 16, 1, __val)
93 #define SET_RX_BUFFER_DESC_TOTAL_LENGTH(__rx_status_desc, __val) \
94 SET_BITS_TO_LE_4BYTE(__rx_status_desc, 16, 15, __val)
96 #define GET_RX_BUFFER_DESC_OWN(__rx_status_desc) \
97 LE_BITS_TO_4BYTE(__rx_status_desc, 31, 1)
98 #define GET_RX_BUFFER_DESC_LS(__rx_status_desc) \
99 LE_BITS_TO_4BYTE(__rx_status_desc, 15, 1)
100 #define GET_RX_BUFFER_DESC_FS(__rx_status_desc) \
101 LE_BITS_TO_4BYTE(__rx_status_desc, 16, 1)
102 #define GET_RX_BUFFER_DESC_TOTAL_LENGTH(__rx_status_desc) \
103 LE_BITS_TO_4BYTE(__rx_status_desc, 16, 15)
106 #define SET_RX_BUFFER_PHYSICAL_LOW(__rx_status_desc, __val) \
107 SET_BITS_TO_LE_4BYTE(__rx_status_desc + 4, 0, 32, __val)
110 #define SET_RX_BUFFER_PHYSICAL_HIGH(__rx_status_desc, __val, dma64) \
111 (dma64 ? SET_BITS_TO_LE_4BYTE((__rx_status_desc) + 8, 0, 32, __val) : 0)
113 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
115 if (_size > TX_DESC_NEXT_DESC_OFFSET) \
116 memset(__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET); \
118 memset(__pdesc, 0, _size); \
121 void rtl8822be_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
123 u16 rtl8822be_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw,
125 u16 rtl8822be_get_available_desc(struct ieee80211_hw *hw, u8 queue_index);
126 void rtl8822be_pre_fill_tx_bd_desc(struct ieee80211_hw *hw, u8 *tx_bd_desc,
127 u8 *desc, u8 queue_index,
128 struct sk_buff *skb, dma_addr_t addr);
130 void rtl8822be_tx_fill_desc(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
131 u8 *pdesc_tx, u8 *pbd_desc_tx,
132 struct ieee80211_tx_info *info,
133 struct ieee80211_sta *sta, struct sk_buff *skb,
134 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc);
135 void rtl8822be_tx_fill_special_desc(struct ieee80211_hw *hw, u8 *pdesc,
136 u8 *pbd_desc, struct sk_buff *skb,
138 bool rtl8822be_rx_query_desc(struct ieee80211_hw *hw, struct rtl_stats *status,
139 struct ieee80211_rx_status *rx_status, u8 *pdesc,
140 struct sk_buff *skb);
141 void rtl8822be_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
142 u8 desc_name, u8 *val);
143 u64 rtl8822be_get_desc(struct ieee80211_hw *hw,
144 u8 *pdesc, bool istx, u8 desc_name);
145 bool rtl8822be_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
147 void rtl8822be_tx_polling(struct ieee80211_hw *hw, u8 hw_queue);
148 void rtl8822be_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
149 bool firstseg, bool lastseg,
150 struct sk_buff *skb);
151 u32 rtl8822be_rx_command_packet(struct ieee80211_hw *hw,
152 const struct rtl_stats *status,
153 struct sk_buff *skb);