1 /******************************************************************************
3 * Copyright(c) 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL8822B_REG_H__
27 #define __RTL8822B_REG_H__
29 #include "../halmac/halmac_reg_8822b.h"
30 #include "../halmac/halmac_bit_8822b.h"
32 #define TXPKT_BUF_SELECT 0x69
33 #define RXPKT_BUF_SELECT 0xA5
34 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
37 #define REG_LEDCFG2_8822B 0x004E /* need review */
38 #define REG_SPS0_CTRL_8822B 0x0011 /* need review: swlps */
40 #define REG_EFUSE_ACCESS_8822B (REG_PMC_DBG_CTRL2_8822B + 3) /*0x00CF*/
41 #define REG_AFE_XTAL_CTRL_8822B REG_AFE_CTRL1_8822B
42 #define REG_AFE_PLL_CTRL_8822B REG_AFE_CTRL2_8822B
46 #define MSR (REG_CR_8822B + 2)
49 #define MSR_NOLINK 0x00
50 #define MSR_ADHOC 0x01
51 #define MSR_INFRA 0x02
54 /*-----------------------------------------------------
56 * 0x0200h ~ 0x027Fh TXDMA Configuration
58 *-----------------------------------------------------
61 /*-----------------------------------------------------
63 * 0x0280h ~ 0x02FFh RXDMA Configuration
65 *-----------------------------------------------------
67 #define REG_RXDMA_CONTROL_8822B (REG_RXPKT_NUM_8822B + 2) /* 0x0286 */
69 /*-----------------------------------------------------
71 * 0x0300h ~ 0x03FFh PCIe
73 *-----------------------------------------------------
77 #define IMR_H2CDOK BIT_SETH2CDOK_MASK_8822B
80 *-----------------------------------------------------
82 * 0x0400h ~ 0x047Fh Protocol Configuration
84 *-----------------------------------------------------
87 #define REG_MAX_AGGR_NUM_8822B (REG_PROT_MODE_CTRL_8822B + 2) /*0x04CA*/
90 #define RRSR_RSC_OFFSET 21
91 #define RRSR_SHORT_OFFSET 23
92 #define RRSR_RSC_BW_40M 0x600000
93 #define RRSR_RSC_UPSUBCHNL 0x400000
94 #define RRSR_RSC_LOWSUBCHNL 0x200000
95 #define RRSR_1M BIT(0)
96 #define RRSR_2M BIT(1)
97 #define RRSR_5_5M BIT(2)
98 #define RRSR_11M BIT(3)
99 #define RRSR_6M BIT(4)
100 #define RRSR_9M BIT(5)
101 #define RRSR_12M BIT(6)
102 #define RRSR_18M BIT(7)
103 #define RRSR_24M BIT(8)
104 #define RRSR_36M BIT(9)
105 #define RRSR_48M BIT(10)
106 #define RRSR_54M BIT(11)
107 #define RRSR_MCS0 BIT(12)
108 #define RRSR_MCS1 BIT(13)
109 #define RRSR_MCS2 BIT(14)
110 #define RRSR_MCS3 BIT(15)
111 #define RRSR_MCS4 BIT(16)
112 #define RRSR_MCS5 BIT(17)
113 #define RRSR_MCS6 BIT(18)
114 #define RRSR_MCS7 BIT(19)
116 #define RRSR_ALL_CCK (RRSR_1M | RRSR_2M | RRSR_5_5M | RRSR_11M)
117 #define RRSR_ALL_OFDM_AG \
118 (RRSR_6M | RRSR_9M | RRSR_12M | RRSR_18M | RRSR_24M | RRSR_36M | \
121 /*-----------------------------------------------------
123 * 0x0500h ~ 0x05FFh EDCA Configuration
125 *-----------------------------------------------------
128 #define REG_SIFS_TRX_8822B (REG_SIFS_8822B + 2) /*0x0516*/
130 /*-----------------------------------------------------
132 * 0x0600h ~ 0x07FFh WMAC Configuration
134 *-----------------------------------------------------
137 #define RATR_1M 0x00000001
138 #define RATR_2M 0x00000002
139 #define RATR_55M 0x00000004
140 #define RATR_11M 0x00000008
141 #define RATR_6M 0x00000010
142 #define RATR_9M 0x00000020
143 #define RATR_12M 0x00000040
144 #define RATR_18M 0x00000080
145 #define RATR_24M 0x00000100
146 #define RATR_36M 0x00000200
147 #define RATR_48M 0x00000400
148 #define RATR_54M 0x00000800
149 #define RATR_MCS0 0x00001000
150 #define RATR_MCS1 0x00002000
151 #define RATR_MCS2 0x00004000
152 #define RATR_MCS3 0x00008000
153 #define RATR_MCS4 0x00010000
154 #define RATR_MCS5 0x00020000
155 #define RATR_MCS6 0x00040000
156 #define RATR_MCS7 0x00080000
157 #define RATR_MCS8 0x00100000
158 #define RATR_MCS9 0x00200000
159 #define RATR_MCS10 0x00400000
160 #define RATR_MCS11 0x00800000
161 #define RATR_MCS12 0x01000000
162 #define RATR_MCS13 0x02000000
163 #define RATR_MCS14 0x04000000
164 #define RATR_MCS15 0x08000000
166 #define RATE_1M BIT(0)
167 #define RATE_2M BIT(1)
168 #define RATE_5_5M BIT(2)
169 #define RATE_11M BIT(3)
170 #define RATE_6M BIT(4)
171 #define RATE_9M BIT(5)
172 #define RATE_12M BIT(6)
173 #define RATE_18M BIT(7)
174 #define RATE_24M BIT(8)
175 #define RATE_36M BIT(9)
176 #define RATE_48M BIT(10)
177 #define RATE_54M BIT(11)
178 #define RATE_MCS0 BIT(12)
179 #define RATE_MCS1 BIT(13)
180 #define RATE_MCS2 BIT(14)
181 #define RATE_MCS3 BIT(15)
182 #define RATE_MCS4 BIT(16)
183 #define RATE_MCS5 BIT(17)
184 #define RATE_MCS6 BIT(18)
185 #define RATE_MCS7 BIT(19)
186 #define RATE_MCS8 BIT(20)
187 #define RATE_MCS9 BIT(21)
188 #define RATE_MCS10 BIT(22)
189 #define RATE_MCS11 BIT(23)
190 #define RATE_MCS12 BIT(24)
191 #define RATE_MCS13 BIT(25)
192 #define RATE_MCS14 BIT(26)
193 #define RATE_MCS15 BIT(27)
198 #define CAM_WEP40 0x01
199 #define CAM_TKIP 0x02
201 #define CAM_WEP104 0x05
203 /*#define TOTAL_CAM_ENTRY 64*/
204 /*#define HALF_CAM_ENTRY 32*/
206 #define CAM_WRITE BIT(16)
207 #define CAM_READ 0x00000000
208 #define CAM_POLLINIG BIT(31)
210 /*********************************************
211 * 8822BE IMR/ISR bits
212 *********************************************
214 #define IMR_DISABLED 0x0
215 /* IMR DW0(0x0060-0063) Bit 0-31 */
216 #define IMR_TIMER2 BIT(31)
217 #define IMR_TIMER1 BIT(30)
218 #define IMR_PSTIMEOUT BIT(29)
219 #define IMR_GTINT4 BIT(28)
220 #define IMR_GTINT3 BIT(27)
221 #define IMR_TBDER BIT(26)
222 #define IMR_TBDOK BIT(25)
223 #define IMR_TSF_BIT32_TOGGLE BIT(24)
224 #define IMR_BCNDMAINT0 BIT(20)
225 #define IMR_BCNDOK0 BIT(16)
226 #define IMR_HSISR_IND_ON_INT BIT(15)
227 #define IMR_BCNDMAINT_E BIT(14)
228 #define IMR_ATIMEND BIT(12)
229 #define IMR_HISR1_IND_INT BIT(11)
230 #define IMR_C2HCMD BIT(10)
231 #define IMR_CPWM2 BIT(9)
232 #define IMR_CPWM BIT(8)
233 #define IMR_HIGHDOK BIT(7)
234 #define IMR_MGNTDOK BIT(6)
235 #define IMR_BKDOK BIT(5)
236 #define IMR_BEDOK BIT(4)
237 #define IMR_VIDOK BIT(3)
238 #define IMR_VODOK BIT(2)
239 #define IMR_RDU BIT(1)
240 #define IMR_ROK BIT(0)
242 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
243 #define IMR_TXFIFO_TH_INT_8822B BIT_TXFIFO_TH_INT_8822B
244 #define IMR_BTON_STS_UPDATE_MASK_8822B BIT_BTON_STS_UPDATE_MASK_8822B
245 #define IMR_MCUERR BIT(28)
246 #define IMR_BCNDMAINT7 BIT(27)
247 #define IMR_BCNDMAINT6 BIT(26)
248 #define IMR_BCNDMAINT5 BIT(25)
249 #define IMR_BCNDMAINT4 BIT(24)
250 #define IMR_BCNDMAINT3 BIT(23)
251 #define IMR_BCNDMAINT2 BIT(22)
252 #define IMR_BCNDMAINT1 BIT(21)
253 #define IMR_BCNDOK7 BIT(20)
254 #define IMR_BCNDOK6 BIT(19)
255 #define IMR_BCNDOK5 BIT(18)
256 #define IMR_BCNDOK4 BIT(17)
257 #define IMR_BCNDOK3 BIT(16)
258 #define IMR_BCNDOK2 BIT(15)
259 #define IMR_BCNDOK1 BIT(14)
260 #define IMR_ATIMEND_E BIT(13)
261 #define IMR_ATIMEND BIT(12)
262 #define IMR_TXERR BIT(11)
263 #define IMR_RXERR BIT(10)
264 #define IMR_TXFOVW BIT(9)
265 #define IMR_RXFOVW BIT(8)
266 #define IMR_CPU_MGQ_TXDONE_MSK_8822B BIT_CPU_MGQ_TXDONE_MSK_8822B
267 #define IMR_PS_TIMER_C_MSK_8822B BIT_PS_TIMER_C_MSK_8822B
268 #define IMR_PS_TIMER_B_MSK_8822B BIT_PS_TIMER_B_MSK_8822B
269 #define IMR_PS_TIMER_A_MSK_8822B BIT_PS_TIMER_A_MSK_8822B
270 #define IMR_CPUMGQ_TX_TIMER_MSK_8822B BIT_CPUMGQ_TX_TIMER_MSK_8822B
272 /*********************************************
273 * 8822BE EFUSE definition
274 *********************************************
276 #define HWSET_MAX_SIZE 1024
277 #define EFUSE_MAX_SECTION 64
278 #define EFUSE_REAL_CONTENT_LEN 1024
279 #define EFUSE_OOB_PROTECT_BYTES 18
281 #define EEPROM_DEFAULT_THERMALMETER 0x12
283 #define RTL8822B_EEPROM_ID 0x8129
285 #define PPG_BB_GAIN_2G_TXA_OFFSET_8822B 0xEE
286 #define PPG_THERMAL_OFFSET_8822B 0xEF
288 #define EEPROM_TX_PWR_INX_8822B 0x10
290 #define EEPROM_CHANNEL_PLAN_8822B 0xB8
291 #define EEPROM_XTAL_8822B 0xB9
292 #define EEPROM_THERMAL_METER_8822B 0xBA
293 #define EEPROM_IQK_LCK_8822B 0xBB
294 #define EEPROM_2G_5G_PA_TYPE_8822B 0xBC
295 /* PATH A & PATH B */
296 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBD
297 /* PATH C & PATH D */
298 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B 0xBE
299 /* PATH A & PATH B */
300 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBF
301 /* PATH C & PATH D */
302 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B 0xC0
304 #define EEPROM_RF_BOARD_OPTION_8822B 0xC1
305 #define EEPROM_FEATURE_OPTION_8822B 0xC2
306 #define EEPROM_RF_BT_SETTING_8822B 0xC3
307 #define EEPROM_VERSION_8822B 0xC4
308 #define EEPROM_CUSTOM_ID_8822B 0xC5
309 #define EEPROM_TX_BBSWING_2G_8822B 0xC6
310 #define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8
311 #define EEPROM_RF_ANTENNA_OPT_8822B 0xC9
312 #define EEPROM_RFE_OPTION_8822B 0xCA
313 #define EEPROM_COUNTRY_CODE_8822B 0xCB
315 #define EEPROM_VID 0xD6
316 #define EEPROM_DID 0xD8
317 #define EEPROM_SVID 0xDA
318 #define EEPROM_SMID 0xDC
321 #define EEPROM_MAC_ADDR_8822BU 0x107
322 #define EEPROM_VID_8822BU 0x100
323 #define EEPROM_PID_8822BU 0x102
324 #define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU 0x104
325 #define EEPROM_USB_MODE_8822BU 0x06
328 #define EEPROM_MAC_ADDR_8822BS 0x11A
331 #define EEPROM_MAC_ADDR_8822BE 0xD0
333 /* ------------------------- */
335 #define STOPBECON BIT(6)
336 #define STOPHIGHT BIT(5)
337 #define STOPMGT BIT(4)
338 #define STOPVO BIT(3)
339 #define STOPVI BIT(2)
340 #define STOPBE BIT(1)
341 #define STOPBK BIT(0)
343 #define RCR_APPFCS BIT(31)
344 #define RCR_APP_MIC BIT(30)
345 #define RCR_APP_ICV BIT(29)
346 #define RCR_APP_PHYST_RXFF BIT(28)
347 #define RCR_APP_BA_SSN BIT(27)
348 #define RCR_VHT_DACK BIT(26)
349 #define RCR_ENMBID BIT(24)
350 #define RCR_LSIGEN BIT(23)
351 #define RCR_MFBEN BIT(22)
352 #define RCR_HTC_LOC_CTRL BIT(14)
353 #define RCR_AMF BIT(13)
354 #define RCR_ACF BIT(12)
355 #define RCR_ADF BIT(11)
356 #define RCR_AICV BIT(9)
357 #define RCR_ACRC32 BIT(8)
358 #define RCR_CBSSID_BCN BIT(7)
359 #define RCR_CBSSID_DATA BIT(6)
360 #define RCR_CBSSID RCR_CBSSID_DATA
361 #define RCR_APWRMGT BIT(5)
362 #define RCR_ADD3 BIT(4)
363 #define RCR_AB BIT(3)
364 #define RCR_AM BIT(2)
365 #define RCR_APM BIT(1)
366 #define RCR_AAP BIT(0)
367 #define RCR_MXDMA_OFFSET 8
368 #define RCR_FIFO_OFFSET 13
370 #define RSV_CTRL 0x001C
371 #define RD_CTRL 0x0524
373 #define REG_USB_INFO_8822B 0xFE17
374 #define REG_USB_SPECIAL_OPTION_8822B 0xFE55
375 #define REG_USB_DMA_AGG_TO_8822B 0xFE5B
376 #define REG_USB_AGG_TO_8822B 0xFE5C
377 #define REG_USB_AGG_TH_8822B 0xFE5D
379 #define REG_USB_VID_8822B 0xFE60
380 #define REG_USB_PID_8822B 0xFE62
381 #define REG_USB_OPTIONAL_8822B 0xFE64
382 #define REG_USB_CHIRP_K_8822B 0xFE65
383 #define REG_USB_PHY_8822B 0xFE66
384 #define REG_USB_MAC_ADDR_8822B 0xFE70
385 #define REG_USB_HRPWM_8822B 0xFE58
386 #define REG_USB_HCPWM_8822B 0xFE57
388 #define SW18_FPWM BIT(3)
390 #define ISO_MD2PP BIT(0)
391 #define ISO_UA2USB BIT(1)
392 #define ISO_UD2CORE BIT(2)
393 #define ISO_PA2PCIE BIT(3)
394 #define ISO_PD2CORE BIT(4)
395 #define ISO_IP2MAC BIT(5)
396 #define ISO_DIOP BIT(6)
397 #define ISO_DIOE BIT(7)
398 #define ISO_EB2CORE BIT(8)
399 #define ISO_DIOR BIT(9)
401 #define PWC_EV25V BIT(14)
402 #define PWC_EV12V BIT(15)
404 #define FEN_BBRSTB BIT(0)
405 #define FEN_BB_GLB_RSTN BIT(1)
406 #define FEN_USBA BIT(2)
407 #define FEN_UPLL BIT(3)
408 #define FEN_USBD BIT(4)
409 #define FEN_DIO_PCIE BIT(5)
410 #define FEN_PCIEA BIT(6)
411 #define FEN_PPLL BIT(7)
412 #define FEN_PCIED BIT(8)
413 #define FEN_DIOE BIT(9)
414 #define FEN_CPUEN BIT(10)
415 #define FEN_DCORE BIT(11)
416 #define FEN_ELDR BIT(12)
417 #define FEN_DIO_RF BIT(13)
418 #define FEN_HWPDN BIT(14)
419 #define FEN_MREGEN BIT(15)
421 #define PFM_LDALL BIT(0)
422 #define PFM_ALDN BIT(1)
423 #define PFM_LDKP BIT(2)
424 #define PFM_WOWL BIT(3)
425 #define EN_PDN BIT(4)
426 #define PDN_PL BIT(5)
427 #define APFM_ONMAC BIT(8)
428 #define APFM_OFF BIT(9)
429 #define APFM_RSM BIT(10)
430 #define AFSM_HSUS BIT(11)
431 #define AFSM_PCIE BIT(12)
432 #define APDM_MAC BIT(13)
433 #define APDM_HOST BIT(14)
434 #define APDM_HPDN BIT(15)
435 #define RDY_MACON BIT(16)
436 #define SUS_HOST BIT(17)
437 #define ROP_ALD BIT(20)
438 #define ROP_PWR BIT(21)
439 #define ROP_SPS BIT(22)
440 #define SOP_MRST BIT(25)
441 #define SOP_FUSE BIT(26)
442 #define SOP_ABG BIT(27)
443 #define SOP_AMB BIT(28)
444 #define SOP_RCK BIT(29)
445 #define SOP_A8M BIT(30)
446 #define XOP_BTCK BIT(31)
448 #define ANAD16V_EN BIT(0)
450 #define MACSLP BIT(4)
451 #define LOADER_CLK_EN BIT(5)
452 #define _80M_SSC_DIS BIT(7)
453 #define _80M_SSC_EN_HO BIT(8)
454 #define PHY_SSC_RSTB BIT(9)
455 #define SEC_CLK_EN BIT(10)
456 #define MAC_CLK_EN BIT(11)
457 #define SYS_CLK_EN BIT(12)
458 #define RING_CLK_EN BIT(13)
460 #define BOOT_FROM_EEPROM BIT(4)
461 #define EEPROM_EN BIT(5)
463 #define AFE_BGEN BIT(0)
464 #define AFE_MBEN BIT(1)
465 #define MAC_ID_EN BIT(7)
467 #define WLOCK_ALL BIT(0)
468 #define WLOCK_00 BIT(1)
469 #define WLOCK_04 BIT(2)
470 #define WLOCK_08 BIT(3)
471 #define WLOCK_40 BIT(4)
472 #define R_DIS_PRST_0 BIT(5)
473 #define R_DIS_PRST_1 BIT(6)
474 #define LOCK_ALL_EN BIT(7)
477 #define RF_RSTB BIT(1)
478 #define RF_SDMRSTB BIT(2)
480 #define LDA15_EN BIT(0)
481 #define LDA15_STBY BIT(1)
482 #define LDA15_OBUF BIT(2)
483 #define LDA15_REG_VOS BIT(3)
484 #define _LDA15_VOADJ(x) (((x) & 0x7) << 4)
486 #define LDV12_EN BIT(0)
487 #define LDV12_SDBY BIT(1)
488 #define LPLDO_HSM BIT(2)
489 #define LPLDO_LSM_DIS BIT(3)
490 #define _LDV12_VADJ(x) (((x) & 0xF) << 4)
492 #define XTAL_EN BIT(0)
493 #define XTAL_BSEL BIT(1)
494 #define _XTAL_BOSC(x) (((x) & 0x3) << 2)
495 #define _XTAL_CADJ(x) (((x) & 0xF) << 4)
496 #define XTAL_GATE_USB BIT(8)
497 #define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)
498 #define XTAL_GATE_AFE BIT(11)
499 #define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)
500 #define XTAL_RF_GATE BIT(14)
501 #define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)
502 #define XTAL_GATE_DIG BIT(17)
503 #define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)
504 #define XTAL_BT_GATE BIT(20)
505 #define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)
506 #define _XTAL_GPIO(x) (((x) & 0x7) << 23)
508 #define CKDLY_AFE BIT(26)
509 #define CKDLY_USB BIT(27)
510 #define CKDLY_DIG BIT(28)
511 #define CKDLY_BT BIT(29)
513 #define APLL_EN BIT(0)
514 #define APLL_320_EN BIT(1)
515 #define APLL_FREF_SEL BIT(2)
516 #define APLL_EDGE_SEL BIT(3)
517 #define APLL_WDOGB BIT(4)
518 #define APLL_LPFEN BIT(5)
520 #define APLL_REF_CLK_13MHZ 0x1
521 #define APLL_REF_CLK_19_2MHZ 0x2
522 #define APLL_REF_CLK_20MHZ 0x3
523 #define APLL_REF_CLK_25MHZ 0x4
524 #define APLL_REF_CLK_26MHZ 0x5
525 #define APLL_REF_CLK_38_4MHZ 0x6
526 #define APLL_REF_CLK_40MHZ 0x7
528 #define APLL_320EN BIT(14)
529 #define APLL_80EN BIT(15)
530 #define APLL_1MEN BIT(24)
532 #define ALD_EN BIT(18)
533 #define EF_PD BIT(19)
534 #define EF_FLAG BIT(31)
536 #define EF_TRPT BIT(7)
537 #define LDOE25_EN BIT(31)
539 #define RSM_EN BIT(0)
540 #define TIMER_EN BIT(4)
542 #define TRSW0EN BIT(2)
543 #define TRSW1EN BIT(3)
544 #define EROM_EN BIT(4)
546 #define EN_UART BIT(8)
547 #define UART_910 BIT(9)
548 #define EN_PMAC BIT(10)
549 #define SIC_SWRST BIT(11)
550 #define EN_SIC BIT(12)
551 #define SIC_23 BIT(13)
552 #define EN_HDP BIT(14)
553 #define SIC_LBK BIT(15)
555 #define LED0PL BIT(4)
556 #define LED1PL BIT(12)
557 #define LED0DIS BIT(7)
559 #define MCUFWDL_EN BIT(0)
560 #define MCUFWDL_RDY BIT(1)
561 #define FWDL_CHKSUM_RPT BIT(2)
562 #define MACINI_RDY BIT(3)
563 #define BBINI_RDY BIT(4)
564 #define RFINI_RDY BIT(5)
565 #define WINTINI_RDY BIT(6)
566 #define CPRST BIT(23)
568 #define XCLK_VLD BIT(0)
569 #define ACLK_VLD BIT(1)
570 #define UCLK_VLD BIT(2)
571 #define PCLK_VLD BIT(3)
572 #define PCIRSTB BIT(4)
573 #define V15_VLD BIT(5)
574 #define TRP_B15V_EN BIT(7)
575 #define SIC_IDLE BIT(8)
576 #define BD_MAC2 BIT(9)
577 #define BD_MAC1 BIT(10)
578 #define IC_MACPHY_MODE BIT(11)
579 #define VENDOR_ID BIT(19)
580 #define PAD_HWPD_IDN BIT(22)
581 #define TRP_VAUX_EN BIT(23)
582 #define TRP_BT_EN BIT(24)
583 #define BD_PKG_SEL BIT(25)
584 #define BD_HCI_SEL BIT(26)
585 #define TYPE_ID BIT(27)
587 #define CHIP_VER_RTL_MASK 0xF000
588 #define CHIP_VER_RTL_SHIFT 12
590 #define REG_LBMODE_8822B (REG_CR_8822B + 3)
592 #define HCI_TXDMA_EN BIT(0)
593 #define HCI_RXDMA_EN BIT(1)
594 #define TXDMA_EN BIT(2)
595 #define RXDMA_EN BIT(3)
596 #define PROTOCOL_EN BIT(4)
597 #define SCHEDULE_EN BIT(5)
598 #define MACTXEN BIT(6)
599 #define MACRXEN BIT(7)
600 #define ENSWBCN BIT(8)
603 #define _NETTYPE(x) (((x) & 0x3) << 16)
604 #define MASK_NETTYPE 0x30000
605 #define NT_NO_LINK 0x0
606 #define NT_LINK_AD_HOC 0x1
607 #define NT_LINK_AP 0x2
610 #define _LBMODE(x) (((x) & 0xF) << 24)
611 #define MASK_LBMODE 0xF000000
612 #define LOOPBACK_NORMAL 0x0
613 #define LOOPBACK_IMMEDIATELY 0xB
614 #define LOOPBACK_MAC_DELAY 0x3
615 #define LOOPBACK_PHY 0x1
616 #define LOOPBACK_DMA 0x7
618 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
619 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
620 #define _PSRX_MASK 0xF
621 #define _PSTX_MASK 0xF0
623 #define _PSTX(x) ((x) << 4)
631 #define RXDMA_ARBBW_EN BIT(0)
632 #define RXSHFT_EN BIT(1)
633 #define RXDMA_AGG_EN BIT(2)
634 #define QS_VO_QUEUE BIT(8)
635 #define QS_VI_QUEUE BIT(9)
636 #define QS_BE_QUEUE BIT(10)
637 #define QS_BK_QUEUE BIT(11)
638 #define QS_MANAGER_QUEUE BIT(12)
639 #define QS_HIGH_QUEUE BIT(13)
641 #define HQSEL_VOQ BIT(0)
642 #define HQSEL_VIQ BIT(1)
643 #define HQSEL_BEQ BIT(2)
644 #define HQSEL_BKQ BIT(3)
645 #define HQSEL_MGTQ BIT(4)
646 #define HQSEL_HIQ BIT(5)
648 #define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
649 #define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
650 #define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
651 #define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
652 #define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
653 #define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
656 #define QUEUE_NORMAL 2
659 #define _LLT_NO_ACTIVE 0x0
660 #define _LLT_WRITE_ACCESS 0x1
661 #define _LLT_READ_ACCESS 0x2
663 #define _LLT_INIT_DATA(x) ((x) & 0xFF)
664 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
665 #define _LLT_OP(x) (((x) & 0x3) << 30)
666 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
668 #define BB_WRITE_READ_MASK (BIT(31) | BIT(30))
669 #define BB_WRITE_EN BIT(30)
670 #define BB_READ_EN BIT(31)
672 #define _HPQ(x) ((x) & 0xFF)
673 #define _LPQ(x) (((x) & 0xFF) << 8)
674 #define _PUBQ(x) (((x) & 0xFF) << 16)
675 #define _NPQ(x) ((x) & 0xFF)
677 #define HPQ_PUBLIC_DIS BIT(24)
678 #define LPQ_PUBLIC_DIS BIT(25)
679 #define LD_RQPN BIT(31)
681 #define BCN_VALID BIT(16)
682 #define BCN_HEAD(x) (((x) & 0xFF) << 8)
683 #define BCN_HEAD_MASK 0xFF00
685 #define BLK_DESC_NUM_SHIFT 4
686 #define BLK_DESC_NUM_MASK 0xF
688 #define DROP_DATA_EN BIT(9)
690 #define EN_AMPDU_RTY_NEW BIT(7)
692 #define _INIRTSMCS_SEL(x) ((x) & 0x3F)
694 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
695 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
697 #define RATE_REG_BITMAP_ALL 0xFFFFF
699 #define _RRSC_BITMAP(x) ((x) & 0xFFFFF)
701 #define _RRSR_RSC(x) (((x) & 0x3) << 21)
702 #define RRSR_RSC_RESERVED 0x0
703 #define RRSR_RSC_UPPER_SUBCHANNEL 0x1
704 #define RRSR_RSC_LOWER_SUBCHANNEL 0x2
705 #define RRSR_RSC_DUPLICATE_MODE 0x3
707 #define USE_SHORT_G1 BIT(20)
709 #define _AGGLMT_MCS0(x) ((x) & 0xF)
710 #define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)
711 #define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)
712 #define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)
713 #define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)
714 #define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)
715 #define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)
716 #define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)
718 #define RETRY_LIMIT_SHORT_SHIFT 8
719 #define RETRY_LIMIT_LONG_SHIFT 0
721 #define _DARF_RC1(x) ((x) & 0x1F)
722 #define _DARF_RC2(x) (((x) & 0x1F) << 8)
723 #define _DARF_RC3(x) (((x) & 0x1F) << 16)
724 #define _DARF_RC4(x) (((x) & 0x1F) << 24)
725 #define _DARF_RC5(x) ((x) & 0x1F)
726 #define _DARF_RC6(x) (((x) & 0x1F) << 8)
727 #define _DARF_RC7(x) (((x) & 0x1F) << 16)
728 #define _DARF_RC8(x) (((x) & 0x1F) << 24)
730 #define _RARF_RC1(x) ((x) & 0x1F)
731 #define _RARF_RC2(x) (((x) & 0x1F) << 8)
732 #define _RARF_RC3(x) (((x) & 0x1F) << 16)
733 #define _RARF_RC4(x) (((x) & 0x1F) << 24)
734 #define _RARF_RC5(x) ((x) & 0x1F)
735 #define _RARF_RC6(x) (((x) & 0x1F) << 8)
736 #define _RARF_RC7(x) (((x) & 0x1F) << 16)
737 #define _RARF_RC8(x) (((x) & 0x1F) << 24)
739 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
740 #define AC_PARAM_ECW_MAX_OFFSET 12
741 #define AC_PARAM_ECW_MIN_OFFSET 8
742 #define AC_PARAM_AIFS_OFFSET 0
745 #define _ECW_MAX_MIN(x) ((x) << 8)
746 #define _TXOP_LIMIT(x) ((x) << 16)
748 #define _BCNIFS(x) ((x) & 0xFF)
749 #define _BCNECW(x) ((((x) & 0xF)) << 8)
751 #define _LRL(x) ((x) & 0x3F)
752 #define _SRL(x) (((x) & 0x3F) << 8)
754 #define _SIFS_CCK_CTX(x) ((x) & 0xFF)
755 #define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)
757 #define _SIFS_OFDM_CTX(x) ((x) & 0xFF)
758 #define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)
760 #define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)
762 #define DIS_EDCA_CNT_DWN BIT(11)
764 #define EN_MBSSID BIT(1)
765 #define EN_TXBCN_RPT BIT(2)
766 #define EN_BCN_FUNCTION BIT(3)
768 #define TSFTR_RST BIT(0)
769 #define TSFTR1_RST BIT(1)
771 #define STOP_BCNQ BIT(6)
773 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
774 #define DIS_TSF_UDT0_TEST_CHIP BIT(5)
776 #define ACMHW_HW_EN BIT(0)
777 #define ACMHW_BEQ_EN BIT(1)
778 #define ACMHW_VIQ_EN BIT(2)
779 #define ACMHW_VOQ_EN BIT(3)
780 #define ACMHW_BEQ_STATUS BIT(4)
781 #define ACMHW_VIQ_STATUS BIT(5)
782 #define ACMHW_VOQ_STATUS BIT(6)
784 #define APSDOFF BIT(6)
785 #define APSDOFF_STATUS BIT(7)
787 #define BW_20MHZ BIT(2)
789 #define RATE_BITMAP_ALL 0xFFFFF
791 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
793 #define TSFRST BIT(0)
794 #define DIS_GCLK BIT(1)
795 #define PAD_SEL BIT(2)
796 #define PWR_ST BIT(6)
797 #define PWRBIT_OW_EN BIT(7)
799 #define CFENDFORM BIT(9)
807 #define APWRMGT BIT(5)
808 #define CBSSID BIT(6)
809 #define CBSSID_DATA BIT(6)
810 #define CBSSID_BCN BIT(7)
811 #define ACRC32 BIT(8)
816 #define HTC_LOC_CTRL BIT(14)
817 #define UC_DATA_EN BIT(16)
818 #define BM_DATA_EN BIT(17)
819 #define MFBEN BIT(22)
820 #define LSIGEN BIT(23)
821 #define EN_MBID BIT(24)
822 #define APP_BASSN BIT(27)
823 #define APP_PHYSTS BIT(28)
824 #define APP_ICV BIT(29)
825 #define APP_MIC BIT(30)
826 #define APP_FCS BIT(31)
828 #define _MIN_SPACE(x) ((x) & 0x7)
829 #define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)
831 #define RXERR_TYPE_OFDM_PPDU 0
832 #define RXERR_TYPE_OFDM_FALSE_ALARM 1
833 #define RXERR_TYPE_OFDM_MPDU_OK 2
834 #define RXERR_TYPE_OFDM_MPDU_FAIL 3
835 #define RXERR_TYPE_CCK_PPDU 4
836 #define RXERR_TYPE_CCK_FALSE_ALARM 5
837 #define RXERR_TYPE_CCK_MPDU_OK 6
838 #define RXERR_TYPE_CCK_MPDU_FAIL 7
839 #define RXERR_TYPE_HT_PPDU 8
840 #define RXERR_TYPE_HT_FALSE_ALARM 9
841 #define RXERR_TYPE_HT_MPDU_TOTAL 10
842 #define RXERR_TYPE_HT_MPDU_OK 11
843 #define RXERR_TYPE_HT_MPDU_FAIL 12
844 #define RXERR_TYPE_RX_FULL_DROP 15
846 #define RXERR_COUNTER_MASK 0xFFFFF
847 #define RXERR_RPT_RST BIT(27)
848 #define _RXERR_RPT_SEL(type) ((type) << 28)
850 #define SCR_TX_USE_DK BIT(0)
851 #define SCR_RX_USE_DK BIT(1)
852 #define SCR_TX_ENC_ENABLE BIT(2)
853 #define SRC_RX_DEC_ENABLE BIT(3)
854 #define SCR_SK_BY_A2 BIT(4)
855 #define SCR_NO_SKMC BIT(5)
856 #define SCR_TXBCUSEDK BIT(6)
857 #define SCR_RXBCUSEDK BIT(7)
859 #define USB_IS_HIGH_SPEED 0
860 #define USB_IS_FULL_SPEED 1
861 #define USB_SPEED_MASK BIT(5)
863 #define USB_NORMAL_SIE_EP_MASK 0xF
864 #define USB_NORMAL_SIE_EP_SHIFT 4
866 #define USB_TEST_EP_MASK 0x30
867 #define USB_TEST_EP_SHIFT 4
869 #define USB_AGG_EN BIT(3)
871 #define MAC_ADDR_LEN 6
872 #define LAST_ENTRY_OF_TX_PKT_BUFFER 175
874 #define POLLING_LLT_THRESHOLD 20
875 #define POLLING_READY_TIMEOUT_COUNT 3000
877 #define MAX_MSS_DENSITY_2T 0x13
878 #define MAX_MSS_DENSITY_1T 0x0A
880 #define EPROM_CMD_OPERATING_MODE_MASK ((1 << 7) | (1 << 6))
881 #define EPROM_CMD_CONFIG 0x3
882 #define EPROM_CMD_LOAD 1
884 #define HAL_8822B_HW_GPIO_WPS_BIT BIT(2)
886 /*-----------------------------------------------------
888 *-----------------------------------------------------
891 #define RFPGA0_XA_HSSIPARAMETER1 0x820
892 #define RFPGA0_XA_HSSIPARAMETER2 0x824
893 #define RFPGA0_XB_HSSIPARAMETER1 0x828
894 #define RFPGA0_XB_HSSIPARAMETER2 0x82c
895 #define RCCAONSEC 0x838
897 #define RFPGA0_XA_LSSIPARAMETER 0x840
898 #define RFPGA0_XB_LSSIPARAMETER 0x844
899 #define RL1PEAKTH 0x848
901 #define RFPGA0_RFWAKEUPPARAMETER 0x850
902 #define RFPGA0_RFSLEEPUPPARAMETER 0x854
904 #define RFPGA0_XAB_SWITCHCONTROL 0x858
905 #define RFPGA0_XCD_SWITCHCONTROL 0x85c
907 #define RFPGA0_XA_RFINTERFACEOE 0x860
908 #define RFC_AREA 0x860
909 #define RFPGA0_XB_RFINTERFACEOE 0x864
911 #define RFPGA0_XAB_RFINTERFACESW 0x870
912 #define RFPGA0_XCD_RFINTERFACESW 0x874
914 #define RFPGA0_XAB_RF_PARA_METER 0x878
915 #define RFPGA0_XCD_RF_PARA_METER 0x87c
917 #define RFPGA0_ANALOGPARAMETER1 0x880
918 #define RFPGA0_ANALOGPARAMETER2 0x884
919 #define RFPGA0_ANALOGPARAMETER3 0x888
920 #define RFPGA0_ANALOGPARAMETER4 0x88c
922 #define RFPGA0_XA_LSSIREADBACK 0x8a0
923 #define RFPGA0_XB_LSSIREADBACK 0x8a4
924 #define RFPGA0_XC_LSSIREADBACK 0x8a8
925 /*#define RFPGA0_XD_LSSIREADBACK 0x8ac*/
927 #define RHSSIREAD_8822BE 0x8b0
929 #define RFPGA0_PSDREPORT 0x8b4
930 #define TRANSCEIVEA_HSPI_READBACK 0x8b8
931 #define TRANSCEIVEB_HSPI_READBACK 0x8bc
932 /*#define REG_SC_CNT_8822B 0x8c4*/
933 #define RADC_BUF_CLK 0x8c4
934 #define RFPGA0_XAB_RFINTERFACERB 0x8e0
935 #define RFPGA0_XCD_RFINTERFACERB 0x8e4
941 #define RA_TXPWRTRAING 0xc54
942 #define RB_TXPWRTRAING 0xe54
944 #define RA_LSSIWRITE_8822B 0xc90
945 #define RB_LSSIWRITE_8822B 0xe90
947 #define RA_PIREAD_8822B 0xd04
948 #define RB_PIREAD_8822B 0xd44
949 #define RA_SIREAD_8822B 0xd08
950 #define RB_SIREAD_8822B 0xd48
952 #define RZEBRA1_HSSIENABLE 0x0
953 #define RZEBRA1_TRXENABLE1 0x1
954 #define RZEBRA1_TRXENABLE2 0x2
955 #define RZEBRA1_AGC 0x4
956 #define RZEBRA1_CHARGEPUMP 0x5
957 #define RZEBRA1_CHANNEL 0x7
959 #define RZEBRA1_TXGAIN 0x8
960 #define RZEBRA1_TXLPF 0x9
961 #define RZEBRA1_RXLPF 0xb
962 #define RZEBRA1_RXHPFCORNER 0xc
964 #define RGLOBALCTRL 0
965 #define RRTL8256_TXLPF 19
966 #define RRTL8256_RXLPF 11
967 #define RRTL8258_TXLPF 0x11
968 #define RRTL8258_RXLPF 0x13
969 #define RRTL8258_RSSILPF 0xa
973 #define RF_IQADJ_G1 0x01
974 #define RF_IQADJ_G2 0x02
975 #define RF_POW_TRSW 0x05
977 #define RF_GAIN_RX 0x06
978 #define RF_GAIN_TX 0x07
980 #define RF_TXM_IDAC 0x08
981 #define RF_BS_IQGEN 0x0F
983 #define RF_MODE1 0x10
984 #define RF_MODE2 0x11
986 #define RF_RX_AGC_HP 0x12
987 #define RF_TX_AGC 0x13
990 #define RF_POW_ABILITY 0x17
991 #define RF_MODE_AG 0x18
992 #define RRFCHANNEL 0x18
993 #define RF_CHNLBW 0x18
996 #define RF_RX_G1 0x1A
997 #define RF_RX_G2 0x1B
999 #define RF_RX_BB2 0x1C
1000 #define RF_RX_BB1 0x1D
1002 #define RF_RCK1 0x1E
1003 #define RF_RCK2 0x1F
1005 #define RF_TX_G1 0x20
1006 #define RF_TX_G2 0x21
1007 #define RF_TX_G3 0x22
1009 #define RF_TX_BB1 0x23
1010 #define RF_T_METER 0x42
1012 #define RF_SYN_G1 0x25
1013 #define RF_SYN_G2 0x26
1014 #define RF_SYN_G3 0x27
1015 #define RF_SYN_G4 0x28
1016 #define RF_SYN_G5 0x29
1017 #define RF_SYN_G6 0x2A
1018 #define RF_SYN_G7 0x2B
1019 #define RF_SYN_G8 0x2C
1021 #define RF_RCK_OS 0x30
1022 #define RF_TXPA_G1 0x31
1023 #define RF_TXPA_G2 0x32
1024 #define RF_TXPA_G3 0x33
1026 #define RF_TX_BIAS_A 0x35
1027 #define RF_TX_BIAS_D 0x36
1028 #define RF_LOBF_9 0x38
1029 #define RF_RXRF_A3 0x3C
1030 #define RF_TRSW 0x3F
1032 #define RF_TXRF_A2 0x41
1033 #define RF_TXPA_G4 0x46
1034 #define RF_TXPA_A4 0x4B
1038 #define RF_WE_LUT 0xEF
1040 #define BBBRESETB 0x100
1041 #define BGLOBALRESETB 0x200
1042 #define BOFDMTXSTART 0x4
1043 #define BCCKTXSTART 0x8
1044 #define BCRC32DEBUG 0x100
1045 #define BPMACLOOPBACK 0x10
1046 #define BTXLSIG 0xffffff
1047 #define BOFDMTXRATE 0xf
1048 #define BOFDMTXRESERVED 0x10
1049 #define BOFDMTXLENGTH 0x1ffe0
1050 #define BOFDMTXPARITY 0x20000
1051 #define BTXHTSIG1 0xffffff
1052 #define BTXHTMCSRATE 0x7f
1053 #define BTXHTBW 0x80
1054 #define BTXHTLENGTH 0xffff00
1055 #define BTXHTSIG2 0xffffff
1056 #define BTXHTSMOOTHING 0x1
1057 #define BTXHTSOUNDING 0x2
1058 #define BTXHTRESERVED 0x4
1059 #define BTXHTAGGREATION 0x8
1060 #define BTXHTSTBC 0x30
1061 #define BTXHTADVANCECODING 0x40
1062 #define BTXHTSHORTGI 0x80
1063 #define BTXHTNUMBERHT_LTF 0x300
1064 #define BTXHTCRC8 0x3fc00
1065 #define BCOUNTERRESET 0x10000
1066 #define BNUMOFOFDMTX 0xffff
1067 #define BNUMOFCCKTX 0xffff0000
1068 #define BTXIDLEINTERVAL 0xffff
1069 #define BOFDMSERVICE 0xffff0000
1070 #define BTXMACHEADER 0xffffffff
1071 #define BTXDATAINIT 0xff
1072 #define BTXHTMODE 0x100
1073 #define BTXDATATYPE 0x30000
1074 #define BTXRANDOMSEED 0xffffffff
1075 #define BCCKTXPREAMBLE 0x1
1076 #define BCCKTXSFD 0xffff0000
1077 #define BCCKTXSIG 0xff
1078 #define BCCKTXSERVICE 0xff00
1079 #define BCCKLENGTHEXT 0x8000
1080 #define BCCKTXLENGHT 0xffff0000
1081 #define BCCKTXCRC16 0xffff
1082 #define BCCKTXSTATUS 0x1
1083 #define BOFDMTXSTATUS 0x2
1084 #define IS_BB_REG_OFFSET_92S(_offset) ((_offset >= 0x800) && (_offset <= 0xfff))
1087 #define BJAPANMODE 0x2
1088 #define BCCKTXSC 0x30
1089 /* Block & Path enable*/
1090 #define ROFDMCCKEN 0x808
1091 #define BCCKEN 0x10000000
1092 #define BOFDMEN 0x20000000
1094 #define RRXPATH 0x808
1095 #define BRXPATH 0xff
1097 #define RTXPATH 0x80c
1098 #define BTXPATH 0x0fffffff
1099 /* for cck rx path selection*/
1100 #define RCCK_RX 0xa04
1101 #define BCCK_RX 0x0c000000
1102 /* Use LSIG for VHT length*/
1103 #define RVHTLEN_USE_LSIG 0x8c3
1105 #define BOFDMRXADCPHASE 0x10000
1106 #define BOFDMTXDACPHASE 0x40000
1107 #define BXATXAGC 0x3f
1109 #define BXBTXAGC 0xf00
1110 #define BXCTXAGC 0xf000
1111 #define BXDTXAGC 0xf0000
1113 #define BPASTART 0xf0000000
1114 #define BTRSTART 0x00f00000
1115 #define BRFSTART 0x0000f000
1116 #define BBBSTART 0x000000f0
1117 #define BBBCCKSTART 0x0000000f
1119 #define BTREND 0x0f000000
1120 #define BRFEND 0x000f0000
1121 #define BCCAMASK 0x000000f0
1122 #define BR2RCCAMASK 0x00000f00
1123 #define BHSSI_R2TDELAY 0xf8000000
1124 #define BHSSI_T2RDELAY 0xf80000
1125 #define BCONTXHSSI 0x400
1126 #define BIGFROMCCK 0x200
1127 #define BAGCADDRESS 0x3f
1128 #define BRXHPTX 0x7000
1129 #define BRXHP2RX 0x38000
1130 #define BRXHPCCKINI 0xc0000
1131 #define BAGCTXCODE 0xc00000
1132 #define BAGCRXCODE 0x300000
1134 #define B3WIREDATALENGTH 0x800
1135 #define B3WIREADDREAALENGTH 0x400
1137 #define B3WIRERFPOWERDOWN 0x1
1138 #define B5GPAPEPOLARITY 0x40000000
1139 #define B2GPAPEPOLARITY 0x80000000
1140 #define BRFSW_TXDEFAULTANT 0x3
1141 #define BRFSW_TXOPTIONANT 0x30
1142 #define BRFSW_RXDEFAULTANT 0x300
1143 #define BRFSW_RXOPTIONANT 0x3000
1144 #define BRFSI_3WIREDATA 0x1
1145 #define BRFSI_3WIRECLOCK 0x2
1146 #define BRFSI_3WIRELOAD 0x4
1147 #define BRFSI_3WIRERW 0x8
1148 #define BRFSI_3WIRE 0xf
1150 #define BRFSI_RFENV 0x10
1152 #define BRFSI_TRSW 0x20
1153 #define BRFSI_TRSWB 0x40
1154 #define BRFSI_ANTSW 0x100
1155 #define BRFSI_ANTSWB 0x200
1156 #define BRFSI_PAPE 0x400
1157 #define BRFSI_PAPE5G 0x800
1158 #define BBANDSELECT 0x1
1159 #define BHTSIG2_GI 0x80
1160 #define BHTSIG2_SMOOTHING 0x01
1161 #define BHTSIG2_SOUNDING 0x02
1162 #define BHTSIG2_AGGREATON 0x08
1163 #define BHTSIG2_STBC 0x30
1164 #define BHTSIG2_ADVCODING 0x40
1165 #define BHTSIG2_NUMOFHTLTF 0x300
1166 #define BHTSIG2_CRC8 0x3fc
1167 #define BHTSIG1_MCS 0x7f
1168 #define BHTSIG1_BANDWIDTH 0x80
1169 #define BHTSIG1_HTLENGTH 0xffff
1170 #define BLSIG_RATE 0xf
1171 #define BLSIG_RESERVED 0x10
1172 #define BLSIG_LENGTH 0x1fffe
1173 #define BLSIG_PARITY 0x20
1174 #define BCCKRXPHASE 0x4
1176 #define BLSSIREADADDRESS 0x7f800000
1177 #define BLSSIREADEDGE 0x80000000
1179 #define BLSSIREADBACKDATA 0xfffff
1181 #define BLSSIREADOKFLAG 0x1000
1182 #define BCCKSAMPLERATE 0x8
1183 #define BREGULATOR0STANDBY 0x1
1184 #define BREGULATORPLLSTANDBY 0x2
1185 #define BREGULATOR1STANDBY 0x4
1186 #define BPLLPOWERUP 0x8
1187 #define BDPLLPOWERUP 0x10
1188 #define BDA10POWERUP 0x20
1189 #define BAD7POWERUP 0x200
1190 #define BDA6POWERUP 0x2000
1191 #define BXTALPOWERUP 0x4000
1192 #define B40MDCLKPOWERUP 0x8000
1193 #define BDA6DEBUGMODE 0x20000
1194 #define BDA6SWING 0x380000
1196 #define BADCLKPHASE 0x4000000
1197 #define B80MCLKDELAY 0x18000000
1198 #define BAFEWATCHDOGENABLE 0x20000000
1200 #define BXTALCAP01 0xc0000000
1201 #define BXTALCAP23 0x3
1202 #define BXTALCAP92X 0x0f000000
1203 #define BXTALCAP 0x0f000000
1205 #define BINTDIFCLKENABLE 0x400
1206 #define BEXTSIGCLKENABLE 0x800
1207 #define BBANDGAP_MBIAS_POWERUP 0x10000
1208 #define BAD11SH_GAIN 0xc0000
1209 #define BAD11NPUT_RANGE 0x700000
1210 #define BAD110P_CURRENT 0x3800000
1211 #define BLPATH_LOOPBACK 0x4000000
1212 #define BQPATH_LOOPBACK 0x8000000
1213 #define BAFE_LOOPBACK 0x10000000
1214 #define BDA10_SWING 0x7e0
1215 #define BDA10_REVERSE 0x800
1216 #define BDA_CLK_SOURCE 0x1000
1217 #define BDA7INPUT_RANGE 0x6000
1218 #define BDA7_GAIN 0x38000
1219 #define BDA7OUTPUT_CM_MODE 0x40000
1220 #define BDA7INPUT_CM_MODE 0x380000
1221 #define BDA7CURRENT 0xc00000
1222 #define BREGULATOR_ADJUST 0x7000000
1223 #define BAD11POWERUP_ATTX 0x1
1224 #define BDA10PS_ATTX 0x10
1225 #define BAD11POWERUP_ATRX 0x100
1226 #define BDA10PS_ATRX 0x1000
1227 #define BCCKRX_AGC_FORMAT 0x200
1228 #define BPSDFFT_SAMPLE_POINT 0xc000
1229 #define BPSD_AVERAGE_NUM 0x3000
1230 #define BIQPATH_CONTROL 0xc00
1231 #define BPSD_FREQ 0x3ff
1232 #define BPSD_ANTENNA_PATH 0x30
1233 #define BPSD_IQ_SWITCH 0x40
1234 #define BPSD_RX_TRIGGER 0x400000
1235 #define BPSD_TX_TRIGGER 0x80000000
1236 #define BPSD_SINE_TONE_SCALE 0x7f000000
1237 #define BPSD_REPORT 0xffff
1239 #define BOFDM_TXSC 0x30000000
1240 #define BCCK_TXON 0x1
1241 #define BOFDM_TXON 0x2
1242 #define BDEBUG_PAGE 0xfff
1243 #define BDEBUG_ITEM 0xff
1245 #define BANT_NONHT 0x100
1246 #define BANT_HT1 0x1000
1247 #define BANT_HT2 0x10000
1248 #define BANT_HT1S1 0x100000
1249 #define BANT_NONHTS1 0x1000000
1251 #define BCCK_BBMODE 0x3
1252 #define BCCK_TXPOWERSAVING 0x80
1253 #define BCCK_RXPOWERSAVING 0x40
1255 #define BCCK_SIDEBAND 0x10
1257 #define BCCK_SCRAMBLE 0x8
1258 #define BCCK_ANTDIVERSITY 0x8000
1259 #define BCCK_CARRIER_RECOVERY 0x4000
1260 #define BCCK_TXRATE 0x3000
1261 #define BCCK_DCCANCEL 0x0800
1262 #define BCCK_ISICANCEL 0x0400
1263 #define BCCK_MATCH_FILTER 0x0200
1264 #define BCCK_EQUALIZER 0x0100
1265 #define BCCK_PREAMBLE_DETECT 0x800000
1266 #define BCCK_FAST_FALSECCA 0x400000
1267 #define BCCK_CH_ESTSTART 0x300000
1268 #define BCCK_CCA_COUNT 0x080000
1269 #define BCCK_CS_LIM 0x070000
1270 #define BCCK_BIST_MODE 0x80000000
1271 #define BCCK_CCAMASK 0x40000000
1272 #define BCCK_TX_DAC_PHASE 0x4
1273 #define BCCK_RX_ADC_PHASE 0x20000000
1274 #define BCCKR_CP_MODE 0x0100
1275 #define BCCK_TXDC_OFFSET 0xf0
1276 #define BCCK_RXDC_OFFSET 0xf
1277 #define BCCK_CCA_MODE 0xc000
1278 #define BCCK_FALSECS_LIM 0x3f00
1279 #define BCCK_CS_RATIO 0xc00000
1280 #define BCCK_CORGBIT_SEL 0x300000
1281 #define BCCK_PD_LIM 0x0f0000
1282 #define BCCK_NEWCCA 0x80000000
1283 #define BCCK_RXHP_OF_IG 0x8000
1284 #define BCCK_RXIG 0x7f00
1285 #define BCCK_LNA_POLARITY 0x800000
1286 #define BCCK_RX1ST_BAIN 0x7f0000
1287 #define BCCK_RF_EXTEND 0x20000000
1288 #define BCCK_RXAGC_SATLEVEL 0x1f000000
1289 #define BCCK_RXAGC_SATCOUNT 0xe0
1290 #define BCCK_RX_RF_SETTLE 0x1f
1291 #define BCCK_FIXED_RXAGC 0x8000
1292 #define BCCK_ANTENNA_POLARITY 0x2000
1293 #define BCCK_TXFILTER_TYPE 0x0c00
1294 #define BCCK_RXAGC_REPORTTYPE 0x0300
1295 #define BCCK_RXDAGC_EN 0x80000000
1296 #define BCCK_RXDAGC_PERIOD 0x20000000
1297 #define BCCK_RXDAGC_SATLEVEL 0x1f000000
1298 #define BCCK_TIMING_RECOVERY 0x800000
1299 #define BCCK_TXC0 0x3f0000
1300 #define BCCK_TXC1 0x3f000000
1301 #define BCCK_TXC2 0x3f
1302 #define BCCK_TXC3 0x3f00
1303 #define BCCK_TXC4 0x3f0000
1304 #define BCCK_TXC5 0x3f000000
1305 #define BCCK_TXC6 0x3f
1306 #define BCCK_TXC7 0x3f00
1307 #define BCCK_DEBUGPORT 0xff0000
1308 #define BCCK_DAC_DEBUG 0x0f000000
1309 #define BCCK_FALSEALARM_ENABLE 0x8000
1310 #define BCCK_FALSEALARM_READ 0x4000
1311 #define BCCK_TRSSI 0x7f
1312 #define BCCK_RXAGC_REPORT 0xfe
1313 #define BCCK_RXREPORT_ANTSEL 0x80000000
1314 #define BCCK_RXREPORT_MFOFF 0x40000000
1315 #define BCCK_RXREPORT_SQLOSS 0x20000000
1316 #define BCCK_RXREPORT_PKTLOSS 0x10000000
1317 #define BCCK_RXREPORT_LOCKEDBIT 0x08000000
1318 #define BCCK_RXREPORT_RATEERROR 0x04000000
1319 #define BCCK_RXREPORT_RXRATE 0x03000000
1320 #define BCCK_RXFA_COUNTER_LOWER 0xff
1321 #define BCCK_RXFA_COUNTER_UPPER 0xff000000
1322 #define BCCK_RXHPAGC_START 0xe000
1323 #define BCCK_RXHPAGC_FINAL 0x1c00
1324 #define BCCK_RXFALSEALARM_ENABLE 0x8000
1325 #define BCCK_FACOUNTER_FREEZE 0x4000
1326 #define BCCK_TXPATH_SEL 0x10000000
1327 #define BCCK_DEFAULT_RXPATH 0xc000000
1328 #define BCCK_OPTION_RXPATH 0x3000000
1330 #define BNUM_OFSTF 0x3
1331 #define BSHIFT_L 0xc0
1333 #define BRXPATH_A 0x1
1334 #define BRXPATH_B 0x2
1335 #define BRXPATH_C 0x4
1336 #define BRXPATH_D 0x8
1337 #define BTXPATH_A 0x1
1338 #define BTXPATH_B 0x2
1339 #define BTXPATH_C 0x4
1340 #define BTXPATH_D 0x8
1341 #define BTRSSI_FREQ 0x200
1342 #define BADC_BACKOFF 0x3000
1343 #define BDFIR_BACKOFF 0xc000
1344 #define BTRSSI_LATCH_PHASE 0x10000
1345 #define BRX_LDC_OFFSET 0xff
1346 #define BRX_QDC_OFFSET 0xff00
1347 #define BRX_DFIR_MODE 0x1800000
1348 #define BRX_DCNF_TYPE 0xe000000
1349 #define BRXIQIMB_A 0x3ff
1350 #define BRXIQIMB_B 0xfc00
1351 #define BRXIQIMB_C 0x3f0000
1352 #define BRXIQIMB_D 0xffc00000
1353 #define BDC_DC_NOTCH 0x60000
1354 #define BRXNB_NOTCH 0x1f000000
1356 #define BPD_TH_OPT2 0xc000
1357 #define BPWED_TH 0x700
1358 #define BIFMF_WIN_L 0x800
1359 #define BPD_OPTION 0x1000
1360 #define BMF_WIN_L 0xe000
1361 #define BBW_SEARCH_L 0x30000
1362 #define BWIN_ENH_L 0xc0000
1363 #define BBW_TH 0x700000
1364 #define BED_TH2 0x3800000
1365 #define BBW_OPTION 0x4000000
1366 #define BRADIO_TH 0x18000000
1367 #define BWINDOW_L 0xe0000000
1368 #define BSBD_OPTION 0x1
1369 #define BFRAME_TH 0x1c
1370 #define BFS_OPTION 0x60
1371 #define BDC_SLOPE_CHECK 0x80
1372 #define BFGUARD_COUNTER_DC_L 0xe00
1373 #define BFRAME_WEIGHT_SHORT 0x7000
1374 #define BSUB_TUNE 0xe00000
1375 #define BFRAME_DC_LENGTH 0xe000000
1376 #define BSBD_START_OFFSET 0x30000000
1377 #define BFRAME_TH_2 0x7
1378 #define BFRAME_GI2_TH 0x38
1379 #define BGI2_SYNC_EN 0x40
1380 #define BSARCH_SHORT_EARLY 0x300
1381 #define BSARCH_SHORT_LATE 0xc00
1382 #define BSARCH_GI2_LATE 0x70000
1383 #define BCFOANTSUM 0x1
1385 #define BCFOSTARTOFFSET 0xc
1386 #define BCFOLOOPBACK 0x70
1387 #define BCFOSUMWEIGHT 0x80
1388 #define BDAGCENABLE 0x10000
1389 #define BTXIQIMB_A 0x3ff
1390 #define BTXIQIMB_b 0xfc00
1391 #define BTXIQIMB_C 0x3f0000
1392 #define BTXIQIMB_D 0xffc00000
1393 #define BTXIDCOFFSET 0xff
1394 #define BTXIQDCOFFSET 0xff00
1395 #define BTXDFIRMODE 0x10000
1396 #define BTXPESUDO_NOISEON 0x4000000
1397 #define BTXPESUDO_NOISE_A 0xff
1398 #define BTXPESUDO_NOISE_B 0xff00
1399 #define BTXPESUDO_NOISE_C 0xff0000
1400 #define BTXPESUDO_NOISE_D 0xff000000
1401 #define BCCA_DROPOPTION 0x20000
1402 #define BCCA_DROPTHRES 0xfff00000
1403 #define BEDCCA_H 0xf
1404 #define BEDCCA_L 0xf0
1405 #define BLAMBDA_ED 0x300
1406 #define BRX_INITIALGAIN 0x7f
1407 #define BRX_ANTDIV_EN 0x80
1408 #define BRX_AGC_ADDRESS_FOR_LNA 0x7f00
1409 #define BRX_HIGHPOWER_FLOW 0x8000
1410 #define BRX_AGC_FREEZE_THRES 0xc0000
1411 #define BRX_FREEZESTEP_AGC1 0x300000
1412 #define BRX_FREEZESTEP_AGC2 0xc00000
1413 #define BRX_FREEZESTEP_AGC3 0x3000000
1414 #define BRX_FREEZESTEP_AGC0 0xc000000
1415 #define BRXRSSI_CMP_EN 0x10000000
1416 #define BRXQUICK_AGCEN 0x20000000
1417 #define BRXAGC_FREEZE_THRES_MODE 0x40000000
1418 #define BRX_OVERFLOW_CHECKTYPE 0x80000000
1419 #define BRX_AGCSHIFT 0x7f
1420 #define BTRSW_TRI_ONLY 0x80
1421 #define BPOWER_THRES 0x300
1422 #define BRXAGC_EN 0x1
1423 #define BRXAGC_TOGETHER_EN 0x2
1424 #define BRXAGC_MIN 0x4
1425 #define BRXHP_INI 0x7
1426 #define BRXHP_TRLNA 0x70
1427 #define BRXHP_RSSI 0x700
1428 #define BRXHP_BBP1 0x7000
1429 #define BRXHP_BBP2 0x70000
1430 #define BRXHP_BBP3 0x700000
1431 #define BRSSI_H 0x7f0000
1432 #define BRSSI_GEN 0x7f000000
1433 #define BRXSETTLE_TRSW 0x7
1434 #define BRXSETTLE_LNA 0x38
1435 #define BRXSETTLE_RSSI 0x1c0
1436 #define BRXSETTLE_BBP 0xe00
1437 #define BRXSETTLE_RXHP 0x7000
1438 #define BRXSETTLE_ANTSW_RSSI 0x38000
1439 #define BRXSETTLE_ANTSW 0xc0000
1440 #define BRXPROCESS_TIME_DAGC 0x300000
1441 #define BRXSETTLE_HSSI 0x400000
1442 #define BRXPROCESS_TIME_BBPPW 0x800000
1443 #define BRXANTENNA_POWER_SHIFT 0x3000000
1444 #define BRSSI_TABLE_SELECT 0xc000000
1445 #define BRXHP_FINAL 0x7000000
1446 #define BRXHPSETTLE_BBP 0x7
1447 #define BRXHTSETTLE_HSSI 0x8
1448 #define BRXHTSETTLE_RXHP 0x70
1449 #define BRXHTSETTLE_BBPPW 0x80
1450 #define BRXHTSETTLE_IDLE 0x300
1451 #define BRXHTSETTLE_RESERVED 0x1c00
1452 #define BRXHT_RXHP_EN 0x8000
1453 #define BRXAGC_FREEZE_THRES 0x30000
1454 #define BRXAGC_TOGETHEREN 0x40000
1455 #define BRXHTAGC_MIN 0x80000
1456 #define BRXHTAGC_EN 0x100000
1457 #define BRXHTDAGC_EN 0x200000
1458 #define BRXHT_RXHP_BBP 0x1c00000
1459 #define BRXHT_RXHP_FINAL 0xe0000000
1460 #define BRXPW_RADIO_TH 0x3
1461 #define BRXPW_RADIO_EN 0x4
1462 #define BRXMF_HOLD 0x3800
1463 #define BRXPD_DELAY_TH1 0x38
1464 #define BRXPD_DELAY_TH2 0x1c0
1465 #define BRXPD_DC_COUNT_MAX 0x600
1466 #define BRXPD_DELAY_TH 0x8000
1467 #define BRXPROCESS_DELAY 0xf0000
1468 #define BRXSEARCHRANGE_GI2_EARLY 0x700000
1469 #define BRXFRAME_FUARD_COUNTER_L 0x3800000
1470 #define BRXSGI_GUARD_L 0xc000000
1471 #define BRXSGI_SEARCH_L 0x30000000
1472 #define BRXSGI_TH 0xc0000000
1473 #define BDFSCNT0 0xff
1474 #define BDFSCNT1 0xff00
1475 #define BDFSFLAG 0xf0000
1476 #define BMF_WEIGHT_SUM 0x300000
1477 #define BMINIDX_TH 0x7f000000
1478 #define BDAFORMAT 0x40000
1479 #define BTXCH_EMU_ENABLE 0x01000000
1480 #define BTRSW_ISOLATION_A 0x7f
1481 #define BTRSW_ISOLATION_B 0x7f00
1482 #define BTRSW_ISOLATION_C 0x7f0000
1483 #define BTRSW_ISOLATION_D 0x7f000000
1484 #define BEXT_LNA_GAIN 0x7c00
1486 #define BSTBC_EN 0x4
1487 #define BANTENNA_MAPPING 0x10
1489 #define BCFO_ANTSUM_ID 0x200
1490 #define BPHY_COUNTER_RESET 0x8000000
1491 #define BCFO_REPORT_GET 0x4000000
1492 #define BOFDM_CONTINUE_TX 0x10000000
1493 #define BOFDM_SINGLE_CARRIER 0x20000000
1494 #define BOFDM_SINGLE_TONE 0x40000000
1495 #define BHT_DETECT 0x100
1496 #define BCFOEN 0x10000
1497 #define BCFOVALUE 0xfff00000
1498 #define BSIGTONE_RE 0x3f
1499 #define BSIGTONE_IM 0x7f00
1500 #define BCOUNTER_CCA 0xffff
1501 #define BCOUNTER_PARITYFAIL 0xffff0000
1502 #define BCOUNTER_RATEILLEGAL 0xffff
1503 #define BCOUNTER_CRC8FAIL 0xffff0000
1504 #define BCOUNTER_MCSNOSUPPORT 0xffff
1505 #define BCOUNTER_FASTSYNC 0xffff
1506 #define BSHORTCFO 0xfff
1507 #define BSHORTCFOT_LENGTH 12
1508 #define BSHORTCFOF_LENGTH 11
1509 #define BLONGCFO 0x7ff
1510 #define BLONGCFOT_LENGTH 11
1511 #define BLONGCFOF_LENGTH 11
1512 #define BTAILCFO 0x1fff
1513 #define BTAILCFOT_LENGTH 13
1514 #define BTAILCFOF_LENGTH 12
1515 #define BNOISE_EN_PWDB 0xffff
1516 #define BCC_POWER_DB 0xffff0000
1517 #define BMOISE_PWDB 0xffff
1518 #define BPOWERMEAST_LENGTH 10
1519 #define BPOWERMEASF_LENGTH 3
1520 #define BRX_HT_BW 0x1
1523 #define BNB_INTF_DET_ON 0x1
1524 #define BINTF_WIN_LEN_CFG 0x30
1525 #define BNB_INTF_TH_CFG 0x1c0
1526 #define BRFGAIN 0x3f
1527 #define BTABLESEL 0x40
1529 #define BRXSNR_A 0xff
1530 #define BRXSNR_B 0xff00
1531 #define BRXSNR_C 0xff0000
1532 #define BRXSNR_D 0xff000000
1533 #define BSNR_EVMT_LENGTH 8
1534 #define BSNR_EVMF_LENGTH 1
1535 #define BCSI1ST 0xff
1536 #define BCSI2ND 0xff00
1537 #define BRXEVM1ST 0xff0000
1538 #define BRXEVM2ND 0xff000000
1539 #define BSIGEVM 0xff
1540 #define BPWDB 0xff00
1541 #define BSGIEN 0x10000
1543 #define BSFACTOR_QMA1 0xf
1544 #define BSFACTOR_QMA2 0xf0
1545 #define BSFACTOR_QMA3 0xf00
1546 #define BSFACTOR_QMA4 0xf000
1547 #define BSFACTOR_QMA5 0xf0000
1548 #define BSFACTOR_QMA6 0xf0000
1549 #define BSFACTOR_QMA7 0xf00000
1550 #define BSFACTOR_QMA8 0xf000000
1551 #define BSFACTOR_QMA9 0xf0000000
1552 #define BCSI_SCHEME 0x100000
1554 #define BNOISE_LVL_TOP_SET 0x3
1555 #define BCHSMOOTH 0x4
1556 #define BCHSMOOTH_CFG1 0x38
1557 #define BCHSMOOTH_CFG2 0x1c0
1558 #define BCHSMOOTH_CFG3 0xe00
1559 #define BCHSMOOTH_CFG4 0x7000
1560 #define BMRCMODE 0x800000
1561 #define BTHEVMCFG 0x7000000
1563 #define BLOOP_FIT_TYPE 0x1
1564 #define BUPD_CFO 0x40
1565 #define BUPD_CFO_OFFDATA 0x80
1566 #define BADV_UPD_CFO 0x100
1567 #define BADV_TIME_CTRL 0x800
1568 #define BUPD_CLKO 0x1000
1570 #define BTRACKING_MODE 0x8000
1571 #define BPHCMP_ENABLE 0x10000
1572 #define BUPD_CLKO_LTF 0x20000
1573 #define BCOM_CH_CFO 0x40000
1574 #define BCSI_ESTI_MODE 0x80000
1575 #define BADV_UPD_EQZ 0x100000
1576 #define BUCHCFG 0x7000000
1577 #define BUPDEQZ 0x8000000
1579 #define BRX_PESUDO_NOISE_ON 0x20000000
1580 #define BRX_PESUDO_NOISE_A 0xff
1581 #define BRX_PESUDO_NOISE_B 0xff00
1582 #define BRX_PESUDO_NOISE_C 0xff0000
1583 #define BRX_PESUDO_NOISE_D 0xff000000
1584 #define BRX_PESUDO_NOISESTATE_A 0xffff
1585 #define BRX_PESUDO_NOISESTATE_B 0xffff0000
1586 #define BRX_PESUDO_NOISESTATE_C 0xffff
1587 #define BRX_PESUDO_NOISESTATE_D 0xffff0000
1589 #define BZEBRA1_HSSIENABLE 0x8
1590 #define BZEBRA1_TRXCONTROL 0xc00
1591 #define BZEBRA1_TRXGAINSETTING 0x07f
1592 #define BZEBRA1_RXCOUNTER 0xc00
1593 #define BZEBRA1_TXCHANGEPUMP 0x38
1594 #define BZEBRA1_RXCHANGEPUMP 0x7
1595 #define BZEBRA1_CHANNEL_NUM 0xf80
1596 #define BZEBRA1_TXLPFBW 0x400
1597 #define BZEBRA1_RXLPFBW 0x600
1599 #define BRTL8256REG_MODE_CTRL1 0x100
1600 #define BRTL8256REG_MODE_CTRL0 0x40
1601 #define BRTL8256REG_TXLPFBW 0x18
1602 #define BRTL8256REG_RXLPFBW 0x600
1604 #define BRTL8258_TXLPFBW 0xc
1605 #define BRTL8258_RXLPFBW 0xc00
1606 #define BRTL8258_RSSILPFBW 0xc0
1616 #define MASKBYTE0 0xff
1617 #define MASKBYTE1 0xff00
1618 #define MASKBYTE2 0xff0000
1619 #define MASKBYTE3 0xff000000
1620 #define MASKHWORD 0xffff0000
1621 #define MASKLWORD 0x0000ffff
1622 #define MASKDWORD 0xffffffff
1623 #define MASK12BITS 0xfff
1624 #define MASKH4BITS 0xf0000000
1625 #define MASKOFDM_D 0xffc00000
1626 #define MASKCCK 0x3f3f3f3f
1628 #define MASK4BITS 0x0f
1629 #define MASK20BITS 0xfffff
1630 #define RFREG_OFFSET_MASK 0xfffff
1632 #define BMASKBYTE0 0xff
1633 #define BMASKBYTE1 0xff00
1634 #define BMASKBYTE2 0xff0000
1635 #define BMASKBYTE3 0xff000000
1636 #define BMASKHWORD 0xffff0000
1637 #define BMASKLWORD 0x0000ffff
1638 #define BMASKDWORD 0xffffffff
1639 #define BMASK12BITS 0xfff
1640 #define BMASKH4BITS 0xf0000000
1641 #define BMASKOFDM_D 0xffc00000
1642 #define BMASKCCK 0x3f3f3f3f
1644 #define BRFREGOFFSETMASK 0xfffff
1646 /* WOL bit information */
1647 #define WOL_REASON_PTK_UPDATE BIT(0)
1648 #define WOL_REASON_GTK_UPDATE BIT(1)
1649 #define WOL_REASON_DISASSOC BIT(2)
1650 #define WOL_REASON_DEAUTH BIT(3)
1651 #define WOL_REASON_FW_DISCONNECT BIT(4)