1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #include "../mp_precomp.h"
27 #include "../phydm_precomp.h"
29 /* ======================================================================== */
30 /* These following functions can be used for PHY DM only*/
32 static u32 reg82c_8822b;
33 static u32 reg838_8822b;
34 static u32 reg830_8822b;
35 static u32 reg83c_8822b;
36 static u32 rega20_8822b;
37 static u32 rega24_8822b;
38 static u32 rega28_8822b;
39 static enum odm_bw bw_8822b;
40 static u8 central_ch_8822b;
42 static u32 cca_ifem_ccut[12][4] = {
44 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
45 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
46 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg838*/
47 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
49 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
50 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
51 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
52 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
54 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
55 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
56 {0x00000000, 0x87746641, 0x00000000, 0x87746641}, /*Reg838*/
57 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
59 static u32 cca_efem_ccut[12][4] = {
61 {0x75A76010, 0x75A76010, 0x75A76010, 0x75A75010}, /*Reg82C*/
62 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
63 {0x87766651, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
64 {0x9194b2b9, 0x9194b2b9, 0x9194b2b9, 0x9194b2b9}, /*Reg83C*/
66 {0x75A85010, 0x75A75010, 0x75A85010, 0x75A75010}, /*Reg82C*/
67 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
68 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
69 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
71 {0x76BA7010, 0x75BA7010, 0x76BA7010, 0x75BA7010}, /*Reg82C*/
72 {0x79a0ea28, 0x00000000, 0x79a0ea28, 0x00000000}, /*Reg830*/
73 {0x87766431, 0x87766431, 0x87766431, 0x87766431}, /*Reg838*/
74 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
76 static u32 cca_ifem_ccut_rfetype5[12][4] = {
78 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
79 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
80 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
81 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
83 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
84 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
85 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
86 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
88 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
89 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
90 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
91 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
93 static u32 cca_ifem_ccut_rfetype3[12][4] = {
95 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
96 {0x00000000, 0x79a0ea2c, 0x00000000, 0x00000000}, /*Reg830*/
97 {0x00000000, 0x00000000, 0x87766461, 0x87766461}, /*Reg838*/
98 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
100 {0x75D97010, 0x75D97010, 0x75D97010, 0x75D97010}, /*Reg82C*/
101 {0x00000000, 0x79a0ea2c, 0x00000000, 0x79a0ea28}, /*Reg830*/
102 {0x87765541, 0x87766341, 0x87765541, 0x87766341}, /*Reg838*/
103 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg83C*/
105 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
106 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, /*Reg830*/
107 {0x00000000, 0x76666641, 0x00000000, 0x76666641}, /*Reg838*/
108 {0x00000000, 0x00000000, 0x00000000, 0x00000000},
111 static inline u32 phydm_check_bit_mask(u32 bit_mask, u32 data_original,
116 if (bit_mask != 0xfffff) {
117 for (bit_shift = 0; bit_shift <= 19; bit_shift++) {
118 if (((bit_mask >> bit_shift) & 0x1) == 1)
121 return ((data_original) & (~bit_mask)) | (data << bit_shift);
126 static bool phydm_rfe_8822b(struct phy_dm_struct *dm, u8 channel)
128 if (dm->rfe_type == 4) {
129 /* Default setting is in PHY parameters */
133 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
135 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
137 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
138 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
141 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
142 BIT(2) | BIT(1) | BIT(0)),
144 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x2);
145 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
146 BIT(2) | BIT(1) | BIT(0)),
148 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x2);
150 /* antenna switch table */
151 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
152 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
154 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf050);
155 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf050);
156 } else if (dm->rx_ant_status == dm->tx_ant_status) {
157 /* TXA+RXA or TXB+RXB */
158 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf055);
159 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf055);
161 /* TXB+RXA or TXA+RXB */
162 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xf550);
163 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xf550);
166 } else if (channel > 35) {
168 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
170 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
172 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
173 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
176 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
177 BIT(2) | BIT(1) | BIT(0)),
179 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
180 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
181 BIT(2) | BIT(1) | BIT(0)),
183 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
185 /* antenna switch table */
186 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
187 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
189 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
190 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
191 } else if (dm->rx_ant_status == dm->tx_ant_status) {
192 /* TXA+RXA or TXB+RXB */
193 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
194 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
196 /* TXB+RXA or TXA+RXB */
197 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
198 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
204 } else if ((dm->rfe_type == 1) || (dm->rfe_type == 2) ||
205 (dm->rfe_type == 7) || (dm->rfe_type == 9)) {
207 if (((dm->cut_version == ODM_CUT_A) ||
208 (dm->cut_version == ODM_CUT_B)) &&
209 (dm->rfe_type < 2)) {
212 odm_set_bb_reg(dm, 0xcb0,
213 (MASKBYTE2 | MASKLWORD),
215 odm_set_bb_reg(dm, 0xeb0,
216 (MASKBYTE2 | MASKLWORD),
218 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
219 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
220 } else if (channel > 35) {
221 odm_set_bb_reg(dm, 0xcb0,
222 (MASKBYTE2 | MASKLWORD),
224 odm_set_bb_reg(dm, 0xeb0,
225 (MASKBYTE2 | MASKLWORD),
227 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x45);
228 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x45);
233 /* delay 400ns for PAPE */
234 odm_set_bb_reg(dm, 0x810,
235 MASKBYTE3 | BIT(20) | BIT(21) | BIT(22) |
239 /* antenna switch table */
240 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa555);
241 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa555);
244 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
245 BIT(2) | BIT(1) | BIT(0)),
247 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
248 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
249 BIT(2) | BIT(1) | BIT(0)),
251 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
255 "%s: Using old RFE control pin setting for A-cut and B-cut\n",
260 odm_set_bb_reg(dm, 0xcb0,
261 (MASKBYTE2 | MASKLWORD),
263 odm_set_bb_reg(dm, 0xeb0,
264 (MASKBYTE2 | MASKLWORD),
266 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
267 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
268 odm_set_bb_reg(dm, 0xcb8, BIT(4), 0);
269 odm_set_bb_reg(dm, 0xeb8, BIT(4), 0);
270 } else if (channel > 35) {
272 odm_set_bb_reg(dm, 0xcb0,
273 (MASKBYTE2 | MASKLWORD),
275 odm_set_bb_reg(dm, 0xeb0,
276 (MASKBYTE2 | MASKLWORD),
278 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
279 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
280 odm_set_bb_reg(dm, 0xcb8, BIT(5), 0);
281 odm_set_bb_reg(dm, 0xeb8, BIT(5), 0);
287 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) |
288 BIT(2) | BIT(1) | BIT(0)),
290 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
291 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) |
292 BIT(2) | BIT(1) | BIT(0)),
294 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
296 /* antenna switch table */
297 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
298 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
300 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
301 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
302 } else if (dm->rx_ant_status == dm->tx_ant_status) {
303 /* TXA+RXA or TXB+RXB */
304 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
305 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
307 /* TXB+RXA or TXA+RXB */
308 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
309 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
312 } else if ((dm->rfe_type == 0) || (dm->rfe_type == 3) ||
313 (dm->rfe_type == 5) || (dm->rfe_type == 6) ||
314 (dm->rfe_type == 8) || (dm->rfe_type == 10)) {
319 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
321 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
323 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x57);
324 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x57);
326 } else if (channel > 35) {
329 odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
331 odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
333 odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
334 odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
341 odm_set_bb_reg(dm, 0xcbc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
344 odm_set_bb_reg(dm, 0xcbc, (BIT(11) | BIT(10)), 0x0);
345 odm_set_bb_reg(dm, 0xebc, (BIT(5) | BIT(4) | BIT(3) | BIT(2) |
348 odm_set_bb_reg(dm, 0xebc, (BIT(11) | BIT(10)), 0x0);
350 /* antenna switch table */
352 if ((dm->rx_ant_status == (ODM_RF_A | ODM_RF_B)) ||
353 (dm->tx_ant_status == (ODM_RF_A | ODM_RF_B))) {
355 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa501);
356 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa501);
357 } else if (dm->rx_ant_status == dm->tx_ant_status) {
358 /* TXA+RXA or TXB+RXB */
359 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa500);
360 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa500);
362 /* TXB+RXA or TXA+RXB */
363 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa005);
364 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa005);
366 } else if (channel > 35) {
367 odm_set_bb_reg(dm, 0xca0, MASKLWORD, 0xa5a5);
368 odm_set_bb_reg(dm, 0xea0, MASKLWORD, 0xa5a5);
373 odm_set_bb_reg(dm, 0x64, BIT(29) | BIT(28), 0x3);
374 odm_set_bb_reg(dm, 0x4c, BIT(26) | BIT(25), 0x0);
375 odm_set_bb_reg(dm, 0x40, BIT(2), 0x1);
378 odm_set_bb_reg(dm, 0x1990,
379 (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
381 odm_set_bb_reg(dm, 0x1990, (BIT(11) | BIT(10)), 0x3);
383 /* input or output */
384 odm_set_bb_reg(dm, 0x974,
385 (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)),
387 odm_set_bb_reg(dm, 0x974, (BIT(11) | BIT(10)), 0x3);
391 "%s: Update RFE control pin setting (ch%d, tx_path 0x%x, rx_path 0x%x)\n",
392 __func__, channel, dm->tx_ant_status, dm->rx_ant_status);
397 static void phydm_ccapar_by_rfe_8822b(struct phy_dm_struct *dm)
399 u32 cca_ifem[12][4], cca_efem[12][4];
401 u32 reg82c, reg830, reg838, reg83c;
403 if (dm->cut_version == ODM_CUT_A)
406 odm_move_memory(dm, cca_efem, cca_efem_ccut, 48 * 4);
407 if (dm->rfe_type == 5)
408 odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype5,
410 else if (dm->rfe_type == 3)
411 odm_move_memory(dm, cca_ifem, cca_ifem_ccut_rfetype3,
414 odm_move_memory(dm, cca_ifem, cca_ifem_ccut, 48 * 4);
416 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
417 "%s: Update CCA parameters for Ccut\n", __func__);
420 if (bw_8822b == ODM_BW20M)
422 else if (bw_8822b == ODM_BW40M)
427 if (central_ch_8822b <= 14) {
428 if ((dm->rx_ant_status == ODM_RF_A) ||
429 (dm->rx_ant_status == ODM_RF_B))
434 if ((dm->rx_ant_status == ODM_RF_A) ||
435 (dm->rx_ant_status == ODM_RF_B))
441 if ((dm->rfe_type == 1) || (dm->rfe_type == 4) || (dm->rfe_type == 6) ||
442 (dm->rfe_type == 7)) {
443 /*eFEM => RFE type 1 & RFE type 4 & RFE type 6 & RFE type 7*/
444 reg82c = (cca_efem[row][col] != 0) ? cca_efem[row][col] :
446 reg830 = (cca_efem[row + 1][col] != 0) ?
447 cca_efem[row + 1][col] :
449 reg838 = (cca_efem[row + 2][col] != 0) ?
450 cca_efem[row + 2][col] :
452 reg83c = (cca_efem[row + 3][col] != 0) ?
453 cca_efem[row + 3][col] :
455 } else if ((dm->rfe_type == 2) || (dm->rfe_type == 9)) {
456 /*5G eFEM, 2G iFEM => RFE type 2, 5G eFEM => RFE type 9 */
457 if (central_ch_8822b <= 14) {
458 reg82c = (cca_ifem[row][col] != 0) ?
461 reg830 = (cca_ifem[row + 1][col] != 0) ?
462 cca_ifem[row + 1][col] :
464 reg838 = (cca_ifem[row + 2][col] != 0) ?
465 cca_ifem[row + 2][col] :
467 reg83c = (cca_ifem[row + 3][col] != 0) ?
468 cca_ifem[row + 3][col] :
471 reg82c = (cca_efem[row][col] != 0) ?
474 reg830 = (cca_efem[row + 1][col] != 0) ?
475 cca_efem[row + 1][col] :
477 reg838 = (cca_efem[row + 2][col] != 0) ?
478 cca_efem[row + 2][col] :
480 reg83c = (cca_efem[row + 3][col] != 0) ?
481 cca_efem[row + 3][col] :
485 /* iFEM =>RFE type 3 & RFE type 5 & RFE type 0 & RFE type 8 &
488 reg82c = (cca_ifem[row][col] != 0) ? cca_ifem[row][col] :
490 reg830 = (cca_ifem[row + 1][col] != 0) ?
491 cca_ifem[row + 1][col] :
493 reg838 = (cca_ifem[row + 2][col] != 0) ?
494 cca_ifem[row + 2][col] :
496 reg83c = (cca_ifem[row + 3][col] != 0) ?
497 cca_ifem[row + 3][col] :
501 odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
502 odm_set_bb_reg(dm, 0x830, MASKDWORD, reg830);
503 odm_set_bb_reg(dm, 0x838, MASKDWORD, reg838);
504 odm_set_bb_reg(dm, 0x83c, MASKDWORD, reg83c);
505 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
506 "%s: (Pkt%d, Intf%d, RFE%d), row = %d, col = %d\n",
507 __func__, dm->package_type, dm->support_interface,
508 dm->rfe_type, row, col);
511 static void phydm_ccapar_by_bw_8822b(struct phy_dm_struct *dm,
512 enum odm_bw bandwidth)
516 if (dm->cut_version != ODM_CUT_A)
520 reg82c = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
522 if (bandwidth == ODM_BW20M) {
526 reg82c &= (~(0x0f00f000));
527 reg82c |= ((0x4) << 12);
528 reg82c |= ((0x6) << 24);
529 } else if (bandwidth == ODM_BW40M) {
533 reg82c &= (~(0x0f0f0000));
534 reg82c |= ((0x9) << 16);
535 reg82c |= ((0x6) << 24);
536 } else if (bandwidth == ODM_BW80M) {
542 reg82c &= (~(0x0ffff000));
543 reg82c |= ((0xdb7) << 12);
544 reg82c |= ((0x3) << 24);
547 odm_set_bb_reg(dm, 0x82c, MASKDWORD, reg82c);
548 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
549 "%s(): Update CCA parameters for Acut\n", __func__);
552 static void phydm_ccapar_by_rxpath_8822b(struct phy_dm_struct *dm)
554 if (dm->cut_version != ODM_CUT_A)
557 if ((dm->rx_ant_status == ODM_RF_A) ||
558 (dm->rx_ant_status == ODM_RF_B)) {
565 odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x777678);
573 odm_set_bb_reg(dm, 0x838, 0x0ffffff0, 0x776633);
575 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
576 "%s(): Update CCA parameters for Acut\n", __func__);
579 static void phydm_rxdfirpar_by_bw_8822b(struct phy_dm_struct *dm,
580 enum odm_bw bandwidth)
582 if (bandwidth == ODM_BW40M) {
583 /* RX DFIR for BW40 */
584 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x1);
585 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x0);
586 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
587 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
588 } else if (bandwidth == ODM_BW80M) {
589 /* RX DFIR for BW80 */
590 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
591 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x1);
592 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x0);
593 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x0);
595 /* RX DFIR for BW20, BW10 and BW5*/
596 odm_set_bb_reg(dm, 0x948, BIT(29) | BIT(28), 0x2);
597 odm_set_bb_reg(dm, 0x94c, BIT(29) | BIT(28), 0x2);
598 odm_set_bb_reg(dm, 0xc20, BIT(31), 0x1);
599 odm_set_bb_reg(dm, 0xe20, BIT(31), 0x1);
603 bool phydm_write_txagc_1byte_8822b(struct phy_dm_struct *dm, u32 power_index,
604 enum odm_rf_radio_path path, u8 hw_rate)
606 u32 offset_txagc[2] = {0x1d00, 0x1d80};
607 u8 rate_idx = (hw_rate & 0xfc), i;
608 u8 rate_offset = (hw_rate & 0x3);
609 u32 txagc_content = 0x0;
611 /* For debug command only!!!! */
614 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
615 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
616 "%s(): unsupported path (%d)\n", __func__, path);
620 /* For HW limitation, We can't write TXAGC once a byte. */
621 for (i = 0; i < 4; i++) {
622 if (i != rate_offset)
624 txagc_content | (config_phydm_read_txagc_8822b(
625 dm, path, rate_idx + i)
628 txagc_content = txagc_content |
629 ((power_index & 0x3f) << (i << 3));
631 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
634 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
635 "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
636 path, hw_rate, (offset_txagc[path] + hw_rate),
641 void phydm_init_hw_info_by_rfe_type_8822b(struct phy_dm_struct *dm)
643 u16 mask_path_a = 0x0303;
644 u16 mask_path_b = 0x0c0c;
645 /*u16 mask_path_c = 0x3030;*/
646 /*u16 mask_path_d = 0xc0c0;*/
648 dm->is_init_hw_info_by_rfe = false;
650 if ((dm->rfe_type == 1) || (dm->rfe_type == 6) || (dm->rfe_type == 7)) {
651 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
652 (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
653 ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
655 if (dm->rfe_type == 6) {
658 (TYPE_GPA1 & (mask_path_a | mask_path_b)));
661 (TYPE_APA1 & (mask_path_a | mask_path_b)));
663 dm, ODM_CMNINFO_GLNA,
664 (TYPE_GLNA1 & (mask_path_a | mask_path_b)));
666 dm, ODM_CMNINFO_ALNA,
667 (TYPE_ALNA1 & (mask_path_a | mask_path_b)));
668 } else if (dm->rfe_type == 7) {
671 (TYPE_GPA2 & (mask_path_a | mask_path_b)));
674 (TYPE_APA2 & (mask_path_a | mask_path_b)));
676 dm, ODM_CMNINFO_GLNA,
677 (TYPE_GLNA2 & (mask_path_a | mask_path_b)));
679 dm, ODM_CMNINFO_ALNA,
680 (TYPE_ALNA2 & (mask_path_a | mask_path_b)));
684 (TYPE_GPA0 & (mask_path_a | mask_path_b)));
687 (TYPE_APA0 & (mask_path_a | mask_path_b)));
689 dm, ODM_CMNINFO_GLNA,
690 (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
692 dm, ODM_CMNINFO_ALNA,
693 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
696 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
698 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
699 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
700 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
701 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
702 } else if (dm->rfe_type == 2) {
703 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
704 (ODM_BOARD_EXT_LNA_5G | ODM_BOARD_EXT_PA_5G));
705 odm_cmn_info_init(dm, ODM_CMNINFO_APA,
706 (TYPE_APA0 & (mask_path_a | mask_path_b)));
707 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
708 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
710 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
712 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
713 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
714 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
715 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
716 } else if (dm->rfe_type == 9) {
717 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
718 (ODM_BOARD_EXT_LNA_5G));
719 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
720 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
722 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
724 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
725 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
726 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
727 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
728 } else if ((dm->rfe_type == 3) || (dm->rfe_type == 5)) {
729 /* RFE type 3: 8822BS\8822BU TFBGA iFEM */
730 /* RFE type 5: 8822BE TFBGA iFEM */
731 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
733 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
735 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
736 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
737 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
738 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
739 } else if (dm->rfe_type == 4) {
740 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE,
741 (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_LNA_5G |
742 ODM_BOARD_EXT_PA | ODM_BOARD_EXT_PA_5G));
743 odm_cmn_info_init(dm, ODM_CMNINFO_GPA,
744 (TYPE_GPA0 & (mask_path_a | mask_path_b)));
745 odm_cmn_info_init(dm, ODM_CMNINFO_APA,
746 (TYPE_APA0 & (mask_path_a | mask_path_b)));
747 odm_cmn_info_init(dm, ODM_CMNINFO_GLNA,
748 (TYPE_GLNA0 & (mask_path_a | mask_path_b)));
749 odm_cmn_info_init(dm, ODM_CMNINFO_ALNA,
750 (TYPE_ALNA0 & (mask_path_a | mask_path_b)));
752 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
754 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, true);
755 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, true);
756 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, true);
757 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, true);
758 } else if (dm->rfe_type == 8) {
759 /* RFE type 8: TFBGA iFEM AP */
760 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
762 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 2);
764 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
765 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
766 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
767 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
769 /* RFE Type 0 & 9 & 10: QFN iFEM */
770 odm_cmn_info_init(dm, ODM_CMNINFO_BOARD_TYPE, 0);
772 odm_cmn_info_init(dm, ODM_CMNINFO_PACKAGE_TYPE, 1);
774 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_LNA, false);
775 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_LNA, false);
776 odm_cmn_info_init(dm, ODM_CMNINFO_EXT_PA, false);
777 odm_cmn_info_init(dm, ODM_CMNINFO_5G_EXT_PA, false);
780 dm->is_init_hw_info_by_rfe = true;
784 "%s(): RFE type (%d), Board type (0x%x), Package type (%d)\n",
785 __func__, dm->rfe_type, dm->board_type, dm->package_type);
788 "%s(): 5G ePA (%d), 5G eLNA (%d), 2G ePA (%d), 2G eLNA (%d)\n",
789 __func__, dm->ext_pa_5g, dm->ext_lna_5g, dm->ext_pa,
793 "%s(): 5G PA type (%d), 5G LNA type (%d), 2G PA type (%d), 2G LNA type (%d)\n",
794 __func__, dm->type_apa, dm->type_alna, dm->type_gpa,
798 s32 phydm_get_condition_number_8822B(struct phy_dm_struct *dm)
802 odm_set_bb_reg(dm, 0x1988, BIT(22), 0x1);
804 (s32)odm_get_bb_reg(dm, 0xf84, (BIT(17) | BIT(16) | MASKLWORD));
807 ret_val = ret_val << (8 - 4);
808 ret_val = ret_val / 234;
809 } else if (bw_8822b == 1) {
810 ret_val = ret_val << (7 - 4);
811 ret_val = ret_val / 108;
812 } else if (bw_8822b == 2) {
813 ret_val = ret_val << (6 - 4);
814 ret_val = ret_val / 52;
820 /* ======================================================================== */
822 /* ======================================================================== */
823 /* These following functions can be used by driver*/
825 u32 config_phydm_read_rf_reg_8822b(struct phy_dm_struct *dm,
826 enum odm_rf_radio_path rf_path, u32 reg_addr,
829 u32 readback_value, direct_addr;
830 u32 offset_read_rf[2] = {0x2800, 0x2c00};
831 u32 power_RF[2] = {0x1c, 0xec};
834 if (rf_path > ODM_RF_PATH_B) {
835 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
836 "%s(): unsupported path (%d)\n", __func__,
838 return INVALID_RF_DATA;
841 /* Error handling. Check if RF power is enable or not */
842 /* 0xffffffff means RF power is disable */
843 if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
844 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
845 "%s(): Read fail, RF is disabled\n", __func__);
846 return INVALID_RF_DATA;
849 /* Calculate offset */
851 direct_addr = offset_read_rf[rf_path] + (reg_addr << 2);
853 /* RF register only has 20bits */
854 bit_mask &= RFREGOFFSETMASK;
856 /* Read RF register directly */
857 readback_value = odm_get_bb_reg(dm, direct_addr, bit_mask);
858 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
859 "%s(): RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", __func__,
860 rf_path, reg_addr, readback_value, bit_mask);
861 return readback_value;
864 bool config_phydm_write_rf_reg_8822b(struct phy_dm_struct *dm,
865 enum odm_rf_radio_path rf_path,
866 u32 reg_addr, u32 bit_mask, u32 data)
868 u32 data_and_addr = 0, data_original = 0;
869 u32 offset_write_rf[2] = {0xc90, 0xe90};
870 u32 power_RF[2] = {0x1c, 0xec};
873 if (rf_path > ODM_RF_PATH_B) {
874 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
875 "%s(): unsupported path (%d)\n", __func__,
880 /* Read RF register content first */
882 bit_mask = bit_mask & RFREGOFFSETMASK;
884 if (bit_mask != RFREGOFFSETMASK) {
885 data_original = config_phydm_read_rf_reg_8822b(
886 dm, rf_path, reg_addr, RFREGOFFSETMASK);
888 /* Error handling. RF is disabled */
889 if (!config_phydm_read_rf_check_8822b(data_original)) {
890 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
891 "%s(): Write fail, RF is disable\n",
897 data = phydm_check_bit_mask(bit_mask, data_original, data);
898 } else if (odm_get_mac_reg(dm, power_RF[rf_path], MASKBYTE3) != 0x7) {
899 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
900 "%s(): Write fail, RF is disabled\n", __func__);
904 /* Put write addr in [27:20] and write data in [19:00] */
905 data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
907 /* Write operation */
908 odm_set_bb_reg(dm, offset_write_rf[rf_path], MASKDWORD, data_and_addr);
911 "%s(): RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n",
912 __func__, rf_path, reg_addr, data, data_original, bit_mask);
916 bool config_phydm_write_txagc_8822b(struct phy_dm_struct *dm, u32 power_index,
917 enum odm_rf_radio_path path, u8 hw_rate)
919 u32 offset_txagc[2] = {0x1d00, 0x1d80};
920 u8 rate_idx = (hw_rate & 0xfc);
922 /* Input need to be HW rate index, not driver rate index!!!! */
924 if (dm->is_disable_phy_api) {
925 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
926 "%s(): disable PHY API for debug!!\n", __func__);
931 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
932 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
933 "%s(): unsupported path (%d)\n", __func__, path);
937 /* driver need to construct a 4-byte power index */
938 odm_set_bb_reg(dm, (offset_txagc[path] + rate_idx), MASKDWORD,
941 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
942 "%s(): path-%d rate index 0x%x (0x%x) = 0x%x\n", __func__,
943 path, hw_rate, (offset_txagc[path] + hw_rate),
948 u8 config_phydm_read_txagc_8822b(struct phy_dm_struct *dm,
949 enum odm_rf_radio_path path, u8 hw_rate)
953 /* Input need to be HW rate index, not driver rate index!!!! */
956 if ((path > ODM_RF_PATH_B) || (hw_rate > 0x53)) {
957 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
958 "%s(): unsupported path (%d)\n", __func__, path);
959 return INVALID_TXAGC_DATA;
962 /* Disable TX AGC report */
963 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0); /* need to check */
965 /* Set data rate index (bit0~6) and path index (bit7) */
966 odm_set_bb_reg(dm, 0x1998, MASKBYTE0, (hw_rate | (path << 7)));
968 /* Enable TXAGC report */
969 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x1);
971 /* Read TX AGC report */
972 read_back_data = (u8)odm_get_bb_reg(dm, 0xd30, 0x7f0000);
974 /* Driver have to disable TXAGC report after reading TXAGC
975 * (ref. user guide v11)
977 odm_set_bb_reg(dm, 0x1998, BIT(16), 0x0);
979 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
980 "%s(): path-%d rate index 0x%x = 0x%x\n", __func__, path,
981 hw_rate, read_back_data);
982 return read_back_data;
985 bool config_phydm_switch_band_8822b(struct phy_dm_struct *dm, u8 central_ch)
988 bool rf_reg_status = true;
990 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()======================>\n",
993 if (dm->is_disable_phy_api) {
994 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
995 "%s(): disable PHY API for debug!!\n", __func__);
999 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1002 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1004 if (central_ch <= 14) {
1007 /* Enable CCK block */
1008 odm_set_bb_reg(dm, 0x808, BIT(28), 0x1);
1010 /* Disable MAC CCK check */
1011 odm_set_bb_reg(dm, 0x454, BIT(7), 0x0);
1013 /* Disable BB CCK check */
1014 odm_set_bb_reg(dm, 0xa80, BIT(18), 0x0);
1017 odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1020 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1022 /* RxHP dynamic control */
1023 if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1024 (dm->rfe_type == 5)) {
1025 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
1026 odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29095612);
1029 } else if (central_ch > 35) {
1032 /* Enable BB CCK check */
1033 odm_set_bb_reg(dm, 0xa80, BIT(18), 0x1);
1035 /* Enable CCK check */
1036 odm_set_bb_reg(dm, 0x454, BIT(7), 0x1);
1038 /* Disable CCK block */
1039 odm_set_bb_reg(dm, 0x808, BIT(28), 0x0);
1042 odm_set_bb_reg(dm, 0x814, 0x0000FC00, 15); /*default value*/
1045 rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8))));
1046 rf_reg18 = (rf_reg18 | BIT(8) | BIT(16));
1048 /* RxHP dynamic control */
1049 if ((dm->rfe_type == 2) || (dm->rfe_type == 3) ||
1050 (dm->rfe_type == 5)) {
1051 odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08100000);
1052 odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x21095612);
1056 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1057 "%s(): Fail to switch band (ch: %d)\n", __func__,
1062 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1063 dm, ODM_RF_PATH_A, 0x18,
1064 RFREGOFFSETMASK, rf_reg18);
1066 if (dm->rf_type > ODM_1T1R)
1068 rf_reg_status & config_phydm_write_rf_reg_8822b(
1069 dm, ODM_RF_PATH_B, 0x18,
1070 RFREGOFFSETMASK, rf_reg18);
1072 if (!phydm_rfe_8822b(dm, central_ch))
1075 if (!rf_reg_status) {
1078 "%s(): Fail to switch band (ch: %d), because writing RF register is fail\n",
1079 __func__, central_ch);
1083 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1084 "%s(): Success to switch band (ch: %d)\n", __func__,
1089 bool config_phydm_switch_channel_8822b(struct phy_dm_struct *dm, u8 central_ch)
1091 struct dig_thres *dig_tab = &dm->dm_dig_table;
1092 u32 rf_reg18 = 0, rf_reg_b8 = 0, rf_reg_be = 0xff;
1093 bool rf_reg_status = true;
1094 u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff,
1095 0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
1096 u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff,
1097 0x0, 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff,
1098 0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7};
1099 u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff,
1100 0x0, 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
1102 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()====================>\n",
1105 if (dm->is_disable_phy_api) {
1106 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1107 "%s(): disable PHY API for debug!!\n", __func__);
1111 central_ch_8822b = central_ch;
1112 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1115 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1116 rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0)));
1118 if (dm->cut_version == ODM_CUT_A) {
1119 rf_reg_b8 = config_phydm_read_rf_reg_8822b(
1120 dm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK);
1121 rf_reg_status = rf_reg_status &
1122 config_phydm_read_rf_check_8822b(rf_reg_b8);
1125 /* Switch band and channel */
1126 if (central_ch <= 14) {
1129 /* 1. RF band and channel*/
1130 rf_reg18 = (rf_reg18 | central_ch);
1132 /* 2. AGC table selection */
1133 odm_set_bb_reg(dm, 0x958, 0x1f, 0x0);
1134 dig_tab->agc_table_idx = 0x0;
1136 /* 3. Set central frequency for clock offset tracking */
1137 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x96a);
1139 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1140 if (dm->cut_version == ODM_CUT_A)
1141 rf_reg_b8 = rf_reg_b8 | BIT(19);
1143 /* CCK TX filter parameters */
1144 if (central_ch == 14) {
1145 odm_set_bb_reg(dm, 0xa20, MASKHWORD, 0x8488);
1146 odm_set_bb_reg(dm, 0xa24, MASKDWORD, 0x00006577);
1147 odm_set_bb_reg(dm, 0xa28, MASKLWORD, 0x0000);
1149 odm_set_bb_reg(dm, 0xa20, MASKHWORD,
1150 (rega20_8822b >> 16));
1151 odm_set_bb_reg(dm, 0xa24, MASKDWORD, rega24_8822b);
1152 odm_set_bb_reg(dm, 0xa28, MASKLWORD,
1153 (rega28_8822b & MASKLWORD));
1156 } else if (central_ch > 35) {
1159 /* 1. RF band and channel*/
1160 rf_reg18 = (rf_reg18 | central_ch);
1162 /* 2. AGC table selection */
1163 if ((central_ch >= 36) && (central_ch <= 64)) {
1164 odm_set_bb_reg(dm, 0x958, 0x1f, 0x1);
1165 dig_tab->agc_table_idx = 0x1;
1166 } else if ((central_ch >= 100) && (central_ch <= 144)) {
1167 odm_set_bb_reg(dm, 0x958, 0x1f, 0x2);
1168 dig_tab->agc_table_idx = 0x2;
1169 } else if (central_ch >= 149) {
1170 odm_set_bb_reg(dm, 0x958, 0x1f, 0x3);
1171 dig_tab->agc_table_idx = 0x3;
1175 "%s(): Fail to switch channel (AGC) (ch: %d)\n",
1176 __func__, central_ch);
1180 /* 3. Set central frequency for clock offset tracking */
1181 if ((central_ch >= 36) && (central_ch <= 48)) {
1182 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x494);
1183 } else if ((central_ch >= 52) && (central_ch <= 64)) {
1184 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x453);
1185 } else if ((central_ch >= 100) && (central_ch <= 116)) {
1186 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x452);
1187 } else if ((central_ch >= 118) && (central_ch <= 177)) {
1188 odm_set_bb_reg(dm, 0x860, 0x1ffe0000, 0x412);
1192 "%s(): Fail to switch channel (fc_area) (ch: %d)\n",
1193 __func__, central_ch);
1197 /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */
1198 if (dm->cut_version == ODM_CUT_A) {
1199 if ((central_ch >= 57) && (central_ch <= 75))
1200 rf_reg_b8 = rf_reg_b8 & (~BIT(19));
1202 rf_reg_b8 = rf_reg_b8 | BIT(19);
1205 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1206 "%s(): Fail to switch channel (ch: %d)\n",
1207 __func__, central_ch);
1211 /* Modify IGI for MP driver to aviod PCIE interference */
1212 if (dm->mp_mode && ((dm->rfe_type == 3) || (dm->rfe_type == 5))) {
1213 if (central_ch == 14)
1214 odm_write_dig(dm, 0x26);
1216 odm_write_dig(dm, 0x20);
1219 /* Modify the setting of register 0xBE to reduce phase noise */
1220 if (central_ch <= 14)
1222 else if ((central_ch >= 36) && (central_ch <= 64))
1223 rf_reg_be = low_band[(central_ch - 36) >> 1];
1224 else if ((central_ch >= 100) && (central_ch <= 144))
1225 rf_reg_be = middle_band[(central_ch - 100) >> 1];
1226 else if ((central_ch >= 149) && (central_ch <= 177))
1227 rf_reg_be = high_band[(central_ch - 149) >> 1];
1231 if (rf_reg_be != 0xff) {
1233 rf_reg_status & config_phydm_write_rf_reg_8822b(
1234 dm, ODM_RF_PATH_A, 0xbe,
1235 (BIT(17) | BIT(16) | BIT(15)),
1240 "%s(): Fail to switch channel (ch: %d, Phase noise)\n",
1241 __func__, central_ch);
1245 /* Fix channel 144 issue, ask by RFSI Alvin*/
1246 /* 00 when freq < 5400; 01 when 5400<=freq<=5720; 10 when freq > 5720;
1249 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */
1250 if (central_ch == 144) {
1251 rf_reg_status = rf_reg_status &
1252 config_phydm_write_rf_reg_8822b(
1253 dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x1);
1254 rf_reg18 = (rf_reg18 | BIT(17));
1256 rf_reg_status = rf_reg_status &
1257 config_phydm_write_rf_reg_8822b(
1258 dm, ODM_RF_PATH_A, 0xdf, BIT(18), 0x0);
1260 if (central_ch > 144)
1261 rf_reg18 = (rf_reg18 | BIT(18));
1262 else if (central_ch >= 80)
1263 rf_reg18 = (rf_reg18 | BIT(17));
1266 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1267 dm, ODM_RF_PATH_A, 0x18,
1268 RFREGOFFSETMASK, rf_reg18);
1270 if (dm->cut_version == ODM_CUT_A)
1272 rf_reg_status & config_phydm_write_rf_reg_8822b(
1273 dm, ODM_RF_PATH_A, 0xb8,
1274 RFREGOFFSETMASK, rf_reg_b8);
1276 if (dm->rf_type > ODM_1T1R) {
1278 rf_reg_status & config_phydm_write_rf_reg_8822b(
1279 dm, ODM_RF_PATH_B, 0x18,
1280 RFREGOFFSETMASK, rf_reg18);
1282 if (dm->cut_version == ODM_CUT_A)
1283 rf_reg_status = rf_reg_status &
1284 config_phydm_write_rf_reg_8822b(
1285 dm, ODM_RF_PATH_B, 0xb8,
1286 RFREGOFFSETMASK, rf_reg_b8);
1289 if (!rf_reg_status) {
1292 "%s(): Fail to switch channel (ch: %d), because writing RF register is fail\n",
1293 __func__, central_ch);
1297 phydm_ccapar_by_rfe_8822b(dm);
1298 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1299 "%s(): Success to switch channel (ch: %d)\n", __func__,
1304 bool config_phydm_switch_bandwidth_8822b(struct phy_dm_struct *dm,
1306 enum odm_bw bandwidth)
1309 bool rf_reg_status = true;
1312 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()===================>\n",
1315 if (dm->is_disable_phy_api) {
1316 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1317 "%s(): disable PHY API for debug!!\n", __func__);
1321 /* Error handling */
1322 if ((bandwidth >= ODM_BW_MAX) ||
1323 ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) ||
1324 ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) {
1327 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1328 __func__, bandwidth, primary_ch_idx);
1332 bw_8822b = bandwidth;
1333 rf_reg18 = config_phydm_read_rf_reg_8822b(dm, ODM_RF_PATH_A, 0x18,
1336 rf_reg_status & config_phydm_read_rf_check_8822b(rf_reg18);
1338 /* Switch bandwidth */
1339 switch (bandwidth) {
1341 /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0,
1342 * rf mode([1:0]) = 20M
1344 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, ODM_BW20M);
1346 /* ADC clock = 160M clock for BW20 */
1347 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x0);
1348 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x1);
1350 /* DAC clock = 160M clock for BW20 */
1351 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x0);
1352 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x1);
1354 /* ADC buffer clock */
1355 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1358 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1363 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1364 * rf mode([1:0]) = 40M
1366 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1367 (((primary_ch_idx & 0xf) << 2) | ODM_BW40M));
1369 /* CCK primary channel */
1370 if (primary_ch_idx == 1)
1371 odm_set_bb_reg(dm, 0xa00, BIT(4), primary_ch_idx);
1373 odm_set_bb_reg(dm, 0xa00, BIT(4), 0);
1375 /* ADC clock = 160M clock for BW40 */
1376 odm_set_bb_reg(dm, 0x8ac, (BIT(11) | BIT(10)), 0x0);
1377 odm_set_bb_reg(dm, 0x8ac, BIT(17), 0x1);
1379 /* DAC clock = 160M clock for BW20 */
1380 odm_set_bb_reg(dm, 0x8ac, (BIT(23) | BIT(22)), 0x0);
1381 odm_set_bb_reg(dm, 0x8ac, BIT(29), 0x1);
1383 /* ADC buffer clock */
1384 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1387 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1388 rf_reg18 = (rf_reg18 | BIT(11));
1393 /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel,
1394 * rf mode([1:0]) = 80M
1396 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0,
1397 (((primary_ch_idx & 0xf) << 2) | ODM_BW80M));
1399 /* ADC clock = 160M clock for BW80 */
1400 odm_set_bb_reg(dm, 0x8ac, (BIT(13) | BIT(12)), 0x0);
1401 odm_set_bb_reg(dm, 0x8ac, BIT(18), 0x1);
1403 /* DAC clock = 160M clock for BW20 */
1404 odm_set_bb_reg(dm, 0x8ac, (BIT(25) | BIT(24)), 0x0);
1405 odm_set_bb_reg(dm, 0x8ac, BIT(30), 0x1);
1407 /* ADC buffer clock */
1408 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x1);
1411 rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10))));
1412 rf_reg18 = (rf_reg18 | BIT(10));
1417 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1418 * rf mode([1:0]) = 20M
1420 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M));
1422 /* ADC clock = 40M clock */
1423 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x2);
1424 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1426 /* DAC clock = 160M clock for BW20 */
1427 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x2);
1428 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1430 /* ADC buffer clock */
1431 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1432 odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1435 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1440 /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0,
1441 * rf mode([1:0]) = 20M
1443 odm_set_bb_reg(dm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M));
1445 /* ADC clock = 80M clock */
1446 odm_set_bb_reg(dm, 0x8ac, (BIT(9) | BIT(8)), 0x3);
1447 odm_set_bb_reg(dm, 0x8ac, BIT(16), 0x0);
1449 /* DAC clock = 160M clock for BW20 */
1450 odm_set_bb_reg(dm, 0x8ac, (BIT(21) | BIT(20)), 0x3);
1451 odm_set_bb_reg(dm, 0x8ac, BIT(28), 0x0);
1453 /* ADC buffer clock */
1454 odm_set_bb_reg(dm, 0x8c4, BIT(30), 0x0);
1455 odm_set_bb_reg(dm, 0x8c8, BIT(31), 0x1);
1458 rf_reg18 = (rf_reg18 | BIT(11) | BIT(10));
1465 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d)\n",
1466 __func__, bandwidth, primary_ch_idx);
1469 /* Write RF register */
1470 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1471 dm, ODM_RF_PATH_A, 0x18,
1472 RFREGOFFSETMASK, rf_reg18);
1474 if (dm->rf_type > ODM_1T1R)
1476 rf_reg_status & config_phydm_write_rf_reg_8822b(
1477 dm, ODM_RF_PATH_B, 0x18,
1478 RFREGOFFSETMASK, rf_reg18);
1480 if (!rf_reg_status) {
1483 "%s(): Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n",
1484 __func__, bandwidth, primary_ch_idx);
1488 /* Modify RX DFIR parameters */
1489 phydm_rxdfirpar_by_bw_8822b(dm, bandwidth);
1491 /* Modify CCA parameters */
1492 phydm_ccapar_by_bw_8822b(dm, bandwidth);
1493 phydm_ccapar_by_rfe_8822b(dm);
1495 /* Toggle RX path to avoid RX dead zone issue */
1496 odm_set_bb_reg(dm, 0x808, MASKBYTE0, 0x0);
1497 odm_set_bb_reg(dm, 0x808, MASKBYTE0,
1498 (dm->rx_ant_status | (dm->rx_ant_status << 4)));
1500 /* Toggle IGI to let RF enter RX mode */
1501 IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1502 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI - 2);
1503 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI - 2);
1504 odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), IGI);
1505 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), IGI);
1509 "%s(): Success to switch bandwidth (bw: %d, primary ch: %d)\n",
1510 __func__, bandwidth, primary_ch_idx);
1514 bool config_phydm_switch_channel_bw_8822b(struct phy_dm_struct *dm,
1515 u8 central_ch, u8 primary_ch_idx,
1516 enum odm_bw bandwidth)
1519 if (!config_phydm_switch_band_8822b(dm, central_ch))
1522 /* Switch channel */
1523 if (!config_phydm_switch_channel_8822b(dm, central_ch))
1526 /* Switch bandwidth */
1527 if (!config_phydm_switch_bandwidth_8822b(dm, primary_ch_idx, bandwidth))
1533 bool config_phydm_trx_mode_8822b(struct phy_dm_struct *dm,
1534 enum odm_rf_path tx_path,
1535 enum odm_rf_path rx_path, bool is_tx2_path)
1537 bool rf_reg_status = true;
1542 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s()=====================>\n",
1545 if (dm->is_disable_phy_api) {
1546 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1547 "%s(): disable PHY API for debug!!\n", __func__);
1551 if ((tx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1552 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1553 "%s(): Wrong TX setting (TX: 0x%x)\n", __func__,
1558 if ((rx_path & (~(ODM_RF_A | ODM_RF_B))) != 0) {
1559 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1560 "%s(): Wrong RX setting (RX: 0x%x)\n", __func__,
1565 /* RF mode of path-A and path-B */
1566 /* Cannot shut down path-A, beacause synthesizer will be shut down when
1567 * path-A is in shut down mode
1569 if ((tx_path | rx_path) & ODM_RF_A)
1570 odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x3231);
1572 odm_set_bb_reg(dm, 0xc08, MASKLWORD, 0x1111);
1574 if ((tx_path | rx_path) & ODM_RF_B)
1575 odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x3231);
1577 odm_set_bb_reg(dm, 0xe08, MASKLWORD, 0x1111);
1579 /* Set TX antenna by Nsts */
1580 odm_set_bb_reg(dm, 0x93c, (BIT(19) | BIT(18)), 0x3);
1581 odm_set_bb_reg(dm, 0x80c, (BIT(29) | BIT(28)), 0x1);
1583 /* Control CCK TX path by 0xa07[7] */
1584 odm_set_bb_reg(dm, 0x80c, BIT(30), 0x1);
1586 /* TX logic map and TX path en for Nsts = 1, and CCK TX path*/
1587 if (tx_path & ODM_RF_A) {
1588 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x001);
1589 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
1590 } else if (tx_path & ODM_RF_B) {
1591 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x002);
1592 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
1595 /* TX logic map and TX path en for Nsts = 2*/
1596 if ((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))
1597 odm_set_bb_reg(dm, 0x940, 0xfff0, 0x01);
1599 odm_set_bb_reg(dm, 0x940, 0xfff0, 0x43);
1601 /* TX path enable */
1602 odm_set_bb_reg(dm, 0x80c, MASKBYTE0, ((tx_path << 4) | tx_path));
1604 /* Tx2path for 1ss */
1605 if (!((tx_path == ODM_RF_A) || (tx_path == ODM_RF_B))) {
1606 if (is_tx2_path || dm->mp_mode) {
1608 odm_set_bb_reg(dm, 0x93c, 0xfff00000, 0x043);
1611 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
1615 /* Always disable MRC for CCK CCA */
1616 odm_set_bb_reg(dm, 0xa2c, BIT(22), 0x0);
1618 /* Always disable MRC for CCK barker */
1619 odm_set_bb_reg(dm, 0xa2c, BIT(18), 0x0);
1621 /* CCK RX 1st and 2nd path setting*/
1622 if (rx_path & ODM_RF_A)
1623 odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x0);
1624 else if (rx_path & ODM_RF_B)
1625 odm_set_bb_reg(dm, 0xa04, 0x0f000000, 0x5);
1627 /* RX path enable */
1628 odm_set_bb_reg(dm, 0x808, MASKBYTE0, ((rx_path << 4) | rx_path));
1630 if ((rx_path == ODM_RF_A) || (rx_path == ODM_RF_B)) {
1633 /* Disable MRC for CCA */
1634 /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x0); */
1636 /* Disable MRC for barker */
1637 /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x0); */
1639 /* Disable CCK antenna diversity */
1640 /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1642 /* Disable Antenna weighting */
1643 odm_set_bb_reg(dm, 0x1904, BIT(16), 0x0);
1644 odm_set_bb_reg(dm, 0x800, BIT(28), 0x0);
1645 odm_set_bb_reg(dm, 0x850, BIT(23), 0x0);
1649 /* Enable MRC for CCA */
1650 /* odm_set_bb_reg(dm, 0xa2c, BIT22, 0x1); */
1652 /* Enable MRC for barker */
1653 /* odm_set_bb_reg(dm, 0xa2c, BIT18, 0x1); */
1655 /* Disable CCK antenna diversity */
1656 /* odm_set_bb_reg(dm, 0xa00, BIT15, 0x0); */
1658 /* Enable Antenna weighting */
1659 odm_set_bb_reg(dm, 0x1904, BIT(16), 0x1);
1660 odm_set_bb_reg(dm, 0x800, BIT(28), 0x1);
1661 odm_set_bb_reg(dm, 0x850, BIT(23), 0x1);
1664 /* Update TXRX antenna status for PHYDM */
1665 dm->tx_ant_status = (tx_path & 0x3);
1666 dm->rx_ant_status = (rx_path & 0x3);
1668 /* MP driver need to support path-B TX\RX */
1673 rf_reg_status & config_phydm_write_rf_reg_8822b(
1674 dm, ODM_RF_PATH_A, 0xef,
1675 RFREGOFFSETMASK, 0x80000);
1677 rf_reg_status & config_phydm_write_rf_reg_8822b(
1678 dm, ODM_RF_PATH_A, 0x33,
1679 RFREGOFFSETMASK, 0x00001);
1682 rf_reg33 = config_phydm_read_rf_reg_8822b(
1683 dm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK);
1685 if ((rf_reg33 == 0x00001) &&
1686 (config_phydm_read_rf_check_8822b(rf_reg33)))
1688 else if (counter == 100) {
1691 "%s(): Fail to set TRx mode setting, because writing RF mode table is fail\n",
1697 if ((dm->mp_mode) || *dm->antenna_test || (dm->normal_rx_path)) {
1698 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080e
1699 * 0xef 0x00000 suggested by Lucas
1702 rf_reg_status & config_phydm_write_rf_reg_8822b(
1703 dm, ODM_RF_PATH_A, 0xef,
1704 RFREGOFFSETMASK, 0x80000);
1706 rf_reg_status & config_phydm_write_rf_reg_8822b(
1707 dm, ODM_RF_PATH_A, 0x33,
1708 RFREGOFFSETMASK, 0x00001);
1710 rf_reg_status & config_phydm_write_rf_reg_8822b(
1711 dm, ODM_RF_PATH_A, 0x3e,
1712 RFREGOFFSETMASK, 0x00034);
1714 rf_reg_status & config_phydm_write_rf_reg_8822b(
1715 dm, ODM_RF_PATH_A, 0x3f,
1716 RFREGOFFSETMASK, 0x4080e);
1718 rf_reg_status & config_phydm_write_rf_reg_8822b(
1719 dm, ODM_RF_PATH_A, 0xef,
1720 RFREGOFFSETMASK, 0x00000);
1723 "%s(): MP mode or Antenna test mode!! support path-B TX and RX\n",
1726 /* 0xef 0x80000 0x33 0x00001 0x3e 0x00034 0x3f 0x4080c
1730 rf_reg_status & config_phydm_write_rf_reg_8822b(
1731 dm, ODM_RF_PATH_A, 0xef,
1732 RFREGOFFSETMASK, 0x80000);
1734 rf_reg_status & config_phydm_write_rf_reg_8822b(
1735 dm, ODM_RF_PATH_A, 0x33,
1736 RFREGOFFSETMASK, 0x00001);
1738 rf_reg_status & config_phydm_write_rf_reg_8822b(
1739 dm, ODM_RF_PATH_A, 0x3e,
1740 RFREGOFFSETMASK, 0x00034);
1742 rf_reg_status & config_phydm_write_rf_reg_8822b(
1743 dm, ODM_RF_PATH_A, 0x3f,
1744 RFREGOFFSETMASK, 0x4080c);
1746 rf_reg_status & config_phydm_write_rf_reg_8822b(
1747 dm, ODM_RF_PATH_A, 0xef,
1748 RFREGOFFSETMASK, 0x00000);
1751 "%s(): Normal mode!! Do not support path-B TX and RX\n",
1755 rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8822b(
1756 dm, ODM_RF_PATH_A, 0xef,
1757 RFREGOFFSETMASK, 0x00000);
1759 if (!rf_reg_status) {
1762 "%s(): Fail to set TRx mode setting (TX: 0x%x, RX: 0x%x), because writing RF register is fail\n",
1763 __func__, tx_path, rx_path);
1767 /* Toggle IGI to let RF enter RX mode,
1768 * because BB doesn't send 3-wire command when RX path is enable
1770 IGI = (u8)odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm));
1771 odm_write_dig(dm, IGI - 2);
1772 odm_write_dig(dm, IGI);
1774 /* Modify CCA parameters */
1775 phydm_ccapar_by_rxpath_8822b(dm);
1776 phydm_ccapar_by_rfe_8822b(dm);
1777 phydm_rfe_8822b(dm, central_ch_8822b);
1781 "%s(): Success to set TRx mode setting (TX: 0x%x, RX: 0x%x)\n",
1782 __func__, tx_path, rx_path);
1786 bool config_phydm_parameter_init(struct phy_dm_struct *dm,
1787 enum odm_parameter_init type)
1789 if (type == ODM_PRE_SETTING) {
1790 odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x0);
1791 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1792 "%s(): Pre setting: disable OFDM and CCK block\n",
1794 } else if (type == ODM_POST_SETTING) {
1795 odm_set_bb_reg(dm, 0x808, (BIT(28) | BIT(29)), 0x3);
1796 ODM_RT_TRACE(dm, ODM_PHY_CONFIG,
1797 "%s(): Post setting: enable OFDM and CCK block\n",
1799 reg82c_8822b = odm_get_bb_reg(dm, 0x82c, MASKDWORD);
1800 reg838_8822b = odm_get_bb_reg(dm, 0x838, MASKDWORD);
1801 reg830_8822b = odm_get_bb_reg(dm, 0x830, MASKDWORD);
1802 reg83c_8822b = odm_get_bb_reg(dm, 0x83c, MASKDWORD);
1803 rega20_8822b = odm_get_bb_reg(dm, 0xa20, MASKDWORD);
1804 rega24_8822b = odm_get_bb_reg(dm, 0xa24, MASKDWORD);
1805 rega28_8822b = odm_get_bb_reg(dm, 0xa28, MASKDWORD);
1807 ODM_RT_TRACE(dm, ODM_PHY_CONFIG, "%s(): Wrong type!!\n",
1815 /* ======================================================================== */