1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
25 #ifndef __ODM_TYPES_H__
26 #define __ODM_TYPES_H__
28 /*Define Different SW team support*/
29 #define ODM_AP 0x01 /*BIT0*/
30 #define ODM_CE 0x04 /*BIT2*/
31 #define ODM_WIN 0x08 /*BIT3*/
32 #define ODM_ADSL 0x10 /*BIT4*/
33 #define ODM_IOT 0x20 /*BIT5*/
35 /*Deifne HW endian support*/
36 #define ODM_ENDIAN_BIG 0
37 #define ODM_ENDIAN_LITTLE 1
39 #define GET_PDM_ODM(__padapter) \
40 ((struct phy_dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
48 * Declare for ODM spin lock definition temporarily fro compile pass.
50 enum rt_spinlock_type {
58 RT_CHNLOP_SPINLOCK = 9,
59 RT_RF_OPERATE_SPINLOCK = 10,
60 RT_INITIAL_SPINLOCK = 11,
61 RT_RF_STATE_SPINLOCK =
62 12, /* For RF state. Added by Bruce, 2007-10-30. */
63 /* Shall we define Ndis 6.2 SpinLock Here ? */
64 RT_PORT_SPINLOCK = 16,
65 RT_VNIC_SPINLOCK = 17,
67 RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
69 rt_bt_data_spinlock = 25,
71 RT_WAPI_OPTION_SPINLOCK = 26,
72 RT_WAPI_RX_SPINLOCK = 27,
74 /* add for 92D CCK control issue */
75 RT_CCK_PAGEA_SPINLOCK = 28,
76 RT_BUFFER_SPINLOCK = 29,
77 RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
78 RT_GEN_TEMP_BUF_SPINLOCK = 31,
80 RT_FW_PS_SPINLOCK = 33,
81 RT_HW_TIMER_SPIN_LOCK = 34,
82 RT_MPT_WI_SPINLOCK = 35,
83 RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
84 RT_DBG_SPIN_LOCK = 37,
86 RT_PENDED_OID_SPINLOCK = 39,
87 RT_CHNLLIST_SPINLOCK = 40,
88 RT_INDIC_SPINLOCK = 41, /* protect indication */
90 RT_SYNC_IO_CNT_SPINLOCK = 43,
94 #include <asm/byteorder.h>
96 #if defined(__LITTLE_ENDIAN)
97 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
98 #elif defined(__BIG_ENDIAN)
99 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
107 #define MASKBYTE0 0xff
108 #define MASKBYTE1 0xff00
109 #define MASKBYTE2 0xff0000
110 #define MASKBYTE3 0xff000000
111 #define MASKHWORD 0xffff0000
112 #define MASKLWORD 0x0000ffff
113 #define MASKDWORD 0xffffffff
114 #define MASK7BITS 0x7f
115 #define MASK12BITS 0xfff
116 #define MASKH4BITS 0xf0000000
117 #define MASK20BITS 0xfffff
118 #define MASKOFDM_D 0xffc00000
119 #define MASKCCK 0x3f3f3f3f
120 #define RFREGOFFSETMASK 0xfffff
121 #define MASKH3BYTES 0xffffff00
122 #define MASKL3BYTES 0x00ffffff
123 #define MASKBYTE2HIGHNIBBLE 0x00f00000
124 #define MASKBYTE3LOWNIBBLE 0x0f000000
125 #define MASKL3BYTES 0x00ffffff
126 #define RFREGOFFSETMASK 0xfffff
128 #include "phydm_features.h"
130 #endif /* __ODM_TYPES_H__ */