1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __PHYDMRAINFO_H__
27 #define __PHYDMRAINFO_H__
29 /*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/
30 /*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/
31 /*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/
32 /*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/
33 /*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
34 /*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask
35 *state and Phydm-lize partial ra mask
38 /*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to
39 *adjust PCR RA threshold
41 /*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
42 #define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem*/
44 #define FORCED_UPDATE_RAMASK_PERIOD 5
46 #define H2C_0X42_LENGTH 5
47 #define H2C_MAX_LENGTH 7
49 #define RA_FLOOR_UP_GAP 3
50 #define RA_FLOOR_TABLE_SIZE 7
52 #define ACTIVE_TP_THRESHOLD 150
53 #define RA_RETRY_DESCEND_NUM 2
54 #define RA_RETRY_LIMIT_LOW 4
55 #define RA_RETRY_LIMIT_HIGH 32
57 #define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */
58 #define RAINFO_STBC_STATE BIT(1)
59 /* #define RAINFO_LDPC_STATE BIT2 */
60 #define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */
61 #define RAINFO_SHURTCUT_STATE BIT(3)
62 #define RAINFO_SHURTCUT_FLAG BIT(4)
63 #define RAINFO_INIT_RSSI_RATE_STATE BIT(5)
64 #define RAINFO_BF_STATE BIT(6)
65 #define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */
67 #define RA_MASK_CCK 0xf
68 #define RA_MASK_OFDM 0xff0
69 #define RA_MASK_HT1SS 0xff000
70 #define RA_MASK_HT2SS 0xff00000
71 /*#define RA_MASK_MCS3SS */
72 #define RA_MASK_HT4SS 0xff0
73 #define RA_MASK_VHT1SS 0x3ff000
74 #define RA_MASK_VHT2SS 0xffc00000
76 #define RA_FIRST_MACID 0
78 #define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init
80 #define DM_RATR_STA_INIT 0
81 #define DM_RATR_STA_HIGH 1
82 #define DM_RATR_STA_MIDDLE 2
83 #define DM_RATR_STA_LOW 3
84 #define DM_RATR_STA_ULTRA_LOW 4
86 enum phydm_ra_arfr_num {
95 enum phydm_ra_dbg_para {
96 RADBG_PCR_TH_OFFSET = 0,
97 RADBG_RTY_PENALTY = 1,
100 RADBG_TRATE_UP_TABLE = 4,
101 RADBG_TRATE_DOWN_TABLE = 5,
102 RADBG_TRYING_NECESSARY = 6,
103 RADBG_TDROPING_NECESSARY = 7,
104 RADBG_RATE_UP_RTY_RATIO = 8,
105 RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
107 RADBG_DEBUG_MONITOR1 = 0xc,
108 RADBG_DEBUG_MONITOR2 = 0xd,
109 RADBG_DEBUG_MONITOR3 = 0xe,
110 RADBG_DEBUG_MONITOR4 = 0xf,
111 RADBG_DEBUG_MONITOR5 = 0x10,
115 enum phydm_wireless_mode {
116 PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
117 PHYDM_WIRELESS_MODE_A = 0x01,
118 PHYDM_WIRELESS_MODE_B = 0x02,
119 PHYDM_WIRELESS_MODE_G = 0x04,
120 PHYDM_WIRELESS_MODE_AUTO = 0x08,
121 PHYDM_WIRELESS_MODE_N_24G = 0x10,
122 PHYDM_WIRELESS_MODE_N_5G = 0x20,
123 PHYDM_WIRELESS_MODE_AC_5G = 0x40,
124 PHYDM_WIRELESS_MODE_AC_24G = 0x80,
125 PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
126 PHYDM_WIRELESS_MODE_MAX = 0x800,
127 PHYDM_WIRELESS_MODE_ALL = 0xFFFF
130 enum phydm_rateid_idx {
131 PHYDM_BGN_40M_2SS = 0,
132 PHYDM_BGN_40M_1SS = 1,
133 PHYDM_BGN_20M_2SS = 2,
134 PHYDM_BGN_20M_1SS = 3,
140 PHYDM_ARFR0_AC_2SS = 9,
141 PHYDM_ARFR1_AC_1SS = 10,
142 PHYDM_ARFR2_AC_2G_1SS = 11,
143 PHYDM_ARFR3_AC_2G_2SS = 12,
144 PHYDM_ARFR4_AC_3SS = 13,
145 PHYDM_ARFR5_N_3SS = 14
148 enum phydm_rf_type_def {
174 u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
175 u8 highest_client_tx_order;
176 u16 highest_client_tx_rate_order;
177 u8 power_tracking_flag;
178 u8 RA_threshold_offset;
179 u8 RA_offset_direction;
180 u8 force_update_ra_mask_count;
183 struct odm_rate_adaptive {
184 /* dm_type_by_fw/dm_type_by_driver */
186 /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */
188 /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */
190 /* Cur RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW*/
193 /* if RSSI > ldpc_thres => switch from LPDC to BCC */
195 bool is_lower_rts_rate;
200 void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
201 char *output, u32 *_out_len);
203 void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
204 char *output, u32 *_out_len);
206 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
208 void odm_ra_para_adjust(void *dm_void);
210 void phydm_ra_dynamic_retry_count(void *dm_void);
212 void phydm_ra_dynamic_retry_limit(void *dm_void);
214 void phydm_ra_dynamic_rate_id_on_assoc(void *dm_void, u8 wireless_mode,
217 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
219 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
221 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
223 void phydm_ra_info_watchdog(void *dm_void);
225 void phydm_ra_info_init(void *dm_void);
227 void odm_rssi_monitor_init(void *dm_void);
229 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
230 u8 RA_threshold_offset);
232 void odm_rssi_monitor_check(void *dm_void);
234 void phydm_init_ra_info(void *dm_void);
236 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
238 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
240 void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
241 u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
242 u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_in,
245 void odm_rate_adaptive_mask_init(void *dm_void);
247 void odm_refresh_rate_adaptive_mask(void *dm_void);
249 void odm_refresh_rate_adaptive_mask_mp(void *dm_void);
251 void odm_refresh_rate_adaptive_mask_ce(void *dm_void);
253 void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void);
255 u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state);
257 bool odm_ra_state_check(void *dm_void, s32 RSSI, bool is_force_update,
260 void odm_refresh_basic_rate_mask(void *dm_void);
261 void odm_ra_post_action_on_assoc(void *dm);
263 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect);
265 void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h);
267 void phydm_update_pwr_track(void *dm_void, u8 rate);
269 #endif /*#ifndef __ODMRAINFO_H__*/