1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
15 #ifndef __PHYDMPREDEFINE_H__
16 #define __PHYDMPREDEFINE_H__
18 /* 1 ============================================================
20 * 1 ============================================================
23 #define PHYDM_CODE_BASE "PHYDM_TRUNK"
24 #define PHYDM_RELEASE_DATE "00000000"
27 #define MAX_PATH_NUM_8188E 1
28 #define MAX_PATH_NUM_8192E 2
29 #define MAX_PATH_NUM_8723B 1
30 #define MAX_PATH_NUM_8812A 2
31 #define MAX_PATH_NUM_8821A 1
32 #define MAX_PATH_NUM_8814A 4
33 #define MAX_PATH_NUM_8822B 2
34 #define MAX_PATH_NUM_8821B 2
35 #define MAX_PATH_NUM_8703B 1
36 #define MAX_PATH_NUM_8188F 1
37 #define MAX_PATH_NUM_8723D 1
38 #define MAX_PATH_NUM_8197F 2
39 #define MAX_PATH_NUM_8821C 1
41 #define MAX_PATH_NUM_8710B 1
44 #define ODM_RF_PATH_MAX 2
45 #define ODM_RF_PATH_MAX_JAGUAR 4
48 #define PHYDM_A BIT(0)
49 #define PHYDM_B BIT(1)
50 #define PHYDM_C BIT(2)
51 #define PHYDM_D BIT(3)
52 #define PHYDM_AB (BIT(0) | BIT(1))
53 #define PHYDM_AC (BIT(0) | BIT(2))
54 #define PHYDM_AD (BIT(0) | BIT(3))
55 #define PHYDM_BC (BIT(1) | BIT(2))
56 #define PHYDM_BD (BIT(1) | BIT(3))
57 #define PHYDM_CD (BIT(2) | BIT(3))
58 #define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
59 #define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
60 #define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
61 #define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
62 #define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
65 /* defined in wifi.h (32+1) */
66 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
68 #define RX_SMOOTH_FACTOR 20
70 /* -----MGN rate--------------------------------- */
161 #define ODM_MGN_MCS0_SG 0xc0
162 #define ODM_MGN_MCS1_SG 0xc1
163 #define ODM_MGN_MCS2_SG 0xc2
164 #define ODM_MGN_MCS3_SG 0xc3
165 #define ODM_MGN_MCS4_SG 0xc4
166 #define ODM_MGN_MCS5_SG 0xc5
167 #define ODM_MGN_MCS6_SG 0xc6
168 #define ODM_MGN_MCS7_SG 0xc7
169 #define ODM_MGN_MCS8_SG 0xc8
170 #define ODM_MGN_MCS9_SG 0xc9
171 #define ODM_MGN_MCS10_SG 0xca
172 #define ODM_MGN_MCS11_SG 0xcb
173 #define ODM_MGN_MCS12_SG 0xcc
174 #define ODM_MGN_MCS13_SG 0xcd
175 #define ODM_MGN_MCS14_SG 0xce
176 #define ODM_MGN_MCS15_SG 0xcf
178 /* -----DESC rate--------------------------------- */
180 #define ODM_RATEMCS15_SG 0x1c
181 #define ODM_RATEMCS32 0x20
183 /* CCK Rates, TxHT = 0 */
184 #define ODM_RATE1M 0x00
185 #define ODM_RATE2M 0x01
186 #define ODM_RATE5_5M 0x02
187 #define ODM_RATE11M 0x03
188 /* OFDM Rates, TxHT = 0 */
189 #define ODM_RATE6M 0x04
190 #define ODM_RATE9M 0x05
191 #define ODM_RATE12M 0x06
192 #define ODM_RATE18M 0x07
193 #define ODM_RATE24M 0x08
194 #define ODM_RATE36M 0x09
195 #define ODM_RATE48M 0x0A
196 #define ODM_RATE54M 0x0B
197 /* MCS Rates, TxHT = 1 */
198 #define ODM_RATEMCS0 0x0C
199 #define ODM_RATEMCS1 0x0D
200 #define ODM_RATEMCS2 0x0E
201 #define ODM_RATEMCS3 0x0F
202 #define ODM_RATEMCS4 0x10
203 #define ODM_RATEMCS5 0x11
204 #define ODM_RATEMCS6 0x12
205 #define ODM_RATEMCS7 0x13
206 #define ODM_RATEMCS8 0x14
207 #define ODM_RATEMCS9 0x15
208 #define ODM_RATEMCS10 0x16
209 #define ODM_RATEMCS11 0x17
210 #define ODM_RATEMCS12 0x18
211 #define ODM_RATEMCS13 0x19
212 #define ODM_RATEMCS14 0x1A
213 #define ODM_RATEMCS15 0x1B
214 #define ODM_RATEMCS16 0x1C
215 #define ODM_RATEMCS17 0x1D
216 #define ODM_RATEMCS18 0x1E
217 #define ODM_RATEMCS19 0x1F
218 #define ODM_RATEMCS20 0x20
219 #define ODM_RATEMCS21 0x21
220 #define ODM_RATEMCS22 0x22
221 #define ODM_RATEMCS23 0x23
222 #define ODM_RATEMCS24 0x24
223 #define ODM_RATEMCS25 0x25
224 #define ODM_RATEMCS26 0x26
225 #define ODM_RATEMCS27 0x27
226 #define ODM_RATEMCS28 0x28
227 #define ODM_RATEMCS29 0x29
228 #define ODM_RATEMCS30 0x2A
229 #define ODM_RATEMCS31 0x2B
230 #define ODM_RATEVHTSS1MCS0 0x2C
231 #define ODM_RATEVHTSS1MCS1 0x2D
232 #define ODM_RATEVHTSS1MCS2 0x2E
233 #define ODM_RATEVHTSS1MCS3 0x2F
234 #define ODM_RATEVHTSS1MCS4 0x30
235 #define ODM_RATEVHTSS1MCS5 0x31
236 #define ODM_RATEVHTSS1MCS6 0x32
237 #define ODM_RATEVHTSS1MCS7 0x33
238 #define ODM_RATEVHTSS1MCS8 0x34
239 #define ODM_RATEVHTSS1MCS9 0x35
240 #define ODM_RATEVHTSS2MCS0 0x36
241 #define ODM_RATEVHTSS2MCS1 0x37
242 #define ODM_RATEVHTSS2MCS2 0x38
243 #define ODM_RATEVHTSS2MCS3 0x39
244 #define ODM_RATEVHTSS2MCS4 0x3A
245 #define ODM_RATEVHTSS2MCS5 0x3B
246 #define ODM_RATEVHTSS2MCS6 0x3C
247 #define ODM_RATEVHTSS2MCS7 0x3D
248 #define ODM_RATEVHTSS2MCS8 0x3E
249 #define ODM_RATEVHTSS2MCS9 0x3F
250 #define ODM_RATEVHTSS3MCS0 0x40
251 #define ODM_RATEVHTSS3MCS1 0x41
252 #define ODM_RATEVHTSS3MCS2 0x42
253 #define ODM_RATEVHTSS3MCS3 0x43
254 #define ODM_RATEVHTSS3MCS4 0x44
255 #define ODM_RATEVHTSS3MCS5 0x45
256 #define ODM_RATEVHTSS3MCS6 0x46
257 #define ODM_RATEVHTSS3MCS7 0x47
258 #define ODM_RATEVHTSS3MCS8 0x48
259 #define ODM_RATEVHTSS3MCS9 0x49
260 #define ODM_RATEVHTSS4MCS0 0x4A
261 #define ODM_RATEVHTSS4MCS1 0x4B
262 #define ODM_RATEVHTSS4MCS2 0x4C
263 #define ODM_RATEVHTSS4MCS3 0x4D
264 #define ODM_RATEVHTSS4MCS4 0x4E
265 #define ODM_RATEVHTSS4MCS5 0x4F
266 #define ODM_RATEVHTSS4MCS6 0x50
267 #define ODM_RATEVHTSS4MCS7 0x51
268 #define ODM_RATEVHTSS4MCS8 0x52
269 #define ODM_RATEVHTSS4MCS9 0x53
271 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
273 /* 1 ============================================================
275 * 1 ============================================================
278 /* ODM_CMNINFO_INTERFACE */
286 /* ODM_CMNINFO_IC_TYPE */
288 ODM_RTL8188E = BIT(0),
289 ODM_RTL8812 = BIT(1),
290 ODM_RTL8821 = BIT(2),
291 ODM_RTL8192E = BIT(3),
292 ODM_RTL8723B = BIT(4),
293 ODM_RTL8814A = BIT(5),
294 ODM_RTL8881A = BIT(6),
295 ODM_RTL8822B = BIT(7),
296 ODM_RTL8703B = BIT(8),
297 ODM_RTL8195A = BIT(9),
298 ODM_RTL8188F = BIT(10),
299 ODM_RTL8723D = BIT(11),
300 ODM_RTL8197F = BIT(12),
301 ODM_RTL8821C = BIT(13),
302 ODM_RTL8814B = BIT(14),
303 ODM_RTL8198F = BIT(15),
304 /* JJ ADD 20161014 */
305 ODM_RTL8710B = BIT(16),
308 /* JJ ADD 20161014 */
310 (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | \
311 ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | \
312 ODM_RTL8195A | ODM_RTL8710B)
313 #define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
314 #define ODM_IC_3SS (ODM_RTL8814A)
315 #define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
317 /* JJ ADD 20161014 */
318 #define ODM_IC_11N_SERIES \
319 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | \
320 ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
321 #define ODM_IC_11AC_SERIES \
322 (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | \
323 ODM_RTL8822B | ODM_RTL8821C)
324 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
325 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
326 #define ODM_IC_TXBF_SUPPORT \
327 (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | \
328 ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
329 #define ODM_IC_11N_GAIN_IDX_EDCCA \
330 (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | \
331 ODM_RTL8197F | ODM_RTL8710B)
332 #define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
333 #define ODM_IC_PHY_STATUE_NEW_TYPE \
334 (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | \
337 #define PHYDM_IC_8051_SERIES \
338 (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | \
339 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
340 #define PHYDM_IC_3081_SERIES \
341 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
343 #define PHYDM_IC_SUPPORT_LA_MODE \
344 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
346 /* JJ ADD 20161014 */
348 /* ODM_CMNINFO_CUT_VER */
349 enum odm_cut_version {
363 /* ODM_CMNINFO_FAB_VER */
369 /* ODM_CMNINFO_RF_TYPE
371 * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
400 enum odm_mac_phy_mode {
406 enum odm_bt_coexist {
413 /* ODM_CMNINFO_OP_MODE */
414 enum odm_operation_mode {
415 ODM_NO_LINK = BIT(0),
418 ODM_POWERSAVE = BIT(3),
419 ODM_AP_MODE = BIT(4),
420 ODM_CLIENT_MODE = BIT(5),
422 ODM_WIFI_DIRECT = BIT(7),
423 ODM_WIFI_DISPLAY = BIT(8),
426 /* ODM_CMNINFO_WM_MODE */
427 enum odm_wireless_mode {
428 ODM_WM_UNKNOWN = 0x0,
432 ODM_WM_N24G = BIT(3),
434 ODM_WM_AUTO = BIT(5),
438 /* ODM_CMNINFO_BAND */
446 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
447 enum phydm_sec_chnl_offset {
453 /* ODM_CMNINFO_SEC_MODE */
461 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
476 /* ODM_CMNINFO_CHNL */
478 /* ODM_CMNINFO_BOARD_TYPE */
479 enum odm_board_type {
480 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
481 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
482 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
483 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
485 BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
487 BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
489 BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
490 ODM_BOARD_EXT_PA_5G =
491 BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
492 ODM_BOARD_EXT_LNA_5G =
493 BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
496 enum odm_package_type {
497 ODM_PACKAGE_DEFAULT = 0,
498 ODM_PACKAGE_QFN68 = BIT(0),
499 ODM_PACKAGE_TFBGA90 = BIT(1),
500 ODM_PACKAGE_TFBGA79 = BIT(2),
552 TYPE_GLNA10 = 0xAAAA,
553 TYPE_GLNA11 = 0xAAFF,
554 TYPE_GLNA12 = 0xFF00,
555 TYPE_GLNA13 = 0xFF55,
556 TYPE_GLNA14 = 0xFFAA,
557 TYPE_GLNA15 = 0xFFFF,
571 TYPE_ALNA10 = 0xAAAA,
572 TYPE_ALNA11 = 0xAAFF,
573 TYPE_ALNA12 = 0xFF00,
574 TYPE_ALNA13 = 0xFF55,
575 TYPE_ALNA14 = 0xFFAA,
576 TYPE_ALNA15 = 0xFFFF,
579 enum odm_rf_radio_path {
580 ODM_RF_PATH_A = 0, /* Radio path A */
581 ODM_RF_PATH_B = 1, /* Radio path B */
582 ODM_RF_PATH_C = 2, /* Radio path C */
583 ODM_RF_PATH_D = 3, /* Radio path D */
594 /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */
597 enum odm_parameter_init {
599 ODM_POST_SETTING = 1,