drivers/staging/rtlwifi/phydm/phydm_pre_define.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 #ifndef __PHYDMPREDEFINE_H__
  16 #define __PHYDMPREDEFINE_H__
  17
  18 /* 1 ============================================================
  19  * 1  Definition
  20  * 1 ============================================================
  21  */
  22
  23 #define PHYDM_CODE_BASE "PHYDM_TRUNK"
  24 #define PHYDM_RELEASE_DATE "00000000"
  25
  26 /* Max path of IC */
  27 #define MAX_PATH_NUM_8188E 1
  28 #define MAX_PATH_NUM_8192E 2
  29 #define MAX_PATH_NUM_8723B 1
  30 #define MAX_PATH_NUM_8812A 2
  31 #define MAX_PATH_NUM_8821A 1
  32 #define MAX_PATH_NUM_8814A 4
  33 #define MAX_PATH_NUM_8822B 2
  34 #define MAX_PATH_NUM_8821B 2
  35 #define MAX_PATH_NUM_8703B 1
  36 #define MAX_PATH_NUM_8188F 1
  37 #define MAX_PATH_NUM_8723D 1
  38 #define MAX_PATH_NUM_8197F 2
  39 #define MAX_PATH_NUM_8821C 1
  40 /* JJ ADD 20161014 */
  41 #define MAX_PATH_NUM_8710B 1
  42
  43 /* Max RF path */
  44 #define ODM_RF_PATH_MAX 2
  45 #define ODM_RF_PATH_MAX_JAGUAR 4
  46
  47 /*Bit define path*/
  48 #define PHYDM_A BIT(0)
  49 #define PHYDM_B BIT(1)
  50 #define PHYDM_C BIT(2)
  51 #define PHYDM_D BIT(3)
  52 #define PHYDM_AB (BIT(0) | BIT(1))
  53 #define PHYDM_AC (BIT(0) | BIT(2))
  54 #define PHYDM_AD (BIT(0) | BIT(3))
  55 #define PHYDM_BC (BIT(1) | BIT(2))
  56 #define PHYDM_BD (BIT(1) | BIT(3))
  57 #define PHYDM_CD (BIT(2) | BIT(3))
  58 #define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
  59 #define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
  60 #define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
  61 #define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
  62 #define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  63
  64 /* number of entry */
  65 /* defined in wifi.h (32+1) */
  66 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
  67
  68 #define RX_SMOOTH_FACTOR 20
  69
  70 /* -----MGN rate--------------------------------- */
  71
  72 enum ODM_MGN_RATE {
  73         ODM_MGN_1M = 0x02,
  74         ODM_MGN_2M = 0x04,
  75         ODM_MGN_5_5M = 0x0B,
  76         ODM_MGN_6M = 0x0C,
  77         ODM_MGN_9M = 0x12,
  78         ODM_MGN_11M = 0x16,
  79         ODM_MGN_12M = 0x18,
  80         ODM_MGN_18M = 0x24,
  81         ODM_MGN_24M = 0x30,
  82         ODM_MGN_36M = 0x48,
  83         ODM_MGN_48M = 0x60,
  84         ODM_MGN_54M = 0x6C,
  85         ODM_MGN_MCS32 = 0x7F,
  86         ODM_MGN_MCS0,
  87         ODM_MGN_MCS1,
  88         ODM_MGN_MCS2,
  89         ODM_MGN_MCS3,
  90         ODM_MGN_MCS4,
  91         ODM_MGN_MCS5,
  92         ODM_MGN_MCS6,
  93         ODM_MGN_MCS7,
  94         ODM_MGN_MCS8,
  95         ODM_MGN_MCS9,
  96         ODM_MGN_MCS10,
  97         ODM_MGN_MCS11,
  98         ODM_MGN_MCS12,
  99         ODM_MGN_MCS13,
 100         ODM_MGN_MCS14,
 101         ODM_MGN_MCS15,
 102         ODM_MGN_MCS16,
 103         ODM_MGN_MCS17,
 104         ODM_MGN_MCS18,
 105         ODM_MGN_MCS19,
 106         ODM_MGN_MCS20,
 107         ODM_MGN_MCS21,
 108         ODM_MGN_MCS22,
 109         ODM_MGN_MCS23,
 110         ODM_MGN_MCS24,
 111         ODM_MGN_MCS25,
 112         ODM_MGN_MCS26,
 113         ODM_MGN_MCS27,
 114         ODM_MGN_MCS28,
 115         ODM_MGN_MCS29,
 116         ODM_MGN_MCS30,
 117         ODM_MGN_MCS31,
 118         ODM_MGN_VHT1SS_MCS0,
 119         ODM_MGN_VHT1SS_MCS1,
 120         ODM_MGN_VHT1SS_MCS2,
 121         ODM_MGN_VHT1SS_MCS3,
 122         ODM_MGN_VHT1SS_MCS4,
 123         ODM_MGN_VHT1SS_MCS5,
 124         ODM_MGN_VHT1SS_MCS6,
 125         ODM_MGN_VHT1SS_MCS7,
 126         ODM_MGN_VHT1SS_MCS8,
 127         ODM_MGN_VHT1SS_MCS9,
 128         ODM_MGN_VHT2SS_MCS0,
 129         ODM_MGN_VHT2SS_MCS1,
 130         ODM_MGN_VHT2SS_MCS2,
 131         ODM_MGN_VHT2SS_MCS3,
 132         ODM_MGN_VHT2SS_MCS4,
 133         ODM_MGN_VHT2SS_MCS5,
 134         ODM_MGN_VHT2SS_MCS6,
 135         ODM_MGN_VHT2SS_MCS7,
 136         ODM_MGN_VHT2SS_MCS8,
 137         ODM_MGN_VHT2SS_MCS9,
 138         ODM_MGN_VHT3SS_MCS0,
 139         ODM_MGN_VHT3SS_MCS1,
 140         ODM_MGN_VHT3SS_MCS2,
 141         ODM_MGN_VHT3SS_MCS3,
 142         ODM_MGN_VHT3SS_MCS4,
 143         ODM_MGN_VHT3SS_MCS5,
 144         ODM_MGN_VHT3SS_MCS6,
 145         ODM_MGN_VHT3SS_MCS7,
 146         ODM_MGN_VHT3SS_MCS8,
 147         ODM_MGN_VHT3SS_MCS9,
 148         ODM_MGN_VHT4SS_MCS0,
 149         ODM_MGN_VHT4SS_MCS1,
 150         ODM_MGN_VHT4SS_MCS2,
 151         ODM_MGN_VHT4SS_MCS3,
 152         ODM_MGN_VHT4SS_MCS4,
 153         ODM_MGN_VHT4SS_MCS5,
 154         ODM_MGN_VHT4SS_MCS6,
 155         ODM_MGN_VHT4SS_MCS7,
 156         ODM_MGN_VHT4SS_MCS8,
 157         ODM_MGN_VHT4SS_MCS9,
 158         ODM_MGN_UNKNOWN
 159 };
 160
 161 #define ODM_MGN_MCS0_SG 0xc0
 162 #define ODM_MGN_MCS1_SG 0xc1
 163 #define ODM_MGN_MCS2_SG 0xc2
 164 #define ODM_MGN_MCS3_SG 0xc3
 165 #define ODM_MGN_MCS4_SG 0xc4
 166 #define ODM_MGN_MCS5_SG 0xc5
 167 #define ODM_MGN_MCS6_SG 0xc6
 168 #define ODM_MGN_MCS7_SG 0xc7
 169 #define ODM_MGN_MCS8_SG 0xc8
 170 #define ODM_MGN_MCS9_SG 0xc9
 171 #define ODM_MGN_MCS10_SG 0xca
 172 #define ODM_MGN_MCS11_SG 0xcb
 173 #define ODM_MGN_MCS12_SG 0xcc
 174 #define ODM_MGN_MCS13_SG 0xcd
 175 #define ODM_MGN_MCS14_SG 0xce
 176 #define ODM_MGN_MCS15_SG 0xcf
 177
 178 /* -----DESC rate--------------------------------- */
 179
 180 #define ODM_RATEMCS15_SG 0x1c
 181 #define ODM_RATEMCS32 0x20
 182
 183 /* CCK Rates, TxHT = 0 */
 184 #define ODM_RATE1M 0x00
 185 #define ODM_RATE2M 0x01
 186 #define ODM_RATE5_5M 0x02
 187 #define ODM_RATE11M 0x03
 188 /* OFDM Rates, TxHT = 0 */
 189 #define ODM_RATE6M 0x04
 190 #define ODM_RATE9M 0x05
 191 #define ODM_RATE12M 0x06
 192 #define ODM_RATE18M 0x07
 193 #define ODM_RATE24M 0x08
 194 #define ODM_RATE36M 0x09
 195 #define ODM_RATE48M 0x0A
 196 #define ODM_RATE54M 0x0B
 197 /* MCS Rates, TxHT = 1 */
 198 #define ODM_RATEMCS0 0x0C
 199 #define ODM_RATEMCS1 0x0D
 200 #define ODM_RATEMCS2 0x0E
 201 #define ODM_RATEMCS3 0x0F
 202 #define ODM_RATEMCS4 0x10
 203 #define ODM_RATEMCS5 0x11
 204 #define ODM_RATEMCS6 0x12
 205 #define ODM_RATEMCS7 0x13
 206 #define ODM_RATEMCS8 0x14
 207 #define ODM_RATEMCS9 0x15
 208 #define ODM_RATEMCS10 0x16
 209 #define ODM_RATEMCS11 0x17
 210 #define ODM_RATEMCS12 0x18
 211 #define ODM_RATEMCS13 0x19
 212 #define ODM_RATEMCS14 0x1A
 213 #define ODM_RATEMCS15 0x1B
 214 #define ODM_RATEMCS16 0x1C
 215 #define ODM_RATEMCS17 0x1D
 216 #define ODM_RATEMCS18 0x1E
 217 #define ODM_RATEMCS19 0x1F
 218 #define ODM_RATEMCS20 0x20
 219 #define ODM_RATEMCS21 0x21
 220 #define ODM_RATEMCS22 0x22
 221 #define ODM_RATEMCS23 0x23
 222 #define ODM_RATEMCS24 0x24
 223 #define ODM_RATEMCS25 0x25
 224 #define ODM_RATEMCS26 0x26
 225 #define ODM_RATEMCS27 0x27
 226 #define ODM_RATEMCS28 0x28
 227 #define ODM_RATEMCS29 0x29
 228 #define ODM_RATEMCS30 0x2A
 229 #define ODM_RATEMCS31 0x2B
 230 #define ODM_RATEVHTSS1MCS0 0x2C
 231 #define ODM_RATEVHTSS1MCS1 0x2D
 232 #define ODM_RATEVHTSS1MCS2 0x2E
 233 #define ODM_RATEVHTSS1MCS3 0x2F
 234 #define ODM_RATEVHTSS1MCS4 0x30
 235 #define ODM_RATEVHTSS1MCS5 0x31
 236 #define ODM_RATEVHTSS1MCS6 0x32
 237 #define ODM_RATEVHTSS1MCS7 0x33
 238 #define ODM_RATEVHTSS1MCS8 0x34
 239 #define ODM_RATEVHTSS1MCS9 0x35
 240 #define ODM_RATEVHTSS2MCS0 0x36
 241 #define ODM_RATEVHTSS2MCS1 0x37
 242 #define ODM_RATEVHTSS2MCS2 0x38
 243 #define ODM_RATEVHTSS2MCS3 0x39
 244 #define ODM_RATEVHTSS2MCS4 0x3A
 245 #define ODM_RATEVHTSS2MCS5 0x3B
 246 #define ODM_RATEVHTSS2MCS6 0x3C
 247 #define ODM_RATEVHTSS2MCS7 0x3D
 248 #define ODM_RATEVHTSS2MCS8 0x3E
 249 #define ODM_RATEVHTSS2MCS9 0x3F
 250 #define ODM_RATEVHTSS3MCS0 0x40
 251 #define ODM_RATEVHTSS3MCS1 0x41
 252 #define ODM_RATEVHTSS3MCS2 0x42
 253 #define ODM_RATEVHTSS3MCS3 0x43
 254 #define ODM_RATEVHTSS3MCS4 0x44
 255 #define ODM_RATEVHTSS3MCS5 0x45
 256 #define ODM_RATEVHTSS3MCS6 0x46
 257 #define ODM_RATEVHTSS3MCS7 0x47
 258 #define ODM_RATEVHTSS3MCS8 0x48
 259 #define ODM_RATEVHTSS3MCS9 0x49
 260 #define ODM_RATEVHTSS4MCS0 0x4A
 261 #define ODM_RATEVHTSS4MCS1 0x4B
 262 #define ODM_RATEVHTSS4MCS2 0x4C
 263 #define ODM_RATEVHTSS4MCS3 0x4D
 264 #define ODM_RATEVHTSS4MCS4 0x4E
 265 #define ODM_RATEVHTSS4MCS5 0x4F
 266 #define ODM_RATEVHTSS4MCS6 0x50
 267 #define ODM_RATEVHTSS4MCS7 0x51
 268 #define ODM_RATEVHTSS4MCS8 0x52
 269 #define ODM_RATEVHTSS4MCS9 0x53
 270
 271 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
 272
 273 /* 1 ============================================================
 274  * 1  enumeration
 275  * 1 ============================================================
 276  */
 277
 278 /*      ODM_CMNINFO_INTERFACE */
 279 enum odm_interface {
 280         ODM_ITRF_PCIE = 0x1,
 281         ODM_ITRF_USB = 0x2,
 282         ODM_ITRF_SDIO = 0x4,
 283         ODM_ITRF_ALL = 0x7,
 284 };
 285
 286 /* ODM_CMNINFO_IC_TYPE */
 287 enum odm_ic_type {
 288         ODM_RTL8188E = BIT(0),
 289         ODM_RTL8812 = BIT(1),
 290         ODM_RTL8821 = BIT(2),
 291         ODM_RTL8192E = BIT(3),
 292         ODM_RTL8723B = BIT(4),
 293         ODM_RTL8814A = BIT(5),
 294         ODM_RTL8881A = BIT(6),
 295         ODM_RTL8822B = BIT(7),
 296         ODM_RTL8703B = BIT(8),
 297         ODM_RTL8195A = BIT(9),
 298         ODM_RTL8188F = BIT(10),
 299         ODM_RTL8723D = BIT(11),
 300         ODM_RTL8197F = BIT(12),
 301         ODM_RTL8821C = BIT(13),
 302         ODM_RTL8814B = BIT(14),
 303         ODM_RTL8198F = BIT(15),
 304         /* JJ ADD 20161014 */
 305         ODM_RTL8710B = BIT(16),
 306 };
 307
 308 /* JJ ADD 20161014 */
 309 #define ODM_IC_1SS                                                             \
 310         (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B |           \
 311          ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |            \
 312          ODM_RTL8195A | ODM_RTL8710B)
 313 #define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
 314 #define ODM_IC_3SS (ODM_RTL8814A)
 315 #define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
 316
 317 /* JJ ADD 20161014 */
 318 #define ODM_IC_11N_SERIES                                                      \
 319         (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |           \
 320          ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
 321 #define ODM_IC_11AC_SERIES                                                     \
 322         (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A |             \
 323          ODM_RTL8822B | ODM_RTL8821C)
 324 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
 325 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
 326 #define ODM_IC_TXBF_SUPPORT                                                    \
 327         (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A |             \
 328          ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 329 #define ODM_IC_11N_GAIN_IDX_EDCCA                                              \
 330         (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D |           \
 331          ODM_RTL8197F | ODM_RTL8710B)
 332 #define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
 333 #define ODM_IC_PHY_STATUE_NEW_TYPE                                             \
 334         (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C |           \
 335          ODM_RTL8710B)
 336
 337 #define PHYDM_IC_8051_SERIES                                                   \
 338         (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E |             \
 339          ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
 340 #define PHYDM_IC_3081_SERIES                                                   \
 341         (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 342
 343 #define PHYDM_IC_SUPPORT_LA_MODE                                               \
 344         (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 345
 346 /* JJ ADD 20161014 */
 347
 348 /* ODM_CMNINFO_CUT_VER */
 349 enum odm_cut_version {
 350         ODM_CUT_A = 0,
 351         ODM_CUT_B = 1,
 352         ODM_CUT_C = 2,
 353         ODM_CUT_D = 3,
 354         ODM_CUT_E = 4,
 355         ODM_CUT_F = 5,
 356
 357         ODM_CUT_I = 8,
 358         ODM_CUT_J = 9,
 359         ODM_CUT_K = 10,
 360         ODM_CUT_TEST = 15,
 361 };
 362
 363 /* ODM_CMNINFO_FAB_VER */
 364 enum odm_fab {
 365         ODM_TSMC = 0,
 366         ODM_UMC = 1,
 367 };
 368
 369 /* ODM_CMNINFO_RF_TYPE
 370  *
 371  * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
 372  */
 373 enum odm_rf_path {
 374         ODM_RF_A = BIT(0),
 375         ODM_RF_B = BIT(1),
 376         ODM_RF_C = BIT(2),
 377         ODM_RF_D = BIT(3),
 378 };
 379
 380 enum odm_rf_tx_num {
 381         ODM_1T = 1,
 382         ODM_2T = 2,
 383         ODM_3T = 3,
 384         ODM_4T = 4,
 385 };
 386
 387 enum odm_rf_type {
 388         ODM_1T1R,
 389         ODM_1T2R,
 390         ODM_2T2R,
 391         ODM_2T2R_GREEN,
 392         ODM_2T3R,
 393         ODM_2T4R,
 394         ODM_3T3R,
 395         ODM_3T4R,
 396         ODM_4T4R,
 397         ODM_XTXR
 398 };
 399
 400 enum odm_mac_phy_mode {
 401         ODM_SMSP = 0,
 402         ODM_DMSP = 1,
 403         ODM_DMDP = 2,
 404 };
 405
 406 enum odm_bt_coexist {
 407         ODM_BT_BUSY = 1,
 408         ODM_BT_ON = 2,
 409         ODM_BT_OFF = 3,
 410         ODM_BT_NONE = 4,
 411 };
 412
 413 /* ODM_CMNINFO_OP_MODE */
 414 enum odm_operation_mode {
 415         ODM_NO_LINK = BIT(0),
 416         ODM_LINK = BIT(1),
 417         ODM_SCAN = BIT(2),
 418         ODM_POWERSAVE = BIT(3),
 419         ODM_AP_MODE = BIT(4),
 420         ODM_CLIENT_MODE = BIT(5),
 421         ODM_AD_HOC = BIT(6),
 422         ODM_WIFI_DIRECT = BIT(7),
 423         ODM_WIFI_DISPLAY = BIT(8),
 424 };
 425
 426 /* ODM_CMNINFO_WM_MODE */
 427 enum odm_wireless_mode {
 428         ODM_WM_UNKNOWN = 0x0,
 429         ODM_WM_B = BIT(0),
 430         ODM_WM_G = BIT(1),
 431         ODM_WM_A = BIT(2),
 432         ODM_WM_N24G = BIT(3),
 433         ODM_WM_N5G = BIT(4),
 434         ODM_WM_AUTO = BIT(5),
 435         ODM_WM_AC = BIT(6),
 436 };
 437
 438 /* ODM_CMNINFO_BAND */
 439 enum odm_band_type {
 440         ODM_BAND_2_4G = 0,
 441         ODM_BAND_5G,
 442         ODM_BAND_ON_BOTH,
 443         ODM_BANDMAX
 444 };
 445
 446 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
 447 enum phydm_sec_chnl_offset {
 448         PHYDM_DONT_CARE = 0,
 449         PHYDM_BELOW = 1,
 450         PHYDM_ABOVE = 2
 451 };
 452
 453 /* ODM_CMNINFO_SEC_MODE */
 454 enum odm_security {
 455         ODM_SEC_OPEN = 0,
 456         ODM_SEC_WEP40 = 1,
 457         ODM_SEC_TKIP = 2,
 458         ODM_SEC_RESERVE = 3,
 459         ODM_SEC_AESCCMP = 4,
 460         ODM_SEC_WEP104 = 5,
 461         ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
 462         ODM_SEC_SMS4 = 7,
 463 };
 464
 465 /* ODM_CMNINFO_BW */
 466 enum odm_bw {
 467         ODM_BW20M = 0,
 468         ODM_BW40M = 1,
 469         ODM_BW80M = 2,
 470         ODM_BW160M = 3,
 471         ODM_BW5M = 4,
 472         ODM_BW10M = 5,
 473         ODM_BW_MAX = 6
 474 };
 475
 476 /* ODM_CMNINFO_CHNL */
 477
 478 /* ODM_CMNINFO_BOARD_TYPE */
 479 enum odm_board_type {
 480         ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
 481         ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
 482         ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
 483         ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
 484         ODM_BOARD_EXT_PA =
 485                 BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
 486         ODM_BOARD_EXT_LNA =
 487                 BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
 488         ODM_BOARD_EXT_TRSW =
 489                 BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
 490         ODM_BOARD_EXT_PA_5G =
 491                 BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
 492         ODM_BOARD_EXT_LNA_5G =
 493                 BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
 494 };
 495
 496 enum odm_package_type {
 497         ODM_PACKAGE_DEFAULT = 0,
 498         ODM_PACKAGE_QFN68 = BIT(0),
 499         ODM_PACKAGE_TFBGA90 = BIT(1),
 500         ODM_PACKAGE_TFBGA79 = BIT(2),
 501 };
 502
 503 enum odm_type_gpa {
 504         TYPE_GPA0 = 0x0000,
 505         TYPE_GPA1 = 0x0055,
 506         TYPE_GPA2 = 0x00AA,
 507         TYPE_GPA3 = 0x00FF,
 508         TYPE_GPA4 = 0x5500,
 509         TYPE_GPA5 = 0x5555,
 510         TYPE_GPA6 = 0x55AA,
 511         TYPE_GPA7 = 0x55FF,
 512         TYPE_GPA8 = 0xAA00,
 513         TYPE_GPA9 = 0xAA55,
 514         TYPE_GPA10 = 0xAAAA,
 515         TYPE_GPA11 = 0xAAFF,
 516         TYPE_GPA12 = 0xFF00,
 517         TYPE_GPA13 = 0xFF55,
 518         TYPE_GPA14 = 0xFFAA,
 519         TYPE_GPA15 = 0xFFFF,
 520 };
 521
 522 enum odm_type_apa {
 523         TYPE_APA0 = 0x0000,
 524         TYPE_APA1 = 0x0055,
 525         TYPE_APA2 = 0x00AA,
 526         TYPE_APA3 = 0x00FF,
 527         TYPE_APA4 = 0x5500,
 528         TYPE_APA5 = 0x5555,
 529         TYPE_APA6 = 0x55AA,
 530         TYPE_APA7 = 0x55FF,
 531         TYPE_APA8 = 0xAA00,
 532         TYPE_APA9 = 0xAA55,
 533         TYPE_APA10 = 0xAAAA,
 534         TYPE_APA11 = 0xAAFF,
 535         TYPE_APA12 = 0xFF00,
 536         TYPE_APA13 = 0xFF55,
 537         TYPE_APA14 = 0xFFAA,
 538         TYPE_APA15 = 0xFFFF,
 539 };
 540
 541 enum odm_type_glna {
 542         TYPE_GLNA0 = 0x0000,
 543         TYPE_GLNA1 = 0x0055,
 544         TYPE_GLNA2 = 0x00AA,
 545         TYPE_GLNA3 = 0x00FF,
 546         TYPE_GLNA4 = 0x5500,
 547         TYPE_GLNA5 = 0x5555,
 548         TYPE_GLNA6 = 0x55AA,
 549         TYPE_GLNA7 = 0x55FF,
 550         TYPE_GLNA8 = 0xAA00,
 551         TYPE_GLNA9 = 0xAA55,
 552         TYPE_GLNA10 = 0xAAAA,
 553         TYPE_GLNA11 = 0xAAFF,
 554         TYPE_GLNA12 = 0xFF00,
 555         TYPE_GLNA13 = 0xFF55,
 556         TYPE_GLNA14 = 0xFFAA,
 557         TYPE_GLNA15 = 0xFFFF,
 558 };
 559
 560 enum odm_type_alna {
 561         TYPE_ALNA0 = 0x0000,
 562         TYPE_ALNA1 = 0x0055,
 563         TYPE_ALNA2 = 0x00AA,
 564         TYPE_ALNA3 = 0x00FF,
 565         TYPE_ALNA4 = 0x5500,
 566         TYPE_ALNA5 = 0x5555,
 567         TYPE_ALNA6 = 0x55AA,
 568         TYPE_ALNA7 = 0x55FF,
 569         TYPE_ALNA8 = 0xAA00,
 570         TYPE_ALNA9 = 0xAA55,
 571         TYPE_ALNA10 = 0xAAAA,
 572         TYPE_ALNA11 = 0xAAFF,
 573         TYPE_ALNA12 = 0xFF00,
 574         TYPE_ALNA13 = 0xFF55,
 575         TYPE_ALNA14 = 0xFFAA,
 576         TYPE_ALNA15 = 0xFFFF,
 577 };
 578
 579 enum odm_rf_radio_path {
 580         ODM_RF_PATH_A = 0, /* Radio path A */
 581         ODM_RF_PATH_B = 1, /* Radio path B */
 582         ODM_RF_PATH_C = 2, /* Radio path C */
 583         ODM_RF_PATH_D = 3, /* Radio path D */
 584         ODM_RF_PATH_AB,
 585         ODM_RF_PATH_AC,
 586         ODM_RF_PATH_AD,
 587         ODM_RF_PATH_BC,
 588         ODM_RF_PATH_BD,
 589         ODM_RF_PATH_CD,
 590         ODM_RF_PATH_ABC,
 591         ODM_RF_PATH_ACD,
 592         ODM_RF_PATH_BCD,
 593         ODM_RF_PATH_ABCD,
 594         /* ODM_RF_PATH_MAX,    */ /* Max RF number 90 support */
 595 };
 596
 597 enum odm_parameter_init {
 598         ODM_PRE_SETTING = 0,
 599         ODM_POST_SETTING = 1,
 600 };
 601
 602 #endif