1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __HALHWOUTSRC_H__
27 #define __HALHWOUTSRC_H__
29 /*--------------------------Define -------------------------------------------*/
30 #define CCK_RSSI_INIT_COUNT 5
32 #define RA_RSSI_STATE_INIT 0
33 #define RA_RSSI_STATE_SEND 1
34 #define RA_RSSI_STATE_HOLD 2
36 #define CFO_HW_RPT_2_MHZ(val) ((val << 1) + (val >> 1))
37 /* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */
39 #define AGC_DIFF_CONFIG_MP(ic, band) \
40 (odm_read_and_config_mp_##ic##_agc_tab_diff( \
41 dm, array_mp_##ic##_agc_tab_diff_##band, \
42 sizeof(array_mp_##ic##_agc_tab_diff_##band) / sizeof(u32)))
43 #define AGC_DIFF_CONFIG_TC(ic, band) \
44 (odm_read_and_config_tc_##ic##_agc_tab_diff( \
45 dm, array_tc_##ic##_agc_tab_diff_##band, \
46 sizeof(array_tc_##ic##_agc_tab_diff_##band) / sizeof(u32)))
48 #define AGC_DIFF_CONFIG(ic, band) \
51 AGC_DIFF_CONFIG_MP(ic, band); \
53 AGC_DIFF_CONFIG_TC(ic, band); \
56 /* ************************************************************
57 * structure and define
58 * *************************************************************/
60 struct phy_rx_agc_info {
61 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
62 u8 gain : 7, trsw : 1;
64 u8 trsw : 1, gain : 7;
68 struct phy_status_rpt_8192cd {
69 struct phy_rx_agc_info path_agc[2];
71 u8 cck_sig_qual_ofdm_pwdb_all;
72 u8 cck_agc_rpt_ofdm_cfosho_a;
73 u8 cck_rpt_b_ofdm_cfosho_b;
74 u8 rsvd_1; /*ch_corr_msb;*/
75 u8 noise_power_db_msb;
80 u8 noise_power_db_lsb;
83 u8 stream_target_csi[2];
87 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
88 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
92 u8 r_ant_train_en : 1;
95 #else /*_BIG_ENDIAN_ */
98 u8 r_ant_train_en : 1;
102 u8 antsel_rx_keep_2 : 1; /*ex_intf_flg:1;*/
106 struct phy_status_rpt_8812 {
108 u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
109 u8 chl_num_LSB; /*channel number[7:0]*/
110 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
111 u8 chl_num_MSB : 2; /*channel number[9:8]*/
112 u8 sub_chnl : 4; /*sub-channel location[3:0]*/
113 u8 r_RFMOD : 2; /*RF mode[1:0]*/
114 #else /*_BIG_ENDIAN_ */
121 u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/
122 s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 */
123 /*CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/
124 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
125 /*this should be checked again
126 *because the definition of 8812 and 8814 is different
129 u8 bt_RF_ch_MSB : 2; /*8812A:2'b0, 8814A: bt rf channel keep[7:6]*/
130 #else /*_BIG_ENDIAN_*/
136 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
137 u8 ant_div_sw_a : 1; /*8812A: ant_div_sw_a, 8814A: 1'b0*/
138 u8 ant_div_sw_b : 1; /*8812A: ant_div_sw_b, 8814A: 1'b0*/
139 u8 bt_RF_ch_LSB : 6; /*8812A: 6'b0, 8814A: bt rf channel keep[5:0]*/
140 #else /*_BIG_ENDIAN_ */
145 s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
146 u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
147 u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
150 s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
151 s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
154 u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
155 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
156 u8 PCTS_MSK_RPT_3 : 6; /*PCTS mask report[29:24]*/
157 u8 pcts_rpt_valid : 1; /*pcts_rpt_valid*/
158 u8 resvd_1 : 1; /*1'b0*/
159 #else /*_BIG_ENDIAN_*/
161 u8 pcts_rpt_valid : 1;
162 u8 PCTS_MSK_RPT_3 : 6;
164 s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 */
165 /* 8812A: 16'b0, 8814A: stream 3 and stream 4 RX EVM*/
168 u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 */
169 /* 8812A: stream 1 and 2 CSI, 8814A: path-C and path-D RX SNR*/
170 u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 */
171 /* path-C and path-D {TRSW, gain[6:0] }*/
174 s8 sigevm; /*signal field EVM*/
175 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
176 u8 antidx_antc : 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
177 u8 antidx_antd : 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
178 u8 dpdt_ctrl_keep : 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
179 u8 GNT_BT_keep : 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
180 #else /*_BIG_ENDIAN_*/
182 u8 dpdt_ctrl_keep : 1;
186 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
187 u8 antidx_anta : 3; /*antidx_anta[2:0]*/
188 u8 antidx_antb : 3; /*antidx_antb[2:0]*/
189 u8 hw_antsw_occur : 2; /*1'b0*/
190 #else /*_BIG_ENDIAN_*/
191 u8 hw_antsw_occur : 2;
197 void phydm_reset_rssi_for_dm(struct phy_dm_struct *dm, u8 station_id);
199 void odm_init_rssi_for_dm(struct phy_dm_struct *dm);
201 void odm_phy_status_query(struct phy_dm_struct *dm,
202 struct dm_phy_status_info *phy_info, u8 *phy_status,
203 struct dm_per_pkt_info *pktinfo);
205 void odm_mac_status_query(struct phy_dm_struct *dm, u8 *mac_status, u8 mac_id,
206 bool is_packet_match_bssid, bool is_packet_to_self,
207 bool is_packet_beacon);
210 odm_config_rf_with_tx_pwr_track_header_file(struct phy_dm_struct *dm);
213 odm_config_rf_with_header_file(struct phy_dm_struct *dm,
214 enum odm_rf_config_type config_type,
215 enum odm_rf_radio_path e_rf_path);
218 odm_config_bb_with_header_file(struct phy_dm_struct *dm,
219 enum odm_bb_config_type config_type);
221 enum hal_status odm_config_mac_with_header_file(struct phy_dm_struct *dm);
224 odm_config_fw_with_header_file(struct phy_dm_struct *dm,
225 enum odm_fw_config_type config_type,
226 u8 *p_firmware, u32 *size);
228 u32 odm_get_hw_img_version(struct phy_dm_struct *dm);
230 s32 odm_signal_scale_mapping(struct phy_dm_struct *dm, s32 curr_sig);
232 /*For 8822B only!! need to move to FW finally */
233 /*==============================================*/
234 void phydm_rx_phy_status_new_type(struct phy_dm_struct *phydm, u8 *phy_status,
235 struct dm_per_pkt_info *pktinfo,
236 struct dm_phy_status_info *phy_info);
238 bool phydm_query_is_mu_api(struct phy_dm_struct *phydm, u8 ppdu_idx,
239 u8 *p_data_rate, u8 *p_gid);
241 struct phy_status_rpt_jaguar2_type0 {
245 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
258 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
270 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
288 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
313 struct phy_status_rpt_jaguar2_type1 {
317 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
325 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
328 u8 hw_antsw_occu : 1;
338 u8 hw_antsw_occu : 1;
345 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
363 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
373 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
388 s8 rxevm[4]; /* s(8,1) */
391 s8 cfo_tail[4]; /* s(8,7) */
394 s8 rxsnr[4]; /* s(8,1) */
397 struct phy_status_rpt_jaguar2_type2 {
401 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
409 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
412 u8 hw_antsw_occu : 1;
422 u8 hw_antsw_occu : 1;
428 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
436 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
450 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
487 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
500 u32 query_phydm_trx_capability(struct phy_dm_struct *dm);
502 u32 query_phydm_stbc_capability(struct phy_dm_struct *dm);
504 u32 query_phydm_ldpc_capability(struct phy_dm_struct *dm);
506 u32 query_phydm_txbf_parameters(struct phy_dm_struct *dm);
508 u32 query_phydm_txbf_capability(struct phy_dm_struct *dm);
510 #endif /*#ifndef __HALHWOUTSRC_H__*/