drivers/staging/rtlwifi/phydm/phydm_debug.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __ODM_DBG_H__
  27 #define __ODM_DBG_H__
  28
  29 /*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
  30 /*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
  31 #define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
  32 #define ODM_DBG_TRACE 5
  33
  34 /*FW DBG MSG*/
  35 #define RATE_DECISION BIT(0)
  36 #define INIT_RA_TABLE BIT(1)
  37 #define RATE_UP BIT(2)
  38 #define RATE_DOWN BIT(3)
  39 #define TRY_DONE BIT(4)
  40 #define RA_H2C BIT(5)
  41 #define F_RATE_AP_RPT BIT(7)
  42
  43 /* -----------------------------------------------------------------------------
  44  * Define the tracing components
  45  *
  46  * -----------------------------------------------------------------------------
  47  */
  48 /*BB FW Functions*/
  49 #define PHYDM_FW_COMP_RA BIT(0)
  50 #define PHYDM_FW_COMP_MU BIT(1)
  51 #define PHYDM_FW_COMP_PATH_DIV BIT(2)
  52 #define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
  53
  54 /*BB Driver Functions*/
  55 #define ODM_COMP_DIG BIT(0)
  56 #define ODM_COMP_RA_MASK BIT(1)
  57 #define ODM_COMP_DYNAMIC_TXPWR BIT(2)
  58 #define ODM_COMP_FA_CNT BIT(3)
  59 #define ODM_COMP_RSSI_MONITOR BIT(4)
  60 #define ODM_COMP_SNIFFER BIT(5)
  61 #define ODM_COMP_ANT_DIV BIT(6)
  62 #define ODM_COMP_DFS BIT(7)
  63 #define ODM_COMP_NOISY_DETECT BIT(8)
  64 #define ODM_COMP_RATE_ADAPTIVE BIT(9)
  65 #define ODM_COMP_PATH_DIV BIT(10)
  66 #define ODM_COMP_CCX BIT(11)
  67
  68 #define ODM_COMP_DYNAMIC_PRICCA BIT(12)
  69 /*BIT13 TBD*/
  70 #define ODM_COMP_MP BIT(14)
  71 #define ODM_COMP_CFO_TRACKING BIT(15)
  72 #define ODM_COMP_ACS BIT(16)
  73 #define PHYDM_COMP_ADAPTIVITY BIT(17)
  74 #define PHYDM_COMP_RA_DBG BIT(18)
  75 #define PHYDM_COMP_TXBF BIT(19)
  76 /* MAC Functions */
  77 #define ODM_COMP_EDCA_TURBO BIT(20)
  78 #define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
  79 #define ODM_FW_DEBUG_TRACE BIT(22)
  80 /* RF Functions */
  81 /*BIT23 TBD*/
  82 #define ODM_COMP_TX_PWR_TRACK BIT(24)
  83 /*BIT25 TBD*/
  84 #define ODM_COMP_CALIBRATION BIT(26)
  85 /* Common Functions */
  86 /*BIT27 TBD*/
  87 #define ODM_PHY_CONFIG BIT(28)
  88 #define ODM_COMP_INIT BIT(29)
  89 #define ODM_COMP_COMMON BIT(30)
  90 #define ODM_COMP_API BIT(31)
  91
  92 #define ODM_COMP_UNCOND 0xFFFFFFFF
  93
  94 /*------------------------Export Marco Definition---------------------------*/
  95
  96 #define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
  97
  98 #define ODM_RT_TRACE(dm, comp, fmt, ...)                                       \
  99         do {                                                                   \
 100                 if (((comp) & dm->debug_components) ||                         \
 101                     ((comp) == ODM_COMP_UNCOND))                               \
 102                         RT_TRACE(dm->adapter, COMP_PHYDM, DBG_DMESG, fmt,      \
 103                                  ##__VA_ARGS__);                               \
 104         } while (0)
 105
 106 #define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
 107 #define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
 108 #define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
 109 #define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
 110
 111 void phydm_init_debug_setting(struct phy_dm_struct *dm);
 112
 113 u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
 114
 115 void phydm_release_bb_dbg_port(void *dm_void);
 116
 117 u32 phydm_get_bb_dbg_port_value(void *dm_void);
 118
 119 void phydm_basic_dbg_message(void *dm_void);
 120
 121 #define PHYDM_DBGPRINT 0
 122 #define MAX_ARGC 20
 123 #define MAX_ARGV 16
 124 #define DCMD_DECIMAL "%d"
 125 #define DCMD_CHAR "%c"
 126 #define DCMD_HEX "%x"
 127
 128 #define PHYDM_SSCANF(x, y, z)                                                  \
 129         do {                                                                   \
 130                 if (sscanf(x, y, z) != 1)                                      \
 131                         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,                      \
 132                                      "%s:%d sscanf fail!", __func__,           \
 133                                      __LINE__);                                \
 134         } while (0)
 135
 136 #define PHYDM_VAST_INFO_SNPRINTF(msg, ...)                                     \
 137         do {                                                                   \
 138                 snprintf(msg, ##__VA_ARGS__);                                  \
 139                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output);                     \
 140         } while (0)
 141
 142 #if (PHYDM_DBGPRINT == 1)
 143 #define PHYDM_SNPRINTF(msg, ...)                                               \
 144         do {                                                                   \
 145                 snprintf(msg, ##__VA_ARGS__);                                  \
 146                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output);                     \
 147         } while (0)
 148 #else
 149 #define PHYDM_SNPRINTF(msg, ...)                                               \
 150         do {                                                                   \
 151                 if (out_len > used)                                            \
 152                         used += snprintf(msg, ##__VA_ARGS__);                  \
 153         } while (0)
 154 #endif
 155
 156 void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
 157                          u32 *_out_len);
 158 s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
 159               char *output, u32 out_len);
 160 void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][16], u32 input_num,
 161                       u8 flag, char *output, u32 out_len);
 162
 163 bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
 164                         enum odm_rf_path rx_path, bool is_tx2_path);
 165
 166 void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
 167                            u32 monitor_mode, u32 macid);
 168
 169 void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
 170
 171 void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
 172
 173 void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
 174
 175 #endif /* __ODM_DBG_H__ */