1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
18 /*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/
19 /*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/
20 #define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/
21 #define ODM_DBG_TRACE 5
24 #define RATE_DECISION BIT(0)
25 #define INIT_RA_TABLE BIT(1)
26 #define RATE_UP BIT(2)
27 #define RATE_DOWN BIT(3)
28 #define TRY_DONE BIT(4)
30 #define F_RATE_AP_RPT BIT(7)
32 /* -----------------------------------------------------------------------------
33 * Define the tracing components
35 * -----------------------------------------------------------------------------
38 #define PHYDM_FW_COMP_RA BIT(0)
39 #define PHYDM_FW_COMP_MU BIT(1)
40 #define PHYDM_FW_COMP_PATH_DIV BIT(2)
41 #define PHYDM_FW_COMP_PHY_CONFIG BIT(3)
43 /*BB Driver Functions*/
44 #define ODM_COMP_DIG BIT(0)
45 #define ODM_COMP_RA_MASK BIT(1)
46 #define ODM_COMP_DYNAMIC_TXPWR BIT(2)
47 #define ODM_COMP_FA_CNT BIT(3)
48 #define ODM_COMP_RSSI_MONITOR BIT(4)
49 #define ODM_COMP_SNIFFER BIT(5)
50 #define ODM_COMP_ANT_DIV BIT(6)
51 #define ODM_COMP_DFS BIT(7)
52 #define ODM_COMP_NOISY_DETECT BIT(8)
53 #define ODM_COMP_RATE_ADAPTIVE BIT(9)
54 #define ODM_COMP_PATH_DIV BIT(10)
55 #define ODM_COMP_CCX BIT(11)
57 #define ODM_COMP_DYNAMIC_PRICCA BIT(12)
59 #define ODM_COMP_MP BIT(14)
60 #define ODM_COMP_CFO_TRACKING BIT(15)
61 #define ODM_COMP_ACS BIT(16)
62 #define PHYDM_COMP_ADAPTIVITY BIT(17)
63 #define PHYDM_COMP_RA_DBG BIT(18)
64 #define PHYDM_COMP_TXBF BIT(19)
66 #define ODM_COMP_EDCA_TURBO BIT(20)
67 #define ODM_COMP_DYNAMIC_RX_PATH BIT(21)
68 #define ODM_FW_DEBUG_TRACE BIT(22)
71 #define ODM_COMP_TX_PWR_TRACK BIT(24)
73 #define ODM_COMP_CALIBRATION BIT(26)
74 /* Common Functions */
76 #define ODM_PHY_CONFIG BIT(28)
77 #define ODM_COMP_INIT BIT(29)
78 #define ODM_COMP_COMMON BIT(30)
79 #define ODM_COMP_API BIT(31)
81 #define ODM_COMP_UNCOND 0xFFFFFFFF
83 /*------------------------Export Marco Definition---------------------------*/
85 #define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA)
87 #define ODM_RT_TRACE(dm, comp, fmt, ...) \
89 if (((comp) & dm->debug_components) || \
90 ((comp) == ODM_COMP_UNCOND)) \
91 RT_TRACE(dm->adapter, COMP_PHYDM, DBG_DMESG, fmt, \
95 #define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/
96 #define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/
97 #define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/
98 #define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/
100 void phydm_init_debug_setting(struct phy_dm_struct *dm);
102 u8 phydm_set_bb_dbg_port(void *dm_void, u8 curr_dbg_priority, u32 debug_port);
104 void phydm_release_bb_dbg_port(void *dm_void);
106 u32 phydm_get_bb_dbg_port_value(void *dm_void);
108 void phydm_basic_dbg_message(void *dm_void);
110 #define PHYDM_DBGPRINT 0
113 #define DCMD_DECIMAL "%d"
114 #define DCMD_CHAR "%c"
115 #define DCMD_HEX "%x"
117 #define PHYDM_SSCANF(x, y, z) \
119 if (sscanf(x, y, z) != 1) \
120 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, \
121 "%s:%d sscanf fail!", __func__, \
125 #define PHYDM_VAST_INFO_SNPRINTF(msg, ...) \
127 snprintf(msg, ##__VA_ARGS__); \
128 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
131 #if (PHYDM_DBGPRINT == 1)
132 #define PHYDM_SNPRINTF(msg, ...) \
134 snprintf(msg, ##__VA_ARGS__); \
135 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, output); \
138 #define PHYDM_SNPRINTF(msg, ...) \
140 if (out_len > used) \
141 used += snprintf(msg, ##__VA_ARGS__); \
145 void phydm_basic_profile(void *dm_void, u32 *_used, char *output,
147 s32 phydm_cmd(struct phy_dm_struct *dm, char *input, u32 in_len, u8 flag,
148 char *output, u32 out_len);
149 void phydm_cmd_parser(struct phy_dm_struct *dm, char input[][16], u32 input_num,
150 u8 flag, char *output, u32 out_len);
152 bool phydm_api_trx_mode(struct phy_dm_struct *dm, enum odm_rf_path tx_path,
153 enum odm_rf_path rx_path, bool is_tx2_path);
155 void phydm_fw_trace_en_h2c(void *dm_void, bool enable, u32 fw_debug_component,
156 u32 monitor_mode, u32 macid);
158 void phydm_fw_trace_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
160 void phydm_fw_trace_handler_code(void *dm_void, u8 *buffer, u8 cmd_len);
162 void phydm_fw_trace_handler_8051(void *dm_void, u8 *cmd_buf, u8 cmd_len);
164 #endif /* __ODM_DBG_H__ */