1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __PHYDMANTDIV_H__
27 #define __PHYDMANTDIV_H__
32 * 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
33 * 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
34 * 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
35 * by BT, because antenna diversity only works when BT is disable
37 * 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
39 * 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
40 * for 8723B, not from PHYDM
41 * 3.6 2015.11.16 Stanley
42 * 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
43 * 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
44 * 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
45 * add cmd for adjust truth table
47 #define ANTDIV_VERSION "3.9"
49 /* 1 ============================================================
51 * 1 ============================================================
54 #define ANTDIV_INIT 0xff
55 #define MAIN_ANT 1 /*ant A or ant Main or S1*/
56 #define AUX_ANT 2 /*AntB or ant Aux or S0*/
57 #define MAX_ANT 3 /* 3 for AP using*/
59 #define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
62 #define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
66 #define SUPPORT_RF_PATH_NUM 4
67 #define SUPPORT_BEAM_PATTERN_NUM 4
68 #define NUM_ANTENNA_8821A 2
70 #define SUPPORT_BEAM_SET_PATTERN_NUM 8
72 #define NO_FIX_TX_ANT 0
73 #define FIX_TX_AT_MAIN 1
74 #define FIX_AUX_AT_MAIN 2
76 /* Antenna Diversty Control type */
77 #define ODM_AUTO_ANT 0
78 #define ODM_FIX_MAIN_ANT 1
79 #define ODM_FIX_AUX_ANT 2
81 #define ODM_N_ANTDIV_SUPPORT \
82 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
83 ODM_RTL8723D | ODM_RTL8195A)
84 #define ODM_AC_ANTDIV_SUPPORT \
85 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
86 ODM_RTL8822B | ODM_RTL8814B)
87 #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
88 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
89 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
91 #define ODM_ANTDIV_2G_SUPPORT_IC \
92 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
93 ODM_RTL8188F | ODM_RTL8723D)
94 #define ODM_ANTDIV_5G_SUPPORT_IC \
95 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
97 #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
99 #define ODM_ANTDIV_2G BIT(0)
100 #define ODM_ANTDIV_5G BIT(1)
111 #define RSSI_METHOD 0
113 #define CRC32_METHOD 2
115 #define INIT_ANTDIV_TIMMER 0
116 #define CANCEL_ANTDIV_TIMMER 1
117 #define RELEASE_ANTDIV_TIMMER 2
122 #define evm_rssi_th_high 25
123 #define evm_rssi_th_low 20
125 #define NORMAL_STATE_MIAN 1
126 #define NORMAL_STATE_AUX 2
127 #define TRAINING_STATE 3
129 #define FORCE_RSSI_DIFF 10
134 #define DIVON_CSIOFF 1
135 #define DIVOFF_CSION 2
137 #define BDC_DIV_TRAIN_STATE 0
138 #define bdc_bfer_train_state 1
139 #define BDC_DECISION_STATE 2
140 #define BDC_BF_HOLD_STATE 3
141 #define BDC_DIV_HOLD_STATE 4
147 #define BDC_MODE_NULL 0xff
149 /*SW S0S1 antenna diversity*/
150 #define SWAW_STEP_INIT 0xff
151 #define SWAW_STEP_PEEK 0
152 #define SWAW_STEP_DETERMINE 1
154 #define RSSI_CHECK_RESET_PERIOD 10
155 #define RSSI_CHECK_THRESHOLD 50
157 /*Hong Lin Smart antenna*/
158 #define HL_SMTANT_2WIRE_DATA_LEN 24
160 /* 1 ============================================================
162 * 1 ============================================================
165 struct sw_antenna_switch {
166 u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
167 *than check this antenna again
176 u8 train_time_flag; /*base on RSSI difference between two antennas*/
177 struct timer_list phydm_sw_antenna_switch_timer;
178 u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
179 bool is_sw_ant_div_by_ctrl_frame;
181 /* AntDect (Before link Antenna Switch check) need to be moved*/
182 u16 single_ant_counter;
183 u16 dual_ant_counter;
184 u16 aux_fail_detec_counter;
186 u8 swas_no_link_state;
187 u32 swas_no_link_bk_reg948;
188 bool ANTA_ON; /*To indicate ant A is or not*/
189 bool ANTB_ON; /*To indicate ant B is on or not*/
190 bool pre_aux_fail_detec;
191 bool rssi_ant_dect_result;
196 struct fast_antenna_training {
207 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
208 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
209 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
210 u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
211 u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
212 u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
213 u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
214 u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
215 u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
216 u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
217 u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
220 bool is_become_linked;
222 u8 idx_ant_div_counter_2g;
223 u8 idx_ant_div_counter_5g;
226 u32 cck_ctrl_frame_cnt_main;
227 u32 cck_ctrl_frame_cnt_aux;
228 u32 ofdm_ctrl_frame_cnt_main;
229 u32 ofdm_ctrl_frame_cnt_aux;
230 u32 main_ant_ctrl_frame_sum;
231 u32 aux_ant_ctrl_frame_sum;
232 u32 main_ant_ctrl_frame_cnt;
233 u32 aux_ant_ctrl_frame_cnt;
236 bool enable_ctrl_frame_antdiv;
237 bool use_ctrl_frame_antdiv;
239 u8 *p_force_tx_ant_by_desc;
240 u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
241 *outer parameter later
247 /* 1 ============================================================
249 * 1 ============================================================
252 /*Fast antenna training*/
254 FAT_BEFORE_LINK_STATE = 0,
255 FAT_PREPARE_STATE = 1,
256 FAT_TRAINING_STATE = 2,
257 FAT_DECISION_STATE = 3
262 CG_TRX_HW_ANTDIV = 0x01,
263 CGCS_RX_HW_ANTDIV = 0x02,
264 FIXED_HW_ANTDIV = 0x03,
265 CG_TRX_SMART_ANTDIV = 0x04,
266 CGCS_RX_SW_ANTDIV = 0x05,
267 /*8723B intrnal switch S0 S1*/
268 S0S1_SW_ANTDIV = 0x06,
269 /*TRX S0S1 diversity for 8723D*/
270 S0S1_TRX_HW_ANTDIV = 0x07,
271 /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
272 *each ant. is equipped with 4 antenna patterns
274 HL_SW_SMART_ANT_TYPE1 = 0x10,
275 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
276 HL_SW_SMART_ANT_TYPE2 = 0x11,
279 /* 1 ============================================================
280 * 1 function prototype
281 * 1 ============================================================
284 void odm_stop_antenna_switch_dm(void *dm_void);
286 void phydm_enable_antenna_diversity(void *dm_void);
288 void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
291 #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
293 void odm_sw_ant_div_rest_after_link(void *dm_void);
295 void odm_ant_div_reset(void *dm_void);
297 void odm_antenna_diversity_init(void *dm_void);
299 void odm_antenna_diversity(void *dm_void);
301 #endif /*#ifndef __ODMANTDIV_H__*/