1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
11 * Larry Finger <Larry.Finger@lwfinger.net>
13 *****************************************************************************/
15 #ifndef __PHYDMANTDIV_H__
16 #define __PHYDMANTDIV_H__
21 * 3.1 2015.07.29 YuChen, remove 92c 92d 8723a
22 * 3.2 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B
23 * 3.3 2015.08.12 Stanley. 8723B does not need to check the antenna is control
24 * by BT, because antenna diversity only works when BT is disable
26 * 3.4 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna
28 * 3.5 2015.10.07 Stanley Always check antenna detection result from BT-coex.
29 * for 8723B, not from PHYDM
30 * 3.6 2015.11.16 Stanley
31 * 3.7 2015.11.20 Dino Add SmartAnt FAT Patch
32 * 3.8 2015.12.21 Dino, Add SmartAnt dynamic training packet num
33 * 3.9 2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and
34 * add cmd for adjust truth table
36 #define ANTDIV_VERSION "3.9"
38 /* 1 ============================================================
40 * 1 ============================================================
43 #define ANTDIV_INIT 0xff
44 #define MAIN_ANT 1 /*ant A or ant Main or S1*/
45 #define AUX_ANT 2 /*AntB or ant Aux or S0*/
46 #define MAX_ANT 3 /* 3 for AP using*/
48 #define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D,
51 #define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D,
55 #define SUPPORT_RF_PATH_NUM 4
56 #define SUPPORT_BEAM_PATTERN_NUM 4
57 #define NUM_ANTENNA_8821A 2
59 #define SUPPORT_BEAM_SET_PATTERN_NUM 8
61 #define NO_FIX_TX_ANT 0
62 #define FIX_TX_AT_MAIN 1
63 #define FIX_AUX_AT_MAIN 2
65 /* Antenna Diversty Control type */
66 #define ODM_AUTO_ANT 0
67 #define ODM_FIX_MAIN_ANT 1
68 #define ODM_FIX_AUX_ANT 2
70 #define ODM_N_ANTDIV_SUPPORT \
71 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | \
72 ODM_RTL8723D | ODM_RTL8195A)
73 #define ODM_AC_ANTDIV_SUPPORT \
74 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | \
75 ODM_RTL8822B | ODM_RTL8814B)
76 #define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT)
77 #define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
78 #define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B)
80 #define ODM_ANTDIV_2G_SUPPORT_IC \
81 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | \
82 ODM_RTL8188F | ODM_RTL8723D)
83 #define ODM_ANTDIV_5G_SUPPORT_IC \
84 (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C)
86 #define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
88 #define ODM_ANTDIV_2G BIT(0)
89 #define ODM_ANTDIV_5G BIT(1)
100 #define RSSI_METHOD 0
102 #define CRC32_METHOD 2
104 #define INIT_ANTDIV_TIMMER 0
105 #define CANCEL_ANTDIV_TIMMER 1
106 #define RELEASE_ANTDIV_TIMMER 2
111 #define evm_rssi_th_high 25
112 #define evm_rssi_th_low 20
114 #define NORMAL_STATE_MIAN 1
115 #define NORMAL_STATE_AUX 2
116 #define TRAINING_STATE 3
118 #define FORCE_RSSI_DIFF 10
123 #define DIVON_CSIOFF 1
124 #define DIVOFF_CSION 2
126 #define BDC_DIV_TRAIN_STATE 0
127 #define bdc_bfer_train_state 1
128 #define BDC_DECISION_STATE 2
129 #define BDC_BF_HOLD_STATE 3
130 #define BDC_DIV_HOLD_STATE 4
136 #define BDC_MODE_NULL 0xff
138 /*SW S0S1 antenna diversity*/
139 #define SWAW_STEP_INIT 0xff
140 #define SWAW_STEP_PEEK 0
141 #define SWAW_STEP_DETERMINE 1
143 #define RSSI_CHECK_RESET_PERIOD 10
144 #define RSSI_CHECK_THRESHOLD 50
146 /*Hong Lin Smart antenna*/
147 #define HL_SMTANT_2WIRE_DATA_LEN 24
149 /* 1 ============================================================
151 * 1 ============================================================
154 struct sw_antenna_switch {
155 u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD",
156 *than check this antenna again
165 u8 train_time_flag; /*base on RSSI difference between two antennas*/
166 struct timer_list phydm_sw_antenna_switch_timer;
167 u32 pkt_cnt_sw_ant_div_by_ctrl_frame;
168 bool is_sw_ant_div_by_ctrl_frame;
170 /* AntDect (Before link Antenna Switch check) need to be moved*/
171 u16 single_ant_counter;
172 u16 dual_ant_counter;
173 u16 aux_fail_detec_counter;
175 u8 swas_no_link_state;
176 u32 swas_no_link_bk_reg948;
177 bool ANTA_ON; /*To indicate ant A is or not*/
178 bool ANTB_ON; /*To indicate ant B is on or not*/
179 bool pre_aux_fail_detec;
180 bool rssi_ant_dect_result;
185 struct fast_antenna_training {
196 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
197 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
198 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
199 u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
200 u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM];
201 u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
202 u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM];
203 u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
204 u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM];
205 u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
206 u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM];
209 bool is_become_linked;
211 u8 idx_ant_div_counter_2g;
212 u8 idx_ant_div_counter_5g;
215 u32 cck_ctrl_frame_cnt_main;
216 u32 cck_ctrl_frame_cnt_aux;
217 u32 ofdm_ctrl_frame_cnt_main;
218 u32 ofdm_ctrl_frame_cnt_aux;
219 u32 main_ant_ctrl_frame_sum;
220 u32 aux_ant_ctrl_frame_sum;
221 u32 main_ant_ctrl_frame_cnt;
222 u32 aux_ant_ctrl_frame_cnt;
225 bool enable_ctrl_frame_antdiv;
226 bool use_ctrl_frame_antdiv;
228 u8 *p_force_tx_ant_by_desc;
229 u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's
230 *outer parameter later
236 /* 1 ============================================================
238 * 1 ============================================================
241 /*Fast antenna training*/
243 FAT_BEFORE_LINK_STATE = 0,
244 FAT_PREPARE_STATE = 1,
245 FAT_TRAINING_STATE = 2,
246 FAT_DECISION_STATE = 3
251 CG_TRX_HW_ANTDIV = 0x01,
252 CGCS_RX_HW_ANTDIV = 0x02,
253 FIXED_HW_ANTDIV = 0x03,
254 CG_TRX_SMART_ANTDIV = 0x04,
255 CGCS_RX_SW_ANTDIV = 0x05,
256 /*8723B intrnal switch S0 S1*/
257 S0S1_SW_ANTDIV = 0x06,
258 /*TRX S0S1 diversity for 8723D*/
259 S0S1_TRX_HW_ANTDIV = 0x07,
260 /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and
261 *each ant. is equipped with 4 antenna patterns
263 HL_SW_SMART_ANT_TYPE1 = 0x10,
264 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/
265 HL_SW_SMART_ANT_TYPE2 = 0x11,
268 /* 1 ============================================================
269 * 1 function prototype
270 * 1 ============================================================
273 void odm_stop_antenna_switch_dm(void *dm_void);
275 void phydm_enable_antenna_diversity(void *dm_void);
277 void odm_set_ant_config(void *dm_void, u8 ant_setting /* 0=A, 1=B, 2=C, .... */
280 #define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link
282 void odm_sw_ant_div_rest_after_link(void *dm_void);
284 void odm_ant_div_reset(void *dm_void);
286 void odm_antenna_diversity_init(void *dm_void);
288 void odm_antenna_diversity(void *dm_void);
290 #endif /*#ifndef __ODMANTDIV_H__*/