drivers/staging/rtlwifi/phydm/phydm_adc_sampling.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25 #include "mp_precomp.h"
  26 #include "phydm_precomp.h"
  27
  28 static bool phydm_la_buffer_allocate(void *dm_void)
  29 {
  30         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  31         struct rt_adcsmp *adc_smp = &dm->adcsmp;
  32         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
  33         bool ret = false;
  34
  35         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA mode BufferAllocate]\n");
  36
  37         if (adc_smp_buf->length == 0) {
  38                 odm_allocate_memory(dm, (void **)&adc_smp_buf->octet,
  39                                     adc_smp_buf->buffer_size);
  40                 if (!adc_smp_buf->octet) {
  41                         ret = false;
  42                 } else {
  43                         adc_smp_buf->length = adc_smp_buf->buffer_size;
  44                         ret = true;
  45                 }
  46         }
  47
  48         return ret;
  49 }
  50
  51 static void phydm_la_get_tx_pkt_buf(void *dm_void)
  52 {
  53         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  54         struct rt_adcsmp *adc_smp = &dm->adcsmp;
  55         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
  56         u32 i = 0, value32, data_l = 0, data_h = 0;
  57         u32 addr, finish_addr;
  58         u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) -
  59                        1; /*end_addr = 0x3ffff;*/
  60         bool is_round_up;
  61         static u32 page = 0xFF;
  62         u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0;
  63
  64         odm_memory_set(dm, adc_smp_buf->octet, 0, adc_smp_buf->length);
  65         odm_write_1byte(dm, 0x0106, 0x69);
  66
  67         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "GetTxPktBuf\n");
  68
  69         value32 = odm_read_4byte(dm, 0x7c0);
  70         is_round_up = (bool)((value32 & BIT(31)) >> 31);
  71         /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
  72         finish_addr = (value32 & 0x7FFF0000) >> 16;
  73
  74         if (is_round_up) {
  75                 addr = (finish_addr + 1) << 3;
  76                 ODM_RT_TRACE(
  77                         dm, ODM_COMP_UNCOND,
  78                         "is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n",
  79                         is_round_up, finish_addr, value32);
  80                 /*Byte to 64Byte*/
  81                 smp_number = ((adc_smp_buf->buffer_size) >> 3);
  82         } else {
  83                 addr = adc_smp_buf->start_pos;
  84
  85                 addr_8byte = addr >> 3;
  86                 if (addr_8byte > finish_addr)
  87                         smp_number = addr_8byte - finish_addr;
  88                 else
  89                         smp_number = finish_addr - addr_8byte;
  90
  91                 ODM_RT_TRACE(
  92                         dm, ODM_COMP_UNCOND,
  93                         "is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
  94                         is_round_up, finish_addr, addr_8byte, smp_number);
  95         }
  96
  97         if (dm->support_ic_type & ODM_RTL8197F) {
  98                 /*64K byte*/
  99                 for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) {
 100                         if ((addr & 0xfff) == 0)
 101                                 odm_set_bb_reg(dm, 0x0140, MASKLWORD,
 102                                                0x780 + (addr >> 12));
 103                         data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
 104                                                 MASKDWORD);
 105                         data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
 106                                                 MASKDWORD);
 107
 108                         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
 109                                      data_l);
 110                 }
 111         } else {
 112                 while (addr != (finish_addr << 3)) {
 113                         if (page != (addr >> 12)) {
 114                                 /*Reg140=0x780+(addr>>12),
 115                                  *addr=0x30~0x3F, total 16 pages
 116                                  */
 117                                 page = (addr >> 12);
 118                         }
 119                         odm_set_bb_reg(dm, 0x0140, MASKLWORD, 0x780 + page);
 120
 121                         /*pDataL = 0x8000+(addr&0xfff);*/
 122                         data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
 123                                                 MASKDWORD);
 124                         data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) + 4,
 125                                                 MASKDWORD);
 126
 127                         adc_smp_buf->octet[i] = data_h;
 128                         adc_smp_buf->octet[i + 1] = data_l;
 129
 130                         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%08x%08x\n", data_h,
 131                                      data_l);
 132
 133                         i = i + 2;
 134
 135                         if ((addr + 8) >= end_addr)
 136                                 addr = adc_smp_buf->start_pos;
 137                         else
 138                                 addr = addr + 8;
 139
 140                         smp_cnt++;
 141                         if (smp_cnt >= (smp_number - 1))
 142                                 break;
 143                 }
 144                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "smp_cnt = ((%d))\n",
 145                              smp_cnt);
 146         }
 147 }
 148
 149 static void phydm_la_mode_set_mac_iq_dump(void *dm_void)
 150 {
 151         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 152         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 153         u32 reg_value;
 154
 155         odm_write_1byte(dm, 0x7c0, 0); /*clear all 0x7c0*/
 156         odm_set_mac_reg(dm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/
 157
 158         if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) {
 159                 adc_smp->is_bb_trigger = 0;
 160                 odm_set_mac_reg(dm, 0x7c0, BIT(2),
 161                                 1); /*polling bit for MAC mode*/
 162                 odm_set_mac_reg(
 163                         dm, 0x7c0, BIT(4) | BIT(3),
 164                         adc_smp->la_trigger_edge); /*trigger mode for MAC*/
 165
 166                 ODM_RT_TRACE(
 167                         dm, ODM_COMP_UNCOND,
 168                         "[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
 169                         adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel,
 170                         adc_smp->la_dbg_port);
 171                 /*[Set MAC Debug Port]*/
 172                 odm_set_mac_reg(dm, 0xF4, BIT(16), 1);
 173                 odm_set_mac_reg(dm, 0x38, 0xff0000, adc_smp->la_dbg_port);
 174                 odm_set_mac_reg(dm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask);
 175                 odm_set_mac_reg(dm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel);
 176
 177         } else {
 178                 adc_smp->is_bb_trigger = 1;
 179                 odm_set_mac_reg(dm, 0x7c0, BIT(1),
 180                                 1); /*polling bit for BB ADC mode*/
 181
 182                 if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
 183                         odm_set_mac_reg(
 184                                 dm, 0x7c0, BIT(3),
 185                                 1); /*polling bit for MAC trigger event*/
 186                         odm_set_mac_reg(dm, 0x7c0, BIT(7) | BIT(6),
 187                                         adc_smp->la_trig_sig_sel);
 188
 189                         if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
 190                                 odm_set_mac_reg(
 191                                         dm, 0x7c0, BIT(5),
 192                                         1); /* manual trigger 0x7C0[5] = 0->1*/
 193                 }
 194         }
 195
 196         reg_value = odm_get_bb_reg(dm, 0x7c0, 0xff);
 197         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 198                      "4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value);
 199 }
 200
 201 static void phydm_la_mode_set_dma_type(void *dm_void, u8 la_dma_type)
 202 {
 203         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 204
 205         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 206                      "2. [LA mode DMA setting] Dma_type = ((%d))\n",
 207                      la_dma_type);
 208
 209         if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
 210                 odm_set_bb_reg(dm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/
 211         else
 212                 odm_set_bb_reg(dm, odm_adc_trigger_jaguar2, 0xf00,
 213                                la_dma_type); /*0x95C[11:8]*/
 214 }
 215
 216 static void phydm_adc_smp_start(void *dm_void)
 217 {
 218         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 219         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 220         u8 tmp_u1b;
 221         u8 while_cnt = 0;
 222         u8 polling_ok = false, target_polling_bit;
 223
 224         phydm_la_mode_bb_setting(dm);
 225         phydm_la_mode_set_dma_type(dm, adc_smp->la_dma_type);
 226         phydm_la_mode_set_trigger_time(dm, adc_smp->la_trigger_time);
 227
 228         if (dm->support_ic_type & ODM_RTL8197F) {
 229                 odm_set_bb_reg(dm, 0xd00, BIT(26), 0x1);
 230         } else { /*for 8814A and 8822B?*/
 231                 odm_write_1byte(dm, 0x198c, 0x7);
 232                 odm_write_1byte(dm, 0x8b4, 0x80);
 233                 /* odm_set_bb_reg(dm, 0x8b4, BIT(7), 1); */
 234         }
 235
 236         phydm_la_mode_set_mac_iq_dump(dm);
 237         /* return; */
 238
 239         target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2);
 240         do { /*Poll time always use 100ms, when it exceed 2s, break while loop*/
 241                 tmp_u1b = odm_read_1byte(dm, 0x7c0);
 242
 243                 if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) {
 244                         ODM_RT_TRACE(
 245                                 dm, ODM_COMP_UNCOND,
 246                                 "[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
 247                         break;
 248
 249                 } else if (tmp_u1b & target_polling_bit) {
 250                         ODM_delay_ms(100);
 251                         while_cnt = while_cnt + 1;
 252                         continue;
 253                 } else {
 254                         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 255                                      "[LA Query OK] polling_bit=((0x%x))\n",
 256                                      target_polling_bit);
 257                         polling_ok = true;
 258                         if (dm->support_ic_type & ODM_RTL8197F)
 259                                 odm_set_bb_reg(dm, 0x7c0, BIT(0), 0x0);
 260                         break;
 261                 }
 262         } while (while_cnt < 20);
 263
 264         if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) {
 265                 if (polling_ok)
 266                         phydm_la_get_tx_pkt_buf(dm);
 267                 else
 268                         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 269                                      "[Polling timeout]\n");
 270         }
 271
 272         if (adc_smp->adc_smp_state == ADCSMP_STATE_SET)
 273                 adc_smp->adc_smp_state = ADCSMP_STATE_QUERY;
 274
 275         ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 276                      "[LA mode] LA_pattern_count = ((%d))\n",
 277                      adc_smp->la_count);
 278
 279         adc_smp_stop(dm);
 280
 281         if (adc_smp->la_count == 0) {
 282                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 283                              "LA Dump finished ---------->\n\n\n");
 284                 /**/
 285         } else {
 286                 adc_smp->la_count--;
 287                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 288                              "LA Dump more ---------->\n\n\n");
 289                 adc_smp_set(dm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel,
 290                             adc_smp->la_dma_type, adc_smp->la_trigger_time, 0);
 291         }
 292 }
 293
 294 void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
 295                  u8 dma_data_sig_sel, u32 trigger_time, u16 polling_time)
 296 {
 297         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 298         bool is_set_success = true;
 299         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 300
 301         adc_smp->la_trig_mode = trig_mode;
 302         adc_smp->la_trig_sig_sel = trig_sig_sel;
 303         adc_smp->la_dma_type = dma_data_sig_sel;
 304         adc_smp->la_trigger_time = trigger_time;
 305
 306         if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE)
 307                 is_set_success = false;
 308         else if (adc_smp->adc_smp_buf.length == 0)
 309                 is_set_success = phydm_la_buffer_allocate(dm);
 310
 311         if (is_set_success) {
 312                 adc_smp->adc_smp_state = ADCSMP_STATE_SET;
 313
 314                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 315                              "[LA Set Success] LA_State=((%d))\n",
 316                              adc_smp->adc_smp_state);
 317
 318                 phydm_adc_smp_start(dm);
 319         } else {
 320                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 321                              "[LA Set Fail] LA_State=((%d))\n",
 322                              adc_smp->adc_smp_state);
 323         }
 324 }
 325
 326 void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
 327 {
 328         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 329         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 330         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
 331         u32 used = *pused;
 332         u32 i;
 333
 334         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "%s adc_smp_state %d", __func__,
 335                      adc_smp->adc_smp_state);
 336
 337         for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) {
 338                 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
 339                                adc_smp_buf->octet[i],
 340                                adc_smp_buf->octet[i + 1]);
 341         }
 342
 343         PHYDM_SNPRINTF(output + used, out_len - used, "\n");
 344         *pused = used;
 345 }
 346
 347 s32 adc_smp_get_sample_counts(void *dm_void)
 348 {
 349         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 350         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 351         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
 352
 353         return (adc_smp_buf->length >> 2) - 2;
 354 }
 355
 356 s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len,
 357                               u32 index)
 358 {
 359         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 360         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 361         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
 362         u32 used = 0;
 363
 364         if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) {
 365                 PHYDM_SNPRINTF(output + used, out_len - used,
 366                                "Error: la data is not ready yet ...\n");
 367                 return -1;
 368         }
 369
 370         if (index < ((adc_smp_buf->length >> 2) - 2)) {
 371                 PHYDM_SNPRINTF(output + used, out_len - used, "%08x%08x\n",
 372                                adc_smp_buf->octet[index],
 373                                adc_smp_buf->octet[index + 1]);
 374         }
 375         return 0;
 376 }
 377
 378 void adc_smp_stop(void *dm_void)
 379 {
 380         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 381         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 382
 383         adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
 384         ODM_RT_TRACE(dm, ODM_COMP_UNCOND, "[LA_Stop] LA_state = ((%d))\n",
 385                      adc_smp->adc_smp_state);
 386 }
 387
 388 void adc_smp_init(void *dm_void)
 389 {
 390         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 391         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 392         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
 393
 394         adc_smp->adc_smp_state = ADCSMP_STATE_IDLE;
 395
 396         if (dm->support_ic_type & ODM_RTL8814A) {
 397                 adc_smp_buf->start_pos = 0x30000;
 398                 adc_smp_buf->buffer_size = 0x10000;
 399         } else if (dm->support_ic_type & ODM_RTL8822B) {
 400                 adc_smp_buf->start_pos = 0x20000;
 401                 adc_smp_buf->buffer_size = 0x20000;
 402         } else if (dm->support_ic_type & ODM_RTL8197F) {
 403                 adc_smp_buf->start_pos = 0x00000;
 404                 adc_smp_buf->buffer_size = 0x10000;
 405         } else if (dm->support_ic_type & ODM_RTL8821C) {
 406                 adc_smp_buf->start_pos = 0x8000;
 407                 adc_smp_buf->buffer_size = 0x8000;
 408         }
 409 }
 410
 411 void adc_smp_de_init(void *dm_void)
 412 {
 413         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 414         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 415         struct rt_adcsmp_string *adc_smp_buf = &adc_smp->adc_smp_buf;
 416
 417         adc_smp_stop(dm);
 418
 419         if (adc_smp_buf->length != 0x0) {
 420                 odm_free_memory(dm, adc_smp_buf->octet, adc_smp_buf->length);
 421                 adc_smp_buf->length = 0x0;
 422         }
 423 }
 424
 425 void phydm_la_mode_bb_setting(void *dm_void)
 426 {
 427         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 428         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 429
 430         u8 trig_mode = adc_smp->la_trig_mode;
 431         u32 trig_sig_sel = adc_smp->la_trig_sig_sel;
 432         u32 dbg_port = adc_smp->la_dbg_port;
 433         u8 is_trigger_edge = adc_smp->la_trigger_edge;
 434         u8 sampling_rate = adc_smp->la_smp_rate;
 435
 436         ODM_RT_TRACE(
 437                 dm, ODM_COMP_UNCOND,
 438                 "1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n",
 439                 trig_mode, dbg_port, is_trigger_edge, sampling_rate,
 440                 trig_sig_sel);
 441
 442         if (trig_mode == PHYDM_MAC_TRIG)
 443                 trig_sig_sel = 0; /*ignore this setting*/
 444
 445         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 446                 if (trig_mode == PHYDM_ADC_RF0_TRIG) {
 447                         /*DBGOUT_RFC_a[31:0]*/
 448                         odm_set_bb_reg(dm, 0x8f8,
 449                                        BIT(25) | BIT(24) | BIT(23) | BIT(22),
 450                                        9);
 451                 } else if (trig_mode == PHYDM_ADC_RF1_TRIG) {
 452                         /*DBGOUT_RFC_b[31:0]*/
 453                         odm_set_bb_reg(dm, 0x8f8,
 454                                        BIT(25) | BIT(24) | BIT(23) | BIT(22),
 455                                        8);
 456                 } else {
 457                         odm_set_bb_reg(dm, 0x8f8,
 458                                        BIT(25) | BIT(24) | BIT(23) | BIT(22),
 459                                        0);
 460                 }
 461                 /*
 462                  *      (0:) '{ofdm_dbg[31:0]}'
 463                  *      (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}'
 464                  *      (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}'
 465                  *      (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}'
 466                  *      (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}'
 467                  *      (5:) '{dbg_iqk_anta}'
 468                  *      (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}'
 469                  *      (7:) '{dbg_iqk_antb}'
 470                  *      (8:) '{DBGOUT_RFC_b[31:0]}'
 471                  *      (9:) '{DBGOUT_RFC_a[31:0]}'
 472                  *      (a:) '{dbg_ofdm}'
 473                  *      (b:) '{dbg_cck}'
 474                  */
 475
 476                 /*disable dbg clk gating*/
 477                 odm_set_bb_reg(dm, 0x198C, BIT(2) | BIT(1) | BIT(0), 7);
 478
 479                 /*0x95C[4:0], BB debug port bit*/
 480                 odm_set_bb_reg(dm, 0x95C, 0x1f, trig_sig_sel);
 481                 odm_set_bb_reg(dm, 0x8FC, MASKDWORD, dbg_port);
 482                 /*0: posedge, 1: negedge*/
 483                 odm_set_bb_reg(dm, 0x95C, BIT(31), is_trigger_edge);
 484                 odm_set_bb_reg(dm, 0x95c, 0xe0, sampling_rate);
 485                 /*      (0:) '80MHz'
 486                  *      (1:) '40MHz'
 487                  *      (2:) '20MHz'
 488                  *      (3:) '10MHz'
 489                  *      (4:) '5MHz'
 490                  *      (5:) '2.5MHz'
 491                  *      (6:) '1.25MHz'
 492                  *      (7:) '160MHz (for BW160 ic)'
 493                  */
 494         } else {
 495                 /*0x9A0[4:0], BB debug port bit*/
 496                 odm_set_bb_reg(dm, 0x9a0, 0x1f, trig_sig_sel);
 497                 odm_set_bb_reg(dm, 0x908, MASKDWORD, dbg_port);
 498                 /*0: posedge, 1: negedge*/
 499                 odm_set_bb_reg(dm, 0x9A0, BIT(31), is_trigger_edge);
 500                 odm_set_bb_reg(dm, 0x9A0, 0xe0, sampling_rate);
 501                 /*      (0:) '80MHz'
 502                  *      (1:) '40MHz'
 503                  *      (2:) '20MHz'
 504                  *      (3:) '10MHz'
 505                  *      (4:) '5MHz'
 506                  *      (5:) '2.5MHz'
 507                  *      (6:) '1.25MHz'
 508                  *      (7:) '160MHz (for BW160 ic)'
 509                  */
 510         }
 511 }
 512
 513 void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
 514 {
 515         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 516         u8 trigger_time_unit_num;
 517         u32 time_unit = 0;
 518
 519         if (trigger_time_mu_sec < 128)
 520                 time_unit = 0; /*unit: 1mu sec*/
 521         else if (trigger_time_mu_sec < 256)
 522                 time_unit = 1; /*unit: 2mu sec*/
 523         else if (trigger_time_mu_sec < 512)
 524                 time_unit = 2; /*unit: 4mu sec*/
 525         else if (trigger_time_mu_sec < 1024)
 526                 time_unit = 3; /*unit: 8mu sec*/
 527         else if (trigger_time_mu_sec < 2048)
 528                 time_unit = 4; /*unit: 16mu sec*/
 529         else if (trigger_time_mu_sec < 4096)
 530                 time_unit = 5; /*unit: 32mu sec*/
 531         else if (trigger_time_mu_sec < 8192)
 532                 time_unit = 6; /*unit: 64mu sec*/
 533
 534         trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit);
 535
 536         ODM_RT_TRACE(
 537                 dm, ODM_COMP_UNCOND,
 538                 "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
 539                 trigger_time_unit_num, time_unit);
 540
 541         odm_set_mac_reg(dm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit);
 542         odm_set_mac_reg(dm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f));
 543 }
 544
 545 void phydm_lamode_trigger_setting(void *dm_void, char input[][16], u32 *_used,
 546                                   char *output, u32 *_out_len, u32 input_num)
 547 {
 548         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 549         struct rt_adcsmp *adc_smp = &dm->adcsmp;
 550         u8 trig_mode, dma_data_sig_sel;
 551         u32 trig_sig_sel;
 552         bool is_enable_la_mode;
 553         u32 trigger_time_mu_sec;
 554         char help[] = "-h";
 555         u32 var1[10] = {0};
 556         u32 used = *_used;
 557         u32 out_len = *_out_len;
 558
 559         if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
 560                 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
 561                 is_enable_la_mode = (bool)var1[0];
 562                 /*dbg_print("echo cmd input_num = %d\n", input_num);*/
 563
 564                 if ((strcmp(input[1], help) == 0)) {
 565                         PHYDM_SNPRINTF(
 566                                 output + used, out_len - used,
 567                                 "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC}\n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime}\n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
 568                         /**/
 569                 } else if ((is_enable_la_mode == 1)) {
 570                         PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
 571
 572                         trig_mode = (u8)var1[1];
 573
 574                         if (trig_mode == PHYDM_MAC_TRIG)
 575                                 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
 576                         else
 577                                 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
 578                         trig_sig_sel = var1[2];
 579
 580                         PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
 581                         PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
 582                         PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
 583                         PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
 584                         PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
 585                         PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
 586                         PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
 587
 588                         dma_data_sig_sel = (u8)var1[3];
 589                         trigger_time_mu_sec = var1[4]; /*unit: us*/
 590
 591                         adc_smp->la_mac_ref_mask = var1[5];
 592                         adc_smp->la_dbg_port = var1[6];
 593                         adc_smp->la_trigger_edge = (u8)var1[7];
 594                         adc_smp->la_smp_rate = (u8)(var1[8] & 0x7);
 595                         adc_smp->la_count = var1[9];
 596
 597                         ODM_RT_TRACE(
 598                                 dm, ODM_COMP_UNCOND,
 599                                 "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
 600                                 var1[0], var1[1], var1[2], var1[3], var1[4],
 601                                 var1[5], var1[6], var1[7], var1[8], var1[9]);
 602
 603                         PHYDM_SNPRINTF(
 604                                 output + used, out_len - used,
 605                                 "a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
 606                                 trig_mode, trig_sig_sel, dma_data_sig_sel);
 607                         PHYDM_SNPRINTF(
 608                                 output + used, out_len - used,
 609                                 "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
 610                                 trigger_time_mu_sec, adc_smp->la_mac_ref_mask,
 611                                 adc_smp->la_dbg_port);
 612                         PHYDM_SNPRINTF(
 613                                 output + used, out_len - used,
 614                                 "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
 615                                 adc_smp->la_trigger_edge,
 616                                 (80 >> adc_smp->la_smp_rate),
 617                                 adc_smp->la_count);
 618
 619                         adc_smp_set(dm, trig_mode, trig_sig_sel,
 620                                     dma_data_sig_sel, trigger_time_mu_sec, 0);
 621
 622                 } else {
 623                         adc_smp_stop(dm);
 624                         PHYDM_SNPRINTF(output + used, out_len - used,
 625                                        "Disable LA mode\n");
 626                 }
 627         }
 628 }