drivers/staging/rtlwifi/phydm/phydm.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 #ifndef __HALDMOUTSRC_H__
  16 #define __HALDMOUTSRC_H__
  17
  18 /*============================================================*/
  19 /*include files*/
  20 /*============================================================*/
  21 #include "phydm_pre_define.h"
  22 #include "phydm_dig.h"
  23 #include "phydm_edcaturbocheck.h"
  24 #include "phydm_antdiv.h"
  25 #include "phydm_dynamicbbpowersaving.h"
  26 #include "phydm_rainfo.h"
  27 #include "phydm_dynamictxpower.h"
  28 #include "phydm_cfotracking.h"
  29 #include "phydm_acs.h"
  30 #include "phydm_adaptivity.h"
  31 #include "phydm_iqk.h"
  32 #include "phydm_dfs.h"
  33 #include "phydm_ccx.h"
  34 #include "txbf/phydm_hal_txbf_api.h"
  35
  36 #include "phydm_adc_sampling.h"
  37 #include "phydm_dynamic_rx_path.h"
  38 #include "phydm_psd.h"
  39
  40 #include "phydm_beamforming.h"
  41
  42 #include "phydm_noisemonitor.h"
  43 #include "halphyrf_ce.h"
  44
  45 /*============================================================*/
  46 /*Definition */
  47 /*============================================================*/
  48
  49 /* Traffic load decision */
  50 #define TRAFFIC_ULTRA_LOW 1
  51 #define TRAFFIC_LOW 2
  52 #define TRAFFIC_MID 3
  53 #define TRAFFIC_HIGH 4
  54
  55 #define NONE 0
  56
  57 /*NBI API------------------------------------*/
  58 #define NBI_ENABLE 1
  59 #define NBI_DISABLE 2
  60
  61 #define NBI_TABLE_SIZE_128 27
  62 #define NBI_TABLE_SIZE_256 59
  63
  64 #define NUM_START_CH_80M 7
  65 #define NUM_START_CH_40M 14
  66
  67 #define CH_OFFSET_40M 2
  68 #define CH_OFFSET_80M 6
  69
  70 /*CSI MASK API------------------------------------*/
  71 #define CSI_MASK_ENABLE 1
  72 #define CSI_MASK_DISABLE 2
  73
  74 /*------------------------------------------------*/
  75
  76 #define FFT_128_TYPE 1
  77 #define FFT_256_TYPE 2
  78
  79 #define SET_SUCCESS 1
  80 #define SET_ERROR 2
  81 #define SET_NO_NEED 3
  82
  83 #define FREQ_POSITIVE 1
  84 #define FREQ_NEGATIVE 2
  85
  86 #define PHYDM_WATCH_DOG_PERIOD 2
  87
  88 /*============================================================*/
  89 /*structure and define*/
  90 /*============================================================*/
  91
  92 /*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
  93 /*We need to remove to other position???*/
  94
  95 struct rtl8192cd_priv {
  96         u8 temp;
  97 };
  98
  99 struct dyn_primary_cca {
 100         u8 pri_cca_flag;
 101         u8 intf_flag;
 102         u8 intf_type;
 103         u8 dup_rts_flag;
 104         u8 monitor_flag;
 105         u8 ch_offset;
 106         u8 mf_state;
 107 };
 108
 109 #define dm_type_by_fw 0
 110 #define dm_type_by_driver 1
 111
 112 /*Declare for common info*/
 113
 114 #define IQK_THRESHOLD 8
 115 #define DPK_THRESHOLD 4
 116
 117 struct dm_phy_status_info {
 118         /*  */
 119         /* Be care, if you want to add any element please insert between */
 120         /* rx_pwdb_all & signal_strength. */
 121         /*  */
 122         u8 rx_pwdb_all;
 123         u8 signal_quality; /* in 0-100 index. */
 124         s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
 125         u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
 126         u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
 127         s16 cfo_short[4]; /* per-path's cfo_short */
 128         s16 cfo_tail[4]; /* per-path's cfo_tail */
 129         s8 rx_power; /* in dBm Translate from PWdB */
 130         s8 recv_signal_power; /* Real power in dBm for this packet,
 131                                * no beautification and aggregation.
 132                                * Keep this raw info to be used for the other
 133                                * procedures.
 134                                */
 135         u8 bt_rx_rssi_percentage;
 136         u8 signal_strength; /* in 0-100 index. */
 137         s8 rx_pwr[4]; /* per-path's pwdb */
 138         s8 rx_snr[4]; /* per-path's SNR */
 139         /* s8      BB_Backup[13];                   backup reg. */
 140         u8 rx_count : 2; /* RX path counter---*/
 141         u8 band_width : 2;
 142         u8 rxsc : 4; /* sub-channel---*/
 143         u8 bt_coex_pwr_adjust;
 144         u8 channel; /* channel number---*/
 145         bool is_mu_packet; /* is MU packet or not---*/
 146         bool is_beamformed; /* BF packet---*/
 147 };
 148
 149 struct dm_per_pkt_info {
 150         u8 data_rate;
 151         u8 station_id;
 152         bool is_packet_match_bssid;
 153         bool is_packet_to_self;
 154         bool is_packet_beacon;
 155         bool is_to_self;
 156         u8 ppdu_cnt;
 157 };
 158
 159 struct odm_phy_dbg_info {
 160         /*ODM Write,debug info*/
 161         s8 rx_snr_db[4];
 162         u32 num_qry_phy_status;
 163         u32 num_qry_phy_status_cck;
 164         u32 num_qry_phy_status_ofdm;
 165         u32 num_qry_mu_pkt;
 166         u32 num_qry_bf_pkt;
 167         u32 num_qry_mu_vht_pkt[40];
 168         u32 num_qry_vht_pkt[40];
 169         bool is_ldpc_pkt;
 170         bool is_stbc_pkt;
 171         u8 num_of_ppdu[4];
 172         u8 gid_num[4];
 173         u8 num_qry_beacon_pkt;
 174         /* Others */
 175         s32 rx_evm[4];
 176 };
 177
 178 /*2011/20/20 MH For MP driver RT_WLAN_STA =  struct rtl_sta_info*/
 179 /*Please declare below ODM relative info in your STA info structure.*/
 180
 181 struct odm_sta_info {
 182         /*Driver Write*/
 183         bool is_used; /*record the sta status link or not?*/
 184         u8 iot_peer; /*Enum value.      HT_IOT_PEER_E*/
 185
 186         /*ODM Write*/
 187         /*PHY_STATUS_INFO*/
 188         u8 rssi_path[4];
 189         u8 rssi_ave;
 190         u8 RXEVM[4];
 191         u8 RXSNR[4];
 192 };
 193
 194 enum odm_cmninfo {
 195         /*Fixed value*/
 196         /*-----------HOOK BEFORE REG INIT-----------*/
 197         ODM_CMNINFO_PLATFORM = 0,
 198         ODM_CMNINFO_ABILITY,
 199         ODM_CMNINFO_INTERFACE,
 200         ODM_CMNINFO_MP_TEST_CHIP,
 201         ODM_CMNINFO_IC_TYPE,
 202         ODM_CMNINFO_CUT_VER,
 203         ODM_CMNINFO_FAB_VER,
 204         ODM_CMNINFO_RF_TYPE,
 205         ODM_CMNINFO_RFE_TYPE,
 206         ODM_CMNINFO_BOARD_TYPE,
 207         ODM_CMNINFO_PACKAGE_TYPE,
 208         ODM_CMNINFO_EXT_LNA,
 209         ODM_CMNINFO_5G_EXT_LNA,
 210         ODM_CMNINFO_EXT_PA,
 211         ODM_CMNINFO_5G_EXT_PA,
 212         ODM_CMNINFO_GPA,
 213         ODM_CMNINFO_APA,
 214         ODM_CMNINFO_GLNA,
 215         ODM_CMNINFO_ALNA,
 216         ODM_CMNINFO_EXT_TRSW,
 217         ODM_CMNINFO_DPK_EN,
 218         ODM_CMNINFO_EXT_LNA_GAIN,
 219         ODM_CMNINFO_PATCH_ID,
 220         ODM_CMNINFO_BINHCT_TEST,
 221         ODM_CMNINFO_BWIFI_TEST,
 222         ODM_CMNINFO_SMART_CONCURRENT,
 223         ODM_CMNINFO_CONFIG_BB_RF,
 224         ODM_CMNINFO_DOMAIN_CODE_2G,
 225         ODM_CMNINFO_DOMAIN_CODE_5G,
 226         ODM_CMNINFO_IQKFWOFFLOAD,
 227         ODM_CMNINFO_IQKPAOFF,
 228         ODM_CMNINFO_HUBUSBMODE,
 229         ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
 230         ODM_CMNINFO_TX_TP,
 231         ODM_CMNINFO_RX_TP,
 232         ODM_CMNINFO_SOUNDING_SEQ,
 233         ODM_CMNINFO_REGRFKFREEENABLE,
 234         ODM_CMNINFO_RFKFREEENABLE,
 235         ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
 236         ODM_CMNINFO_EFUSE0X3D8,
 237         ODM_CMNINFO_EFUSE0X3D7,
 238         /*-----------HOOK BEFORE REG INIT-----------*/
 239
 240         /*Dynamic value:*/
 241
 242         /*--------- POINTER REFERENCE-----------*/
 243         ODM_CMNINFO_MAC_PHY_MODE,
 244         ODM_CMNINFO_TX_UNI,
 245         ODM_CMNINFO_RX_UNI,
 246         ODM_CMNINFO_WM_MODE,
 247         ODM_CMNINFO_BAND,
 248         ODM_CMNINFO_SEC_CHNL_OFFSET,
 249         ODM_CMNINFO_SEC_MODE,
 250         ODM_CMNINFO_BW,
 251         ODM_CMNINFO_CHNL,
 252         ODM_CMNINFO_FORCED_RATE,
 253         ODM_CMNINFO_ANT_DIV,
 254         ODM_CMNINFO_ADAPTIVITY,
 255         ODM_CMNINFO_DMSP_GET_VALUE,
 256         ODM_CMNINFO_BUDDY_ADAPTOR,
 257         ODM_CMNINFO_DMSP_IS_MASTER,
 258         ODM_CMNINFO_SCAN,
 259         ODM_CMNINFO_POWER_SAVING,
 260         ODM_CMNINFO_ONE_PATH_CCA,
 261         ODM_CMNINFO_DRV_STOP,
 262         ODM_CMNINFO_PNP_IN,
 263         ODM_CMNINFO_INIT_ON,
 264         ODM_CMNINFO_ANT_TEST,
 265         ODM_CMNINFO_NET_CLOSED,
 266         ODM_CMNINFO_FORCED_IGI_LB,
 267         ODM_CMNINFO_P2P_LINK,
 268         ODM_CMNINFO_FCS_MODE,
 269         ODM_CMNINFO_IS1ANTENNA,
 270         ODM_CMNINFO_RFDEFAULTPATH,
 271         ODM_CMNINFO_DFS_MASTER_ENABLE,
 272         ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
 273         ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
 274         /*--------- POINTER REFERENCE-----------*/
 275
 276         /*------------CALL BY VALUE-------------*/
 277         ODM_CMNINFO_WIFI_DIRECT,
 278         ODM_CMNINFO_WIFI_DISPLAY,
 279         ODM_CMNINFO_LINK_IN_PROGRESS,
 280         ODM_CMNINFO_LINK,
 281         ODM_CMNINFO_CMW500LINK,
 282         ODM_CMNINFO_LPSPG,
 283         ODM_CMNINFO_STATION_STATE,
 284         ODM_CMNINFO_RSSI_MIN,
 285         ODM_CMNINFO_DBG_COMP,
 286         ODM_CMNINFO_DBG_LEVEL,
 287         ODM_CMNINFO_RA_THRESHOLD_HIGH,
 288         ODM_CMNINFO_RA_THRESHOLD_LOW,
 289         ODM_CMNINFO_RF_ANTENNA_TYPE,
 290         ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
 291         ODM_CMNINFO_BE_FIX_TX_ANT,
 292         ODM_CMNINFO_BT_ENABLED,
 293         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
 294         ODM_CMNINFO_BT_HS_RSSI,
 295         ODM_CMNINFO_BT_OPERATION,
 296         ODM_CMNINFO_BT_LIMITED_DIG,
 297         ODM_CMNINFO_BT_DIG,
 298         ODM_CMNINFO_BT_BUSY,
 299         ODM_CMNINFO_BT_DISABLE_EDCA,
 300         ODM_CMNINFO_AP_TOTAL_NUM,
 301         ODM_CMNINFO_POWER_TRAINING,
 302         ODM_CMNINFO_DFS_REGION_DOMAIN,
 303         /*------------CALL BY VALUE-------------*/
 304
 305         /*Dynamic ptr array hook itms.*/
 306         ODM_CMNINFO_STA_STATUS,
 307         ODM_CMNINFO_MAX,
 308
 309 };
 310
 311 enum phydm_info_query {
 312         PHYDM_INFO_FA_OFDM,
 313         PHYDM_INFO_FA_CCK,
 314         PHYDM_INFO_FA_TOTAL,
 315         PHYDM_INFO_CCA_OFDM,
 316         PHYDM_INFO_CCA_CCK,
 317         PHYDM_INFO_CCA_ALL,
 318         PHYDM_INFO_CRC32_OK_VHT,
 319         PHYDM_INFO_CRC32_OK_HT,
 320         PHYDM_INFO_CRC32_OK_LEGACY,
 321         PHYDM_INFO_CRC32_OK_CCK,
 322         PHYDM_INFO_CRC32_ERROR_VHT,
 323         PHYDM_INFO_CRC32_ERROR_HT,
 324         PHYDM_INFO_CRC32_ERROR_LEGACY,
 325         PHYDM_INFO_CRC32_ERROR_CCK,
 326         PHYDM_INFO_EDCCA_FLAG,
 327         PHYDM_INFO_OFDM_ENABLE,
 328         PHYDM_INFO_CCK_ENABLE,
 329         PHYDM_INFO_DBG_PORT_0
 330 };
 331
 332 enum phydm_api {
 333         PHYDM_API_NBI = 1,
 334         PHYDM_API_CSI_MASK,
 335
 336 };
 337
 338 /*2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY*/
 339 enum odm_ability {
 340         /*BB ODM section BIT 0-19*/
 341         ODM_BB_DIG = BIT(0),
 342         ODM_BB_RA_MASK = BIT(1),
 343         ODM_BB_DYNAMIC_TXPWR = BIT(2),
 344         ODM_BB_FA_CNT = BIT(3),
 345         ODM_BB_RSSI_MONITOR = BIT(4),
 346         ODM_BB_CCK_PD = BIT(5),
 347         ODM_BB_ANT_DIV = BIT(6),
 348         ODM_BB_PWR_TRAIN = BIT(8),
 349         ODM_BB_RATE_ADAPTIVE = BIT(9),
 350         ODM_BB_PATH_DIV = BIT(10),
 351         ODM_BB_ADAPTIVITY = BIT(13),
 352         ODM_BB_CFO_TRACKING = BIT(14),
 353         ODM_BB_NHM_CNT = BIT(15),
 354         ODM_BB_PRIMARY_CCA = BIT(16),
 355         ODM_BB_TXBF = BIT(17),
 356         ODM_BB_DYNAMIC_ARFR = BIT(18),
 357
 358         ODM_MAC_EDCA_TURBO = BIT(20),
 359         ODM_BB_DYNAMIC_RX_PATH = BIT(21),
 360
 361         /*RF ODM section BIT 24-31*/
 362         ODM_RF_TX_PWR_TRACK = BIT(24),
 363         ODM_RF_RX_GAIN_TRACK = BIT(25),
 364         ODM_RF_CALIBRATION = BIT(26),
 365
 366 };
 367
 368 /*ODM_CMNINFO_ONE_PATH_CCA*/
 369 enum odm_cca_path {
 370         ODM_CCA_2R = 0,
 371         ODM_CCA_1R_A = 1,
 372         ODM_CCA_1R_B = 2,
 373 };
 374
 375 enum cca_pathdiv_en {
 376         CCA_PATHDIV_DISABLE = 0,
 377         CCA_PATHDIV_ENABLE = 1,
 378
 379 };
 380
 381 enum phy_reg_pg_type {
 382         PHY_REG_PG_RELATIVE_VALUE = 0,
 383         PHY_REG_PG_EXACT_VALUE = 1
 384 };
 385
 386 /*2011/09/22 MH Copy from SD4 defined structure.
 387  *We use to support PHY DM integration.
 388  */
 389
 390 struct phy_dm_struct {
 391         /*Add for different team use temporarily*/
 392         void *adapter; /*For CE/NIC team*/
 393         struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
 394         /*When you use adapter or priv pointer,
 395          *you must make sure the pointer is ready.
 396          */
 397         bool odm_ready;
 398
 399         struct rtl8192cd_priv fake_priv;
 400
 401         enum phy_reg_pg_type phy_reg_pg_value_type;
 402         u8 phy_reg_pg_version;
 403
 404         u32 debug_components;
 405         u32 fw_debug_components;
 406         u32 debug_level;
 407
 408         u32 num_qry_phy_status_all; /*CCK + OFDM*/
 409         u32 last_num_qry_phy_status_all;
 410         u32 rx_pwdb_ave;
 411         bool MPDIG_2G; /*off MPDIG*/
 412         u8 times_2g;
 413         bool is_init_hw_info_by_rfe;
 414
 415         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 416         bool is_cck_high_power;
 417         u8 rf_path_rx_enable;
 418         u8 control_channel;
 419         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 420
 421         /* 1  COMMON INFORMATION */
 422
 423         /*Init value*/
 424         /*-----------HOOK BEFORE REG INIT-----------*/
 425         /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
 426         u8 support_platform;
 427         /* ODM Platform info WIN/AP/CE = 1/2/3 */
 428         u8 normal_rx_path;
 429         /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ... = 1/2/3/...*/
 430         u32 support_ability;
 431         /*ODM PCIE/USB/SDIO = 1/2/3*/
 432         u8 support_interface;
 433         /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or
 434          *any other type = 1/2/3/...
 435          */
 436         u32 support_ic_type;
 437         /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
 438         u8 cut_version;
 439         /*Fab version TSMC/UMC = 0/1*/
 440         u8 fab_version;
 441         /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
 442         u8 rf_type;
 443         u8 rfe_type;
 444         /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
 445         /*Enable Function DPK OFF/ON = 0/1*/
 446         u8 dpk_en;
 447         u8 board_type;
 448         u8 package_type;
 449         u16 type_glna;
 450         u16 type_gpa;
 451         u16 type_alna;
 452         u16 type_apa;
 453         /*with external LNA  NO/Yes = 0/1*/
 454         u8 ext_lna; /*2G*/
 455         u8 ext_lna_5g; /*5G*/
 456         /*with external PA  NO/Yes = 0/1*/
 457         u8 ext_pa; /*2G*/
 458         u8 ext_pa_5g; /*5G*/
 459         /*with Efuse number*/
 460         u8 efuse0x3d7;
 461         u8 efuse0x3d8;
 462         /*with external TRSW  NO/Yes = 0/1*/
 463         u8 ext_trsw;
 464         u8 ext_lna_gain; /*2G*/
 465         u8 patch_id; /*Customer ID*/
 466         bool is_in_hct_test;
 467         u8 wifi_test;
 468
 469         bool is_dual_mac_smart_concurrent;
 470         u32 bk_support_ability;
 471         u8 ant_div_type;
 472         u8 with_extenal_ant_switch;
 473         bool config_bbrf;
 474         u8 odm_regulation_2_4g;
 475         u8 odm_regulation_5g;
 476         u8 iqk_fw_offload;
 477         bool cck_new_agc;
 478         u8 phydm_period;
 479         u32 phydm_sys_up_time;
 480         u8 num_rf_path;
 481         /*-----------HOOK BEFORE REG INIT-----------*/
 482
 483         /*Dynamic value*/
 484
 485         /*--------- POINTER REFERENCE-----------*/
 486
 487         u8 u1_byte_temp;
 488         bool BOOLEAN_temp;
 489         void *PADAPTER_temp;
 490
 491         /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
 492         u8 *mac_phy_mode;
 493         /*TX Unicast byte count*/
 494         u64 *num_tx_bytes_unicast;
 495         /*RX Unicast byte count*/
 496         u64 *num_rx_bytes_unicast;
 497         /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
 498         u8 *wireless_mode;
 499         /*Frequence band 2.4G/5G = 0/1*/
 500         u8 *band_type;
 501         /*Secondary channel offset don't_care/below/above = 0/1/2*/
 502         u8 *sec_ch_offset;
 503         /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
 504         u8 *security;
 505         /*BW info 20M/40M/80M = 0/1/2*/
 506         u8 *band_width;
 507         /*Central channel location Ch1/Ch2/....*/
 508         u8 *channel; /*central channel number*/
 509         bool dpk_done;
 510         /*Common info for 92D DMSP*/
 511
 512         bool *is_get_value_from_other_mac;
 513         void **buddy_adapter;
 514         bool *is_master_of_dmsp; /* MAC0: master, MAC1: slave */
 515         /*Common info for status*/
 516         bool *is_scan_in_process;
 517         bool *is_power_saving;
 518         /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
 519         u8 *one_path_cca;
 520         u8 *antenna_test;
 521         bool *is_net_closed;
 522         u8 *pu1_forced_igi_lb;
 523         bool *is_fcs_mode_enable;
 524         /*--------- For 8723B IQK-----------*/
 525         bool *is_1_antenna;
 526         u8 *rf_default_path;
 527         /* 0:S1, 1:S0 */
 528
 529         /*--------- POINTER REFERENCE-----------*/
 530         u16 *forced_data_rate;
 531         u8 *enable_antdiv;
 532         u8 *enable_adaptivity;
 533         u8 *hub_usb_mode;
 534         bool *is_fw_dw_rsvd_page_in_progress;
 535         u32 *current_tx_tp;
 536         u32 *current_rx_tp;
 537         u8 *sounding_seq;
 538         /*------------CALL BY VALUE-------------*/
 539         bool is_link_in_process;
 540         bool is_wifi_direct;
 541         bool is_wifi_display;
 542         bool is_linked;
 543         bool is_linkedcmw500;
 544         bool is_in_lps_pg;
 545         bool bsta_state;
 546         u8 rssi_min;
 547         u8 interface_index; /*Add for 92D  dual MAC: 0--Mac0 1--Mac1*/
 548         bool is_mp_chip;
 549         bool is_one_entry_only;
 550         bool mp_mode;
 551         u32 one_entry_macid;
 552         u8 pre_number_linked_client;
 553         u8 number_linked_client;
 554         u8 pre_number_active_client;
 555         u8 number_active_client;
 556         /*Common info for BTDM*/
 557         bool is_bt_enabled; /*BT is enabled*/
 558         bool is_bt_connect_process; /*BT HS is under connection progress.*/
 559         u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
 560         bool is_bt_hs_operation; /*BT HS mode is under progress*/
 561         u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
 562         bool is_bt_disable_edca_turbo; /*Under some condition, don't enable*/
 563         bool is_bt_busy; /*BT is busy.*/
 564         bool is_bt_limited_dig; /*BT is busy.*/
 565         bool is_disable_phy_api;
 566         /*------------CALL BY VALUE-------------*/
 567         u8 rssi_a;
 568         u8 rssi_b;
 569         u8 rssi_c;
 570         u8 rssi_d;
 571         u64 rssi_trsw;
 572         u64 rssi_trsw_h;
 573         u64 rssi_trsw_l;
 574         u64 rssi_trsw_iso;
 575         u8 tx_ant_status;
 576         u8 rx_ant_status;
 577         u8 cck_lna_idx;
 578         u8 cck_vga_idx;
 579         u8 curr_station_id;
 580         u8 ofdm_agc_idx[4];
 581
 582         u8 rx_rate;
 583         bool is_noisy_state;
 584         u8 tx_rate;
 585         u8 linked_interval;
 586         u8 pre_channel;
 587         u32 txagc_offset_value_a;
 588         bool is_txagc_offset_positive_a;
 589         u32 txagc_offset_value_b;
 590         bool is_txagc_offset_positive_b;
 591         u32 tx_tp;
 592         u32 rx_tp;
 593         u32 total_tp;
 594         u64 cur_tx_ok_cnt;
 595         u64 cur_rx_ok_cnt;
 596         u64 last_tx_ok_cnt;
 597         u64 last_rx_ok_cnt;
 598         u32 bb_swing_offset_a;
 599         bool is_bb_swing_offset_positive_a;
 600         u32 bb_swing_offset_b;
 601         bool is_bb_swing_offset_positive_b;
 602         u8 igi_lower_bound;
 603         u8 igi_upper_bound;
 604         u8 antdiv_rssi;
 605         u8 fat_comb_a;
 606         u8 fat_comb_b;
 607         u8 antdiv_intvl;
 608         u8 ant_type;
 609         u8 pre_ant_type;
 610         u8 antdiv_period;
 611         u8 evm_antdiv_period;
 612         u8 antdiv_select;
 613         u8 path_select;
 614         u8 antdiv_evm_en;
 615         u8 bdc_holdstate;
 616         u8 ndpa_period;
 617         bool h2c_rarpt_connect;
 618         bool cck_agc_report_type;
 619
 620         u8 dm_dig_max_TH;
 621         u8 dm_dig_min_TH;
 622         u8 print_agc;
 623         u8 traffic_load;
 624         u8 pre_traffic_load;
 625         /*8821C Antenna BTG/WLG/WLA Select*/
 626         u8 current_rf_set_8821c;
 627         u8 default_rf_set_8821c;
 628         /*For Adaptivtiy*/
 629         u16 nhm_cnt_0;
 630         u16 nhm_cnt_1;
 631         s8 TH_L2H_default;
 632         s8 th_edcca_hl_diff_default;
 633         s8 th_l2h_ini;
 634         s8 th_edcca_hl_diff;
 635         s8 th_l2h_ini_mode2;
 636         s8 th_edcca_hl_diff_mode2;
 637         bool carrier_sense_enable;
 638         u8 adaptivity_igi_upper;
 639         bool adaptivity_flag;
 640         u8 dc_backoff;
 641         bool adaptivity_enable;
 642         u8 ap_total_num;
 643         bool edcca_enable;
 644         u8 pre_dbg_priority;
 645         struct adaptivity_statistics adaptivity;
 646         /*For Adaptivtiy*/
 647         u8 last_usb_hub;
 648         u8 tx_bf_data_rate;
 649
 650         u8 nbi_set_result;
 651
 652         u8 c2h_cmd_start;
 653         u8 fw_debug_trace[60];
 654         u8 pre_c2h_seq;
 655         bool fw_buff_is_enpty;
 656         u32 data_frame_num;
 657
 658         /*for noise detection*/
 659         bool noisy_decision; /*b_noisy*/
 660         bool pre_b_noisy;
 661         u32 noisy_decision_smooth;
 662         bool is_disable_dym_ecs;
 663
 664         struct odm_noise_monitor noise_level;
 665         /*Define STA info.*/
 666         /*odm_sta_info*/
 667         /*2012/01/12 MH For MP,
 668          *we need to reduce one array pointer for default port.??
 669          */
 670         struct rtl_sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
 671         u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
 672         /* platform_macid_table[platform_macid] = phydm_macid */
 673         s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
 674
 675         /*2012/02/14 MH Add to share 88E ra with other SW team.*/
 676         /*We need to colelct all support abilit to a proper area.*/
 677
 678         bool ra_support88e;
 679
 680         struct odm_phy_dbg_info phy_dbg_info;
 681
 682         /*ODM Structure*/
 683         struct fast_antenna_training dm_fat_table;
 684         struct dig_thres dm_dig_table;
 685         struct dyn_pwr_saving dm_ps_table;
 686         struct dyn_primary_cca dm_pri_cca;
 687         struct ra_table dm_ra_table;
 688         struct false_alarm_stat false_alm_cnt;
 689         struct false_alarm_stat flase_alm_cnt_buddy_adapter;
 690         struct sw_antenna_switch dm_swat_table;
 691         struct cfo_tracking dm_cfo_track;
 692         struct acs_info dm_acs;
 693         struct ccx_info dm_ccx_info;
 694         struct psd_info dm_psd_table;
 695
 696         struct rt_adcsmp adcsmp;
 697
 698         struct dm_iqk_info IQK_info;
 699
 700         struct edca_turbo dm_edca_table;
 701         u32 WMMEDCA_BE;
 702
 703         bool *is_driver_stopped;
 704         bool *is_driver_is_going_to_pnp_set_power_sleep;
 705         bool *pinit_adpt_in_progress;
 706
 707         /*PSD*/
 708         bool is_user_assign_level;
 709         u8 RSSI_BT; /*come from BT*/
 710         bool is_psd_in_process;
 711         bool is_psd_active;
 712         bool is_dm_initial_gain_enable;
 713
 714         /*MPT DIG*/
 715         struct timer_list mpt_dig_timer;
 716
 717         /*for rate adaptive, in fact,  88c/92c fw will handle this*/
 718         u8 is_use_ra_mask;
 719
 720         /* for dynamic SoML control */
 721         bool bsomlenabled;
 722
 723         struct odm_rate_adaptive rate_adaptive;
 724         struct dm_rf_calibration_struct rf_calibrate_info;
 725         u32 n_iqk_cnt;
 726         u32 n_iqk_ok_cnt;
 727         u32 n_iqk_fail_cnt;
 728
 729         /*Power Training*/
 730         u8 force_power_training_state;
 731         bool is_change_state;
 732         u32 PT_score;
 733         u64 ofdm_rx_cnt;
 734         u64 cck_rx_cnt;
 735         bool is_disable_power_training;
 736         u8 dynamic_tx_high_power_lvl;
 737         u8 last_dtp_lvl;
 738         u32 tx_agc_ofdm_18_6;
 739         u8 rx_pkt_type;
 740
 741         /*ODM relative time.*/
 742         struct timer_list path_div_switch_timer;
 743         /*2011.09.27 add for path Diversity*/
 744         struct timer_list cck_path_diversity_timer;
 745         struct timer_list fast_ant_training_timer;
 746         struct timer_list sbdcnt_timer;
 747
 748         /*ODM relative workitem.*/
 749 };
 750
 751 enum phydm_structure_type {
 752         PHYDM_FALSEALMCNT,
 753         PHYDM_CFOTRACK,
 754         PHYDM_ADAPTIVITY,
 755         PHYDM_ROMINFO,
 756
 757 };
 758
 759 enum odm_rf_content {
 760         odm_radioa_txt = 0x1000,
 761         odm_radiob_txt = 0x1001,
 762         odm_radioc_txt = 0x1002,
 763         odm_radiod_txt = 0x1003
 764 };
 765
 766 enum odm_bb_config_type {
 767         CONFIG_BB_PHY_REG,
 768         CONFIG_BB_AGC_TAB,
 769         CONFIG_BB_AGC_TAB_2G,
 770         CONFIG_BB_AGC_TAB_5G,
 771         CONFIG_BB_PHY_REG_PG,
 772         CONFIG_BB_PHY_REG_MP,
 773         CONFIG_BB_AGC_TAB_DIFF,
 774 };
 775
 776 enum odm_rf_config_type {
 777         CONFIG_RF_RADIO,
 778         CONFIG_RF_TXPWR_LMT,
 779 };
 780
 781 enum odm_fw_config_type {
 782         CONFIG_FW_NIC,
 783         CONFIG_FW_NIC_2,
 784         CONFIG_FW_AP,
 785         CONFIG_FW_AP_2,
 786         CONFIG_FW_MP,
 787         CONFIG_FW_WOWLAN,
 788         CONFIG_FW_WOWLAN_2,
 789         CONFIG_FW_AP_WOWLAN,
 790         CONFIG_FW_BT,
 791 };
 792
 793 /*status code*/
 794 enum rt_status {
 795         RT_STATUS_SUCCESS,
 796         RT_STATUS_FAILURE,
 797         RT_STATUS_PENDING,
 798         RT_STATUS_RESOURCE,
 799         RT_STATUS_INVALID_CONTEXT,
 800         RT_STATUS_INVALID_PARAMETER,
 801         RT_STATUS_NOT_SUPPORT,
 802         RT_STATUS_OS_API_FAILED,
 803 };
 804
 805 /*===========================================================*/
 806 /*AGC RX High Power mode*/
 807 /*===========================================================*/
 808 #define lna_low_gain_1 0x64
 809 #define lna_low_gain_2 0x5A
 810 #define lna_low_gain_3 0x58
 811
 812 #define FA_RXHP_TH1 5000
 813 #define FA_RXHP_TH2 1500
 814 #define FA_RXHP_TH3 800
 815 #define FA_RXHP_TH4 600
 816 #define FA_RXHP_TH5 500
 817
 818 enum dm_1r_cca {
 819         CCA_1R = 0,
 820         CCA_2R = 1,
 821         CCA_MAX = 2,
 822 };
 823
 824 enum dm_rf {
 825         rf_save = 0,
 826         rf_normal = 1,
 827         RF_MAX = 2,
 828 };
 829
 830 /*check Sta pointer valid or not*/
 831
 832 #define IS_STA_VALID(sta) (sta)
 833
 834 u32 odm_convert_to_db(u32 value);
 835
 836 u32 odm_convert_to_linear(u32 value);
 837
 838 s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
 839
 840 s32 odm_sign_conversion(s32 value, u32 total_bit);
 841
 842 void odm_init_mp_driver_status(struct phy_dm_struct *dm);
 843
 844 void phydm_txcurrentcalibration(struct phy_dm_struct *dm);
 845
 846 void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
 847                        u8 seq_length);
 848
 849 void odm_dm_init(struct phy_dm_struct *dm);
 850
 851 void odm_dm_reset(struct phy_dm_struct *dm);
 852
 853 void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
 854                                  char *output, u32 *_out_len);
 855
 856 void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path);
 857
 858 void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
 859                            char *output, u32 *_out_len);
 860
 861 void odm_dm_watchdog(struct phy_dm_struct *dm);
 862
 863 void phydm_watchdog_mp(struct phy_dm_struct *dm);
 864
 865 void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 866                        u32 value);
 867
 868 void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 869                        void *value);
 870
 871 void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
 872                                  enum odm_cmninfo cmn_info, u16 index,
 873                                  void *value);
 874
 875 void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value);
 876
 877 u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
 878                          enum phydm_info_query info_type);
 879
 880 void odm_init_all_timers(struct phy_dm_struct *dm);
 881
 882 void odm_cancel_all_timers(struct phy_dm_struct *dm);
 883
 884 void odm_release_all_timers(struct phy_dm_struct *dm);
 885
 886 void odm_asoc_entry_init(struct phy_dm_struct *dm);
 887
 888 void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type);
 889
 890 /*===========================================================*/
 891 /* The following is for compile only*/
 892 /*===========================================================*/
 893
 894 #define IS_HARDWARE_TYPE_8188E(_adapter) false
 895 #define IS_HARDWARE_TYPE_8188F(_adapter) false
 896 #define IS_HARDWARE_TYPE_8703B(_adapter) false
 897 #define IS_HARDWARE_TYPE_8723D(_adapter) false
 898 #define IS_HARDWARE_TYPE_8821C(_adapter) false
 899 #define IS_HARDWARE_TYPE_8812AU(_adapter) false
 900 #define IS_HARDWARE_TYPE_8814A(_adapter) false
 901 #define IS_HARDWARE_TYPE_8814AU(_adapter) false
 902 #define IS_HARDWARE_TYPE_8814AE(_adapter) false
 903 #define IS_HARDWARE_TYPE_8814AS(_adapter) false
 904 #define IS_HARDWARE_TYPE_8723BU(_adapter) false
 905 #define IS_HARDWARE_TYPE_8822BU(_adapter) false
 906 #define IS_HARDWARE_TYPE_8822BS(_adapter) false
 907 #define IS_HARDWARE_TYPE_JAGUAR(_adapter)                                      \
 908         (IS_HARDWARE_TYPE_8812(_adapter) || IS_HARDWARE_TYPE_8821(_adapter))
 909 #define IS_HARDWARE_TYPE_8723AE(_adapter) false
 910 #define IS_HARDWARE_TYPE_8192C(_adapter) false
 911 #define IS_HARDWARE_TYPE_8192D(_adapter) false
 912 #define RF_T_METER_92D 0x42
 913
 914 #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc)                           \
 915         LE_BITS_TO_1BYTE(__prx_status_desc + 12, 0, 6)
 916
 917 #define REG_CONFIG_RAM64X16 0xb2c
 918
 919 #define TARGET_CHNL_NUM_2G_5G 59
 920
 921 /* *********************************************************** */
 922
 923 void odm_dtc(struct phy_dm_struct *dm);
 924
 925 void phydm_noisy_detection(struct phy_dm_struct *dm);
 926
 927 void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
 928                           char *output, u32 *_out_len);
 929
 930 void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
 931                      u32 *_used, char *output, u32 *_out_len);
 932
 933 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
 934                      u32 f_interference, u32 second_ch);
 935 #endif /* __HALDMOUTSRC_H__ */