drivers/staging/rtlwifi/phydm/phydm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __HALDMOUTSRC_H__
  27 #define __HALDMOUTSRC_H__
  28
  29 /*============================================================*/
  30 /*include files*/
  31 /*============================================================*/
  32 #include "phydm_pre_define.h"
  33 #include "phydm_dig.h"
  34 #include "phydm_edcaturbocheck.h"
  35 #include "phydm_antdiv.h"
  36 #include "phydm_dynamicbbpowersaving.h"
  37 #include "phydm_rainfo.h"
  38 #include "phydm_dynamictxpower.h"
  39 #include "phydm_cfotracking.h"
  40 #include "phydm_acs.h"
  41 #include "phydm_adaptivity.h"
  42 #include "phydm_iqk.h"
  43 #include "phydm_dfs.h"
  44 #include "phydm_ccx.h"
  45 #include "txbf/phydm_hal_txbf_api.h"
  46
  47 #include "phydm_adc_sampling.h"
  48 #include "phydm_dynamic_rx_path.h"
  49 #include "phydm_psd.h"
  50
  51 #include "phydm_beamforming.h"
  52
  53 #include "phydm_noisemonitor.h"
  54 #include "halphyrf_ce.h"
  55
  56 /*============================================================*/
  57 /*Definition */
  58 /*============================================================*/
  59
  60 /* Traffic load decision */
  61 #define TRAFFIC_ULTRA_LOW 1
  62 #define TRAFFIC_LOW 2
  63 #define TRAFFIC_MID 3
  64 #define TRAFFIC_HIGH 4
  65
  66 #define NONE 0
  67
  68 /*NBI API------------------------------------*/
  69 #define NBI_ENABLE 1
  70 #define NBI_DISABLE 2
  71
  72 #define NBI_TABLE_SIZE_128 27
  73 #define NBI_TABLE_SIZE_256 59
  74
  75 #define NUM_START_CH_80M 7
  76 #define NUM_START_CH_40M 14
  77
  78 #define CH_OFFSET_40M 2
  79 #define CH_OFFSET_80M 6
  80
  81 /*CSI MASK API------------------------------------*/
  82 #define CSI_MASK_ENABLE 1
  83 #define CSI_MASK_DISABLE 2
  84
  85 /*------------------------------------------------*/
  86
  87 #define FFT_128_TYPE 1
  88 #define FFT_256_TYPE 2
  89
  90 #define SET_SUCCESS 1
  91 #define SET_ERROR 2
  92 #define SET_NO_NEED 3
  93
  94 #define FREQ_POSITIVE 1
  95 #define FREQ_NEGATIVE 2
  96
  97 #define PHYDM_WATCH_DOG_PERIOD 2
  98
  99 /*============================================================*/
 100 /*structure and define*/
 101 /*============================================================*/
 102
 103 /*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/
 104 /*We need to remove to other position???*/
 105
 106 struct rtl8192cd_priv {
 107         u8 temp;
 108 };
 109
 110 struct dyn_primary_cca {
 111         u8 pri_cca_flag;
 112         u8 intf_flag;
 113         u8 intf_type;
 114         u8 dup_rts_flag;
 115         u8 monitor_flag;
 116         u8 ch_offset;
 117         u8 mf_state;
 118 };
 119
 120 #define dm_type_by_fw 0
 121 #define dm_type_by_driver 1
 122
 123 /*Declare for common info*/
 124
 125 #define IQK_THRESHOLD 8
 126 #define DPK_THRESHOLD 4
 127
 128 struct dm_phy_status_info {
 129         /*  */
 130         /* Be care, if you want to add any element please insert between */
 131         /* rx_pwdb_all & signal_strength. */
 132         /*  */
 133         u8 rx_pwdb_all;
 134         u8 signal_quality; /* in 0-100 index. */
 135         s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */
 136         u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */
 137         u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
 138         s16 cfo_short[4]; /* per-path's cfo_short */
 139         s16 cfo_tail[4]; /* per-path's cfo_tail */
 140         s8 rx_power; /* in dBm Translate from PWdB */
 141         s8 recv_signal_power; /* Real power in dBm for this packet,
 142                                * no beautification and aggregation.
 143                                * Keep this raw info to be used for the other
 144                                * procedures.
 145                                */
 146         u8 bt_rx_rssi_percentage;
 147         u8 signal_strength; /* in 0-100 index. */
 148         s8 rx_pwr[4]; /* per-path's pwdb */
 149         s8 rx_snr[4]; /* per-path's SNR */
 150         /* s8      BB_Backup[13];                   backup reg. */
 151         u8 rx_count : 2; /* RX path counter---*/
 152         u8 band_width : 2;
 153         u8 rxsc : 4; /* sub-channel---*/
 154         u8 bt_coex_pwr_adjust;
 155         u8 channel; /* channel number---*/
 156         bool is_mu_packet; /* is MU packet or not---*/
 157         bool is_beamformed; /* BF packet---*/
 158 };
 159
 160 struct dm_per_pkt_info {
 161         u8 data_rate;
 162         u8 station_id;
 163         bool is_packet_match_bssid;
 164         bool is_packet_to_self;
 165         bool is_packet_beacon;
 166         bool is_to_self;
 167         u8 ppdu_cnt;
 168 };
 169
 170 struct odm_phy_dbg_info {
 171         /*ODM Write,debug info*/
 172         s8 rx_snr_db[4];
 173         u32 num_qry_phy_status;
 174         u32 num_qry_phy_status_cck;
 175         u32 num_qry_phy_status_ofdm;
 176         u32 num_qry_mu_pkt;
 177         u32 num_qry_bf_pkt;
 178         u32 num_qry_mu_vht_pkt[40];
 179         u32 num_qry_vht_pkt[40];
 180         bool is_ldpc_pkt;
 181         bool is_stbc_pkt;
 182         u8 num_of_ppdu[4];
 183         u8 gid_num[4];
 184         u8 num_qry_beacon_pkt;
 185         /* Others */
 186         s32 rx_evm[4];
 187 };
 188
 189 /*2011/20/20 MH For MP driver RT_WLAN_STA =  struct rtl_sta_info*/
 190 /*Please declare below ODM relative info in your STA info structure.*/
 191
 192 struct odm_sta_info {
 193         /*Driver Write*/
 194         bool is_used; /*record the sta status link or not?*/
 195         u8 iot_peer; /*Enum value.      HT_IOT_PEER_E*/
 196
 197         /*ODM Write*/
 198         /*PHY_STATUS_INFO*/
 199         u8 rssi_path[4];
 200         u8 rssi_ave;
 201         u8 RXEVM[4];
 202         u8 RXSNR[4];
 203 };
 204
 205 enum odm_cmninfo {
 206         /*Fixed value*/
 207         /*-----------HOOK BEFORE REG INIT-----------*/
 208         ODM_CMNINFO_PLATFORM = 0,
 209         ODM_CMNINFO_ABILITY,
 210         ODM_CMNINFO_INTERFACE,
 211         ODM_CMNINFO_MP_TEST_CHIP,
 212         ODM_CMNINFO_IC_TYPE,
 213         ODM_CMNINFO_CUT_VER,
 214         ODM_CMNINFO_FAB_VER,
 215         ODM_CMNINFO_RF_TYPE,
 216         ODM_CMNINFO_RFE_TYPE,
 217         ODM_CMNINFO_BOARD_TYPE,
 218         ODM_CMNINFO_PACKAGE_TYPE,
 219         ODM_CMNINFO_EXT_LNA,
 220         ODM_CMNINFO_5G_EXT_LNA,
 221         ODM_CMNINFO_EXT_PA,
 222         ODM_CMNINFO_5G_EXT_PA,
 223         ODM_CMNINFO_GPA,
 224         ODM_CMNINFO_APA,
 225         ODM_CMNINFO_GLNA,
 226         ODM_CMNINFO_ALNA,
 227         ODM_CMNINFO_EXT_TRSW,
 228         ODM_CMNINFO_DPK_EN,
 229         ODM_CMNINFO_EXT_LNA_GAIN,
 230         ODM_CMNINFO_PATCH_ID,
 231         ODM_CMNINFO_BINHCT_TEST,
 232         ODM_CMNINFO_BWIFI_TEST,
 233         ODM_CMNINFO_SMART_CONCURRENT,
 234         ODM_CMNINFO_CONFIG_BB_RF,
 235         ODM_CMNINFO_DOMAIN_CODE_2G,
 236         ODM_CMNINFO_DOMAIN_CODE_5G,
 237         ODM_CMNINFO_IQKFWOFFLOAD,
 238         ODM_CMNINFO_IQKPAOFF,
 239         ODM_CMNINFO_HUBUSBMODE,
 240         ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS,
 241         ODM_CMNINFO_TX_TP,
 242         ODM_CMNINFO_RX_TP,
 243         ODM_CMNINFO_SOUNDING_SEQ,
 244         ODM_CMNINFO_REGRFKFREEENABLE,
 245         ODM_CMNINFO_RFKFREEENABLE,
 246         ODM_CMNINFO_NORMAL_RX_PATH_CHANGE,
 247         ODM_CMNINFO_EFUSE0X3D8,
 248         ODM_CMNINFO_EFUSE0X3D7,
 249         /*-----------HOOK BEFORE REG INIT-----------*/
 250
 251         /*Dynamic value:*/
 252
 253         /*--------- POINTER REFERENCE-----------*/
 254         ODM_CMNINFO_MAC_PHY_MODE,
 255         ODM_CMNINFO_TX_UNI,
 256         ODM_CMNINFO_RX_UNI,
 257         ODM_CMNINFO_WM_MODE,
 258         ODM_CMNINFO_BAND,
 259         ODM_CMNINFO_SEC_CHNL_OFFSET,
 260         ODM_CMNINFO_SEC_MODE,
 261         ODM_CMNINFO_BW,
 262         ODM_CMNINFO_CHNL,
 263         ODM_CMNINFO_FORCED_RATE,
 264         ODM_CMNINFO_ANT_DIV,
 265         ODM_CMNINFO_ADAPTIVITY,
 266         ODM_CMNINFO_DMSP_GET_VALUE,
 267         ODM_CMNINFO_BUDDY_ADAPTOR,
 268         ODM_CMNINFO_DMSP_IS_MASTER,
 269         ODM_CMNINFO_SCAN,
 270         ODM_CMNINFO_POWER_SAVING,
 271         ODM_CMNINFO_ONE_PATH_CCA,
 272         ODM_CMNINFO_DRV_STOP,
 273         ODM_CMNINFO_PNP_IN,
 274         ODM_CMNINFO_INIT_ON,
 275         ODM_CMNINFO_ANT_TEST,
 276         ODM_CMNINFO_NET_CLOSED,
 277         ODM_CMNINFO_FORCED_IGI_LB,
 278         ODM_CMNINFO_P2P_LINK,
 279         ODM_CMNINFO_FCS_MODE,
 280         ODM_CMNINFO_IS1ANTENNA,
 281         ODM_CMNINFO_RFDEFAULTPATH,
 282         ODM_CMNINFO_DFS_MASTER_ENABLE,
 283         ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC,
 284         ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA,
 285         /*--------- POINTER REFERENCE-----------*/
 286
 287         /*------------CALL BY VALUE-------------*/
 288         ODM_CMNINFO_WIFI_DIRECT,
 289         ODM_CMNINFO_WIFI_DISPLAY,
 290         ODM_CMNINFO_LINK_IN_PROGRESS,
 291         ODM_CMNINFO_LINK,
 292         ODM_CMNINFO_CMW500LINK,
 293         ODM_CMNINFO_LPSPG,
 294         ODM_CMNINFO_STATION_STATE,
 295         ODM_CMNINFO_RSSI_MIN,
 296         ODM_CMNINFO_DBG_COMP,
 297         ODM_CMNINFO_DBG_LEVEL,
 298         ODM_CMNINFO_RA_THRESHOLD_HIGH,
 299         ODM_CMNINFO_RA_THRESHOLD_LOW,
 300         ODM_CMNINFO_RF_ANTENNA_TYPE,
 301         ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH,
 302         ODM_CMNINFO_BE_FIX_TX_ANT,
 303         ODM_CMNINFO_BT_ENABLED,
 304         ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
 305         ODM_CMNINFO_BT_HS_RSSI,
 306         ODM_CMNINFO_BT_OPERATION,
 307         ODM_CMNINFO_BT_LIMITED_DIG,
 308         ODM_CMNINFO_BT_DIG,
 309         ODM_CMNINFO_BT_BUSY,
 310         ODM_CMNINFO_BT_DISABLE_EDCA,
 311         ODM_CMNINFO_AP_TOTAL_NUM,
 312         ODM_CMNINFO_POWER_TRAINING,
 313         ODM_CMNINFO_DFS_REGION_DOMAIN,
 314         /*------------CALL BY VALUE-------------*/
 315
 316         /*Dynamic ptr array hook itms.*/
 317         ODM_CMNINFO_STA_STATUS,
 318         ODM_CMNINFO_MAX,
 319
 320 };
 321
 322 enum phydm_info_query {
 323         PHYDM_INFO_FA_OFDM,
 324         PHYDM_INFO_FA_CCK,
 325         PHYDM_INFO_FA_TOTAL,
 326         PHYDM_INFO_CCA_OFDM,
 327         PHYDM_INFO_CCA_CCK,
 328         PHYDM_INFO_CCA_ALL,
 329         PHYDM_INFO_CRC32_OK_VHT,
 330         PHYDM_INFO_CRC32_OK_HT,
 331         PHYDM_INFO_CRC32_OK_LEGACY,
 332         PHYDM_INFO_CRC32_OK_CCK,
 333         PHYDM_INFO_CRC32_ERROR_VHT,
 334         PHYDM_INFO_CRC32_ERROR_HT,
 335         PHYDM_INFO_CRC32_ERROR_LEGACY,
 336         PHYDM_INFO_CRC32_ERROR_CCK,
 337         PHYDM_INFO_EDCCA_FLAG,
 338         PHYDM_INFO_OFDM_ENABLE,
 339         PHYDM_INFO_CCK_ENABLE,
 340         PHYDM_INFO_DBG_PORT_0
 341 };
 342
 343 enum phydm_api {
 344         PHYDM_API_NBI = 1,
 345         PHYDM_API_CSI_MASK,
 346
 347 };
 348
 349 /*2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY*/
 350 enum odm_ability {
 351         /*BB ODM section BIT 0-19*/
 352         ODM_BB_DIG = BIT(0),
 353         ODM_BB_RA_MASK = BIT(1),
 354         ODM_BB_DYNAMIC_TXPWR = BIT(2),
 355         ODM_BB_FA_CNT = BIT(3),
 356         ODM_BB_RSSI_MONITOR = BIT(4),
 357         ODM_BB_CCK_PD = BIT(5),
 358         ODM_BB_ANT_DIV = BIT(6),
 359         ODM_BB_PWR_TRAIN = BIT(8),
 360         ODM_BB_RATE_ADAPTIVE = BIT(9),
 361         ODM_BB_PATH_DIV = BIT(10),
 362         ODM_BB_ADAPTIVITY = BIT(13),
 363         ODM_BB_CFO_TRACKING = BIT(14),
 364         ODM_BB_NHM_CNT = BIT(15),
 365         ODM_BB_PRIMARY_CCA = BIT(16),
 366         ODM_BB_TXBF = BIT(17),
 367         ODM_BB_DYNAMIC_ARFR = BIT(18),
 368
 369         ODM_MAC_EDCA_TURBO = BIT(20),
 370         ODM_BB_DYNAMIC_RX_PATH = BIT(21),
 371
 372         /*RF ODM section BIT 24-31*/
 373         ODM_RF_TX_PWR_TRACK = BIT(24),
 374         ODM_RF_RX_GAIN_TRACK = BIT(25),
 375         ODM_RF_CALIBRATION = BIT(26),
 376
 377 };
 378
 379 /*ODM_CMNINFO_ONE_PATH_CCA*/
 380 enum odm_cca_path {
 381         ODM_CCA_2R = 0,
 382         ODM_CCA_1R_A = 1,
 383         ODM_CCA_1R_B = 2,
 384 };
 385
 386 enum cca_pathdiv_en {
 387         CCA_PATHDIV_DISABLE = 0,
 388         CCA_PATHDIV_ENABLE = 1,
 389
 390 };
 391
 392 enum phy_reg_pg_type {
 393         PHY_REG_PG_RELATIVE_VALUE = 0,
 394         PHY_REG_PG_EXACT_VALUE = 1
 395 };
 396
 397 /*2011/09/22 MH Copy from SD4 defined structure.
 398  *We use to support PHY DM integration.
 399  */
 400
 401 struct phy_dm_struct {
 402         /*Add for different team use temporarily*/
 403         void *adapter; /*For CE/NIC team*/
 404         struct rtl8192cd_priv *priv; /*For AP/ADSL team*/
 405         /*When you use adapter or priv pointer,
 406          *you must make sure the pointer is ready.
 407          */
 408         bool odm_ready;
 409
 410         struct rtl8192cd_priv fake_priv;
 411
 412         enum phy_reg_pg_type phy_reg_pg_value_type;
 413         u8 phy_reg_pg_version;
 414
 415         u32 debug_components;
 416         u32 fw_debug_components;
 417         u32 debug_level;
 418
 419         u32 num_qry_phy_status_all; /*CCK + OFDM*/
 420         u32 last_num_qry_phy_status_all;
 421         u32 rx_pwdb_ave;
 422         bool MPDIG_2G; /*off MPDIG*/
 423         u8 times_2g;
 424         bool is_init_hw_info_by_rfe;
 425
 426         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 427         bool is_cck_high_power;
 428         u8 rf_path_rx_enable;
 429         u8 control_channel;
 430         /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/
 431
 432         /* 1  COMMON INFORMATION */
 433
 434         /*Init value*/
 435         /*-----------HOOK BEFORE REG INIT-----------*/
 436         /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/
 437         u8 support_platform;
 438         /* ODM Platform info WIN/AP/CE = 1/2/3 */
 439         u8 normal_rx_path;
 440         /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ... = 1/2/3/...*/
 441         u32 support_ability;
 442         /*ODM PCIE/USB/SDIO = 1/2/3*/
 443         u8 support_interface;
 444         /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or
 445          *any other type = 1/2/3/...
 446          */
 447         u32 support_ic_type;
 448         /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/
 449         u8 cut_version;
 450         /*Fab version TSMC/UMC = 0/1*/
 451         u8 fab_version;
 452         /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/
 453         u8 rf_type;
 454         u8 rfe_type;
 455         /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/
 456         /*Enable Function DPK OFF/ON = 0/1*/
 457         u8 dpk_en;
 458         u8 board_type;
 459         u8 package_type;
 460         u16 type_glna;
 461         u16 type_gpa;
 462         u16 type_alna;
 463         u16 type_apa;
 464         /*with external LNA  NO/Yes = 0/1*/
 465         u8 ext_lna; /*2G*/
 466         u8 ext_lna_5g; /*5G*/
 467         /*with external PA  NO/Yes = 0/1*/
 468         u8 ext_pa; /*2G*/
 469         u8 ext_pa_5g; /*5G*/
 470         /*with Efuse number*/
 471         u8 efuse0x3d7;
 472         u8 efuse0x3d8;
 473         /*with external TRSW  NO/Yes = 0/1*/
 474         u8 ext_trsw;
 475         u8 ext_lna_gain; /*2G*/
 476         u8 patch_id; /*Customer ID*/
 477         bool is_in_hct_test;
 478         u8 wifi_test;
 479
 480         bool is_dual_mac_smart_concurrent;
 481         u32 bk_support_ability;
 482         u8 ant_div_type;
 483         u8 with_extenal_ant_switch;
 484         bool config_bbrf;
 485         u8 odm_regulation_2_4g;
 486         u8 odm_regulation_5g;
 487         u8 iqk_fw_offload;
 488         bool cck_new_agc;
 489         u8 phydm_period;
 490         u32 phydm_sys_up_time;
 491         u8 num_rf_path;
 492         /*-----------HOOK BEFORE REG INIT-----------*/
 493
 494         /*Dynamic value*/
 495
 496         /*--------- POINTER REFERENCE-----------*/
 497
 498         u8 u1_byte_temp;
 499         bool BOOLEAN_temp;
 500         void *PADAPTER_temp;
 501
 502         /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/
 503         u8 *mac_phy_mode;
 504         /*TX Unicast byte count*/
 505         u64 *num_tx_bytes_unicast;
 506         /*RX Unicast byte count*/
 507         u64 *num_rx_bytes_unicast;
 508         /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/
 509         u8 *wireless_mode;
 510         /*Frequence band 2.4G/5G = 0/1*/
 511         u8 *band_type;
 512         /*Secondary channel offset don't_care/below/above = 0/1/2*/
 513         u8 *sec_ch_offset;
 514         /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/
 515         u8 *security;
 516         /*BW info 20M/40M/80M = 0/1/2*/
 517         u8 *band_width;
 518         /*Central channel location Ch1/Ch2/....*/
 519         u8 *channel; /*central channel number*/
 520         bool dpk_done;
 521         /*Common info for 92D DMSP*/
 522
 523         bool *is_get_value_from_other_mac;
 524         void **buddy_adapter;
 525         bool *is_master_of_dmsp; /* MAC0: master, MAC1: slave */
 526         /*Common info for status*/
 527         bool *is_scan_in_process;
 528         bool *is_power_saving;
 529         /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path.*/
 530         u8 *one_path_cca;
 531         u8 *antenna_test;
 532         bool *is_net_closed;
 533         u8 *pu1_forced_igi_lb;
 534         bool *is_fcs_mode_enable;
 535         /*--------- For 8723B IQK-----------*/
 536         bool *is_1_antenna;
 537         u8 *rf_default_path;
 538         /* 0:S1, 1:S0 */
 539
 540         /*--------- POINTER REFERENCE-----------*/
 541         u16 *forced_data_rate;
 542         u8 *enable_antdiv;
 543         u8 *enable_adaptivity;
 544         u8 *hub_usb_mode;
 545         bool *is_fw_dw_rsvd_page_in_progress;
 546         u32 *current_tx_tp;
 547         u32 *current_rx_tp;
 548         u8 *sounding_seq;
 549         /*------------CALL BY VALUE-------------*/
 550         bool is_link_in_process;
 551         bool is_wifi_direct;
 552         bool is_wifi_display;
 553         bool is_linked;
 554         bool is_linkedcmw500;
 555         bool is_in_lps_pg;
 556         bool bsta_state;
 557         u8 rssi_min;
 558         u8 interface_index; /*Add for 92D  dual MAC: 0--Mac0 1--Mac1*/
 559         bool is_mp_chip;
 560         bool is_one_entry_only;
 561         bool mp_mode;
 562         u32 one_entry_macid;
 563         u8 pre_number_linked_client;
 564         u8 number_linked_client;
 565         u8 pre_number_active_client;
 566         u8 number_active_client;
 567         /*Common info for BTDM*/
 568         bool is_bt_enabled; /*BT is enabled*/
 569         bool is_bt_connect_process; /*BT HS is under connection progress.*/
 570         u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/
 571         bool is_bt_hs_operation; /*BT HS mode is under progress*/
 572         u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/
 573         bool is_bt_disable_edca_turbo; /*Under some condition, don't enable*/
 574         bool is_bt_busy; /*BT is busy.*/
 575         bool is_bt_limited_dig; /*BT is busy.*/
 576         bool is_disable_phy_api;
 577         /*------------CALL BY VALUE-------------*/
 578         u8 rssi_a;
 579         u8 rssi_b;
 580         u8 rssi_c;
 581         u8 rssi_d;
 582         u64 rssi_trsw;
 583         u64 rssi_trsw_h;
 584         u64 rssi_trsw_l;
 585         u64 rssi_trsw_iso;
 586         u8 tx_ant_status;
 587         u8 rx_ant_status;
 588         u8 cck_lna_idx;
 589         u8 cck_vga_idx;
 590         u8 curr_station_id;
 591         u8 ofdm_agc_idx[4];
 592
 593         u8 rx_rate;
 594         bool is_noisy_state;
 595         u8 tx_rate;
 596         u8 linked_interval;
 597         u8 pre_channel;
 598         u32 txagc_offset_value_a;
 599         bool is_txagc_offset_positive_a;
 600         u32 txagc_offset_value_b;
 601         bool is_txagc_offset_positive_b;
 602         u32 tx_tp;
 603         u32 rx_tp;
 604         u32 total_tp;
 605         u64 cur_tx_ok_cnt;
 606         u64 cur_rx_ok_cnt;
 607         u64 last_tx_ok_cnt;
 608         u64 last_rx_ok_cnt;
 609         u32 bb_swing_offset_a;
 610         bool is_bb_swing_offset_positive_a;
 611         u32 bb_swing_offset_b;
 612         bool is_bb_swing_offset_positive_b;
 613         u8 igi_lower_bound;
 614         u8 igi_upper_bound;
 615         u8 antdiv_rssi;
 616         u8 fat_comb_a;
 617         u8 fat_comb_b;
 618         u8 antdiv_intvl;
 619         u8 ant_type;
 620         u8 pre_ant_type;
 621         u8 antdiv_period;
 622         u8 evm_antdiv_period;
 623         u8 antdiv_select;
 624         u8 path_select;
 625         u8 antdiv_evm_en;
 626         u8 bdc_holdstate;
 627         u8 ndpa_period;
 628         bool h2c_rarpt_connect;
 629         bool cck_agc_report_type;
 630
 631         u8 dm_dig_max_TH;
 632         u8 dm_dig_min_TH;
 633         u8 print_agc;
 634         u8 traffic_load;
 635         u8 pre_traffic_load;
 636         /*8821C Antenna BTG/WLG/WLA Select*/
 637         u8 current_rf_set_8821c;
 638         u8 default_rf_set_8821c;
 639         /*For Adaptivtiy*/
 640         u16 nhm_cnt_0;
 641         u16 nhm_cnt_1;
 642         s8 TH_L2H_default;
 643         s8 th_edcca_hl_diff_default;
 644         s8 th_l2h_ini;
 645         s8 th_edcca_hl_diff;
 646         s8 th_l2h_ini_mode2;
 647         s8 th_edcca_hl_diff_mode2;
 648         bool carrier_sense_enable;
 649         u8 adaptivity_igi_upper;
 650         bool adaptivity_flag;
 651         u8 dc_backoff;
 652         bool adaptivity_enable;
 653         u8 ap_total_num;
 654         bool edcca_enable;
 655         u8 pre_dbg_priority;
 656         struct adaptivity_statistics adaptivity;
 657         /*For Adaptivtiy*/
 658         u8 last_usb_hub;
 659         u8 tx_bf_data_rate;
 660
 661         u8 nbi_set_result;
 662
 663         u8 c2h_cmd_start;
 664         u8 fw_debug_trace[60];
 665         u8 pre_c2h_seq;
 666         bool fw_buff_is_enpty;
 667         u32 data_frame_num;
 668
 669         /*for noise detection*/
 670         bool noisy_decision; /*b_noisy*/
 671         bool pre_b_noisy;
 672         u32 noisy_decision_smooth;
 673         bool is_disable_dym_ecs;
 674
 675         struct odm_noise_monitor noise_level;
 676         /*Define STA info.*/
 677         /*odm_sta_info*/
 678         /*2012/01/12 MH For MP,
 679          *we need to reduce one array pointer for default port.??
 680          */
 681         struct rtl_sta_info *odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM];
 682         u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM];
 683         /* platform_macid_table[platform_macid] = phydm_macid */
 684         s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM];
 685
 686         /*2012/02/14 MH Add to share 88E ra with other SW team.*/
 687         /*We need to colelct all support abilit to a proper area.*/
 688
 689         bool ra_support88e;
 690
 691         struct odm_phy_dbg_info phy_dbg_info;
 692
 693         /*ODM Structure*/
 694         struct fast_antenna_training dm_fat_table;
 695         struct dig_thres dm_dig_table;
 696         struct dyn_pwr_saving dm_ps_table;
 697         struct dyn_primary_cca dm_pri_cca;
 698         struct ra_table dm_ra_table;
 699         struct false_alarm_stat false_alm_cnt;
 700         struct false_alarm_stat flase_alm_cnt_buddy_adapter;
 701         struct sw_antenna_switch dm_swat_table;
 702         struct cfo_tracking dm_cfo_track;
 703         struct acs_info dm_acs;
 704         struct ccx_info dm_ccx_info;
 705         struct psd_info dm_psd_table;
 706
 707         struct rt_adcsmp adcsmp;
 708
 709         struct dm_iqk_info IQK_info;
 710
 711         struct edca_turbo dm_edca_table;
 712         u32 WMMEDCA_BE;
 713
 714         bool *is_driver_stopped;
 715         bool *is_driver_is_going_to_pnp_set_power_sleep;
 716         bool *pinit_adpt_in_progress;
 717
 718         /*PSD*/
 719         bool is_user_assign_level;
 720         u8 RSSI_BT; /*come from BT*/
 721         bool is_psd_in_process;
 722         bool is_psd_active;
 723         bool is_dm_initial_gain_enable;
 724
 725         /*MPT DIG*/
 726         struct timer_list mpt_dig_timer;
 727
 728         /*for rate adaptive, in fact,  88c/92c fw will handle this*/
 729         u8 is_use_ra_mask;
 730
 731         /* for dynamic SoML control */
 732         bool bsomlenabled;
 733
 734         struct odm_rate_adaptive rate_adaptive;
 735         struct dm_rf_calibration_struct rf_calibrate_info;
 736         u32 n_iqk_cnt;
 737         u32 n_iqk_ok_cnt;
 738         u32 n_iqk_fail_cnt;
 739
 740         /*Power Training*/
 741         u8 force_power_training_state;
 742         bool is_change_state;
 743         u32 PT_score;
 744         u64 ofdm_rx_cnt;
 745         u64 cck_rx_cnt;
 746         bool is_disable_power_training;
 747         u8 dynamic_tx_high_power_lvl;
 748         u8 last_dtp_lvl;
 749         u32 tx_agc_ofdm_18_6;
 750         u8 rx_pkt_type;
 751
 752         /*ODM relative time.*/
 753         struct timer_list path_div_switch_timer;
 754         /*2011.09.27 add for path Diversity*/
 755         struct timer_list cck_path_diversity_timer;
 756         struct timer_list fast_ant_training_timer;
 757         struct timer_list sbdcnt_timer;
 758
 759         /*ODM relative workitem.*/
 760 };
 761
 762 enum phydm_structure_type {
 763         PHYDM_FALSEALMCNT,
 764         PHYDM_CFOTRACK,
 765         PHYDM_ADAPTIVITY,
 766         PHYDM_ROMINFO,
 767
 768 };
 769
 770 enum odm_rf_content {
 771         odm_radioa_txt = 0x1000,
 772         odm_radiob_txt = 0x1001,
 773         odm_radioc_txt = 0x1002,
 774         odm_radiod_txt = 0x1003
 775 };
 776
 777 enum odm_bb_config_type {
 778         CONFIG_BB_PHY_REG,
 779         CONFIG_BB_AGC_TAB,
 780         CONFIG_BB_AGC_TAB_2G,
 781         CONFIG_BB_AGC_TAB_5G,
 782         CONFIG_BB_PHY_REG_PG,
 783         CONFIG_BB_PHY_REG_MP,
 784         CONFIG_BB_AGC_TAB_DIFF,
 785 };
 786
 787 enum odm_rf_config_type {
 788         CONFIG_RF_RADIO,
 789         CONFIG_RF_TXPWR_LMT,
 790 };
 791
 792 enum odm_fw_config_type {
 793         CONFIG_FW_NIC,
 794         CONFIG_FW_NIC_2,
 795         CONFIG_FW_AP,
 796         CONFIG_FW_AP_2,
 797         CONFIG_FW_MP,
 798         CONFIG_FW_WOWLAN,
 799         CONFIG_FW_WOWLAN_2,
 800         CONFIG_FW_AP_WOWLAN,
 801         CONFIG_FW_BT,
 802 };
 803
 804 /*status code*/
 805 enum rt_status {
 806         RT_STATUS_SUCCESS,
 807         RT_STATUS_FAILURE,
 808         RT_STATUS_PENDING,
 809         RT_STATUS_RESOURCE,
 810         RT_STATUS_INVALID_CONTEXT,
 811         RT_STATUS_INVALID_PARAMETER,
 812         RT_STATUS_NOT_SUPPORT,
 813         RT_STATUS_OS_API_FAILED,
 814 };
 815
 816 /*===========================================================*/
 817 /*AGC RX High Power mode*/
 818 /*===========================================================*/
 819 #define lna_low_gain_1 0x64
 820 #define lna_low_gain_2 0x5A
 821 #define lna_low_gain_3 0x58
 822
 823 #define FA_RXHP_TH1 5000
 824 #define FA_RXHP_TH2 1500
 825 #define FA_RXHP_TH3 800
 826 #define FA_RXHP_TH4 600
 827 #define FA_RXHP_TH5 500
 828
 829 enum dm_1r_cca {
 830         CCA_1R = 0,
 831         CCA_2R = 1,
 832         CCA_MAX = 2,
 833 };
 834
 835 enum dm_rf {
 836         rf_save = 0,
 837         rf_normal = 1,
 838         RF_MAX = 2,
 839 };
 840
 841 /*check Sta pointer valid or not*/
 842
 843 #define IS_STA_VALID(sta) (sta)
 844
 845 u32 odm_convert_to_db(u32 value);
 846
 847 u32 odm_convert_to_linear(u32 value);
 848
 849 s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit);
 850
 851 s32 odm_sign_conversion(s32 value, u32 total_bit);
 852
 853 void odm_init_mp_driver_status(struct phy_dm_struct *dm);
 854
 855 void phydm_txcurrentcalibration(struct phy_dm_struct *dm);
 856
 857 void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
 858                        u8 seq_length);
 859
 860 void odm_dm_init(struct phy_dm_struct *dm);
 861
 862 void odm_dm_reset(struct phy_dm_struct *dm);
 863
 864 void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
 865                                  char *output, u32 *_out_len);
 866
 867 void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path);
 868
 869 void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
 870                            char *output, u32 *_out_len);
 871
 872 void odm_dm_watchdog(struct phy_dm_struct *dm);
 873
 874 void phydm_watchdog_mp(struct phy_dm_struct *dm);
 875
 876 void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 877                        u32 value);
 878
 879 void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 880                        void *value);
 881
 882 void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
 883                                  enum odm_cmninfo cmn_info, u16 index,
 884                                  void *value);
 885
 886 void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value);
 887
 888 u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
 889                          enum phydm_info_query info_type);
 890
 891 void odm_init_all_timers(struct phy_dm_struct *dm);
 892
 893 void odm_cancel_all_timers(struct phy_dm_struct *dm);
 894
 895 void odm_release_all_timers(struct phy_dm_struct *dm);
 896
 897 void odm_asoc_entry_init(struct phy_dm_struct *dm);
 898
 899 void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type);
 900
 901 /*===========================================================*/
 902 /* The following is for compile only*/
 903 /*===========================================================*/
 904
 905 #define IS_HARDWARE_TYPE_8188E(_adapter) false
 906 #define IS_HARDWARE_TYPE_8188F(_adapter) false
 907 #define IS_HARDWARE_TYPE_8703B(_adapter) false
 908 #define IS_HARDWARE_TYPE_8723D(_adapter) false
 909 #define IS_HARDWARE_TYPE_8821C(_adapter) false
 910 #define IS_HARDWARE_TYPE_8812AU(_adapter) false
 911 #define IS_HARDWARE_TYPE_8814A(_adapter) false
 912 #define IS_HARDWARE_TYPE_8814AU(_adapter) false
 913 #define IS_HARDWARE_TYPE_8814AE(_adapter) false
 914 #define IS_HARDWARE_TYPE_8814AS(_adapter) false
 915 #define IS_HARDWARE_TYPE_8723BU(_adapter) false
 916 #define IS_HARDWARE_TYPE_8822BU(_adapter) false
 917 #define IS_HARDWARE_TYPE_8822BS(_adapter) false
 918 #define IS_HARDWARE_TYPE_JAGUAR(_adapter)                                      \
 919         (IS_HARDWARE_TYPE_8812(_adapter) || IS_HARDWARE_TYPE_8821(_adapter))
 920 #define IS_HARDWARE_TYPE_8723AE(_adapter) false
 921 #define IS_HARDWARE_TYPE_8192C(_adapter) false
 922 #define IS_HARDWARE_TYPE_8192D(_adapter) false
 923 #define RF_T_METER_92D 0x42
 924
 925 #define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc)                           \
 926         LE_BITS_TO_1BYTE(__prx_status_desc + 12, 0, 6)
 927
 928 #define REG_CONFIG_RAM64X16 0xb2c
 929
 930 #define TARGET_CHNL_NUM_2G_5G 59
 931
 932 /* *********************************************************** */
 933
 934 void odm_dtc(struct phy_dm_struct *dm);
 935
 936 void phydm_noisy_detection(struct phy_dm_struct *dm);
 937
 938 void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
 939                           char *output, u32 *_out_len);
 940
 941 void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
 942                      u32 *_used, char *output, u32 *_out_len);
 943
 944 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
 945                      u32 f_interference, u32 second_ch);
 946 #endif /* __HALDMOUTSRC_H__ */