drivers/staging/rtlwifi/halmac/halmac_type.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14 #ifndef _HALMAC_TYPE_H_
  15 #define _HALMAC_TYPE_H_
  16
  17 #include "halmac_2_platform.h"
  18 #include "halmac_fw_info.h"
  19 #include "halmac_intf_phy_cmd.h"
  20
  21 #define HALMAC_SCAN_CH_NUM_MAX 28
  22 #define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
  23 #define HALMAC_PHY_PARAMETER_SIZE 12
  24 #define HALMAC_PHY_PARAMETER_MAX_NUM 128
  25 #define HALMAC_MAX_SSID_LEN 32
  26 #define HALMAC_SUPPORT_NLO_NUM 16
  27 #define HALMAC_SUPPORT_PROBE_REQ_NUM 8
  28 #define HALMC_DDMA_POLLING_COUNT 1000
  29 #define API_ARRAY_SIZE 32
  30
  31 /* platform api */
  32 #define PLATFORM_SDIO_CMD52_READ                                               \
  33         halmac_adapter->halmac_platform_api->SDIO_CMD52_READ
  34 #define PLATFORM_SDIO_CMD53_READ_8                                             \
  35         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_8
  36 #define PLATFORM_SDIO_CMD53_READ_16                                            \
  37         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_16
  38 #define PLATFORM_SDIO_CMD53_READ_32                                            \
  39         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_32
  40 #define PLATFORM_SDIO_CMD53_READ_N                                             \
  41         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_N
  42 #define PLATFORM_SDIO_CMD52_WRITE                                              \
  43         halmac_adapter->halmac_platform_api->SDIO_CMD52_WRITE
  44 #define PLATFORM_SDIO_CMD53_WRITE_8                                            \
  45         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_8
  46 #define PLATFORM_SDIO_CMD53_WRITE_16                                           \
  47         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_16
  48 #define PLATFORM_SDIO_CMD53_WRITE_32                                           \
  49         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_32
  50
  51 #define PLATFORM_REG_READ_8 halmac_adapter->halmac_platform_api->REG_READ_8
  52 #define PLATFORM_REG_READ_16 halmac_adapter->halmac_platform_api->REG_READ_16
  53 #define PLATFORM_REG_READ_32 halmac_adapter->halmac_platform_api->REG_READ_32
  54 #define PLATFORM_REG_WRITE_8 halmac_adapter->halmac_platform_api->REG_WRITE_8
  55 #define PLATFORM_REG_WRITE_16 halmac_adapter->halmac_platform_api->REG_WRITE_16
  56 #define PLATFORM_REG_WRITE_32 halmac_adapter->halmac_platform_api->REG_WRITE_32
  57
  58 #define PLATFORM_SEND_RSVD_PAGE                                                \
  59         halmac_adapter->halmac_platform_api->SEND_RSVD_PAGE
  60 #define PLATFORM_SEND_H2C_PKT halmac_adapter->halmac_platform_api->SEND_H2C_PKT
  61
  62 #define PLATFORM_EVENT_INDICATION                                              \
  63         halmac_adapter->halmac_platform_api->EVENT_INDICATION
  64
  65 #define HALMAC_RT_TRACE(drv_adapter, comp, level, fmt, ...)                    \
  66         RT_TRACE(drv_adapter, COMP_HALMAC, level, fmt, ##__VA_ARGS__)
  67
  68 #define HALMAC_REG_READ_8 halmac_api->halmac_reg_read_8
  69 #define HALMAC_REG_READ_16 halmac_api->halmac_reg_read_16
  70 #define HALMAC_REG_READ_32 halmac_api->halmac_reg_read_32
  71 #define HALMAC_REG_WRITE_8 halmac_api->halmac_reg_write_8
  72 #define HALMAC_REG_WRITE_16 halmac_api->halmac_reg_write_16
  73 #define HALMAC_REG_WRITE_32 halmac_api->halmac_reg_write_32
  74 #define HALMAC_REG_SDIO_CMD53_READ_N halmac_api->halmac_reg_sdio_cmd53_read_n
  75
  76 /* Swap Little-endian <-> Big-endia*/
  77
  78 /*1->Little endian 0->Big endian*/
  79 #if HALMAC_SYSTEM_ENDIAN
  80 #else
  81 #endif
  82
  83 #define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
  84 #define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
  85
  86 /* HALMAC API return status*/
  87 enum halmac_ret_status {
  88         HALMAC_RET_SUCCESS = 0x00,
  89         HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
  90         HALMAC_RET_PLATFORM_API_NULL = 0x02,
  91         HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
  92         HALMAC_RET_MALLOC_FAIL = 0x04,
  93         HALMAC_RET_ADAPTER_INVALID = 0x05,
  94         HALMAC_RET_ITF_INCORRECT = 0x06,
  95         HALMAC_RET_DLFW_FAIL = 0x07,
  96         HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
  97         HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
  98         HALMAC_RET_INIT_LLT_FAIL = 0x0A,
  99         HALMAC_RET_POWER_STATE_INVALID = 0x0B,
 100         HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
 101         HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
 102         HALMAC_RET_EFUSE_R_FAIL = 0x0E,
 103         HALMAC_RET_EFUSE_W_FAIL = 0x0F,
 104         HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
 105         HALMAC_RET_SEND_H2C_FAIL = 0x11,
 106         HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
 107         HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
 108         HALMAC_RET_ENDIAN_ERR = 0x14,
 109         HALMAC_RET_FW_SIZE_ERR = 0x15,
 110         HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
 111         HALMAC_RET_FAIL = 0x17,
 112         HALMAC_RET_CHANGE_PS_FAIL = 0x18,
 113         HALMAC_RET_CFG_PARA_FAIL = 0x19,
 114         HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
 115         HALMAC_RET_SCAN_FAIL = 0x1B,
 116         HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
 117         HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
 118         HALMAC_RET_POWER_ON_FAIL = 0x1E,
 119         HALMAC_RET_POWER_OFF_FAIL = 0x1F,
 120         HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
 121         HALMAC_RET_DATA_BUF_NULL = 0x21,
 122         HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
 123         HALMAC_RET_QSEL_INCORRECT = 0x23,
 124         HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
 125         HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
 126         HALMAC_RET_DDMA_FAIL = 0x26,
 127         HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
 128         HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
 129         HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
 130         HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
 131         HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
 132         HALMAC_RET_NULL_POINTER = 0x2C,
 133         HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
 134         HALMAC_RET_FW_NO_MEMORY = 0x2E,
 135         HALMAC_RET_H2C_STATUS_ERR = 0x2F,
 136         HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
 137         HALMAC_RET_H2C_SPACE_FULL = 0x31,
 138         HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
 139         HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
 140         HALMAC_RET_TX_DMA_ERR = 0x34,
 141         HALMAC_RET_RX_DMA_ERR = 0x35,
 142         HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
 143         HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
 144         HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
 145         HALMAC_RET_CH_SW_NO_BUF = 0x39,
 146         HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
 147         HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
 148         HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
 149         HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
 150         HALMAC_RET_STATE_INCORRECT = 0x3E,
 151         HALMAC_RET_H2C_BUSY = 0x3F,
 152         HALMAC_RET_INVALID_FEATURE_ID = 0x40,
 153         HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
 154         HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
 155         HALMAC_RET_BUSY_STATE = 0x43,
 156         HALMAC_RET_ERROR_STATE = 0x44,
 157         HALMAC_RET_API_INVALID = 0x45,
 158         HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
 159         HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
 160         HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
 161         HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
 162         HALMAC_RET_WRONG_ARGUMENT = 0x4A,
 163         HALMAC_RET_NOT_SUPPORT = 0x4B,
 164         HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
 165         HALMAC_RET_PARA_SENDING = 0x4D,
 166         HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
 167         HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
 168         HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
 169         HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
 170         HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
 171         HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
 172         HALMAC_RET_NO_DLFW = 0x54,
 173         HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
 174         HALMAC_RET_BIP_NO_SUPPORT = 0x56,
 175         HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
 176         HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
 177         HALMAC_RET_DRV_DL_ERR = 0x59,
 178         HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
 179         HALMAC_RET_PWR_UNCHANGE = 0x5B,
 180         HALMAC_RET_FW_NO_SUPPORT = 0x60,
 181         HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
 182 };
 183
 184 enum halmac_mac_clock_hw_def {
 185         HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
 186         HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
 187         HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
 188 };
 189
 190 /* Rx aggregation parameters */
 191 enum halmac_normal_rxagg_th_to {
 192         HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
 193         HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
 194 };
 195
 196 enum halmac_loopback_rxagg_th_to {
 197         HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
 198         HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
 199 };
 200
 201 /* Chip ID*/
 202 enum halmac_chip_id {
 203         HALMAC_CHIP_ID_8822B = 0,
 204         HALMAC_CHIP_ID_8821C = 1,
 205         HALMAC_CHIP_ID_8814B = 2,
 206         HALMAC_CHIP_ID_8197F = 3,
 207         HALMAC_CHIP_ID_UNDEFINE = 0x7F,
 208 };
 209
 210 enum halmac_chip_id_hw_def {
 211         HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
 212         HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
 213         HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
 214         HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
 215         HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
 216         HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
 217         HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
 218         HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
 219         HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
 220         HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
 221         HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
 222         HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
 223         HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
 224         HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
 225         HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
 226         HALMAC_CHIP_ID_HW_DEF_8814B = 0x10,
 227         HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
 228         HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
 229 };
 230
 231 /* Chip Version*/
 232 enum halmac_chip_ver {
 233         HALMAC_CHIP_VER_A_CUT = 0x00,
 234         HALMAC_CHIP_VER_B_CUT = 0x01,
 235         HALMAC_CHIP_VER_C_CUT = 0x02,
 236         HALMAC_CHIP_VER_D_CUT = 0x03,
 237         HALMAC_CHIP_VER_E_CUT = 0x04,
 238         HALMAC_CHIP_VER_F_CUT = 0x05,
 239         HALMAC_CHIP_VER_TEST = 0xFF,
 240         HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
 241 };
 242
 243 /* Network type select */
 244 enum halmac_network_type_select {
 245         HALMAC_NETWORK_NO_LINK = 0,
 246         HALMAC_NETWORK_ADHOC = 1,
 247         HALMAC_NETWORK_INFRASTRUCTURE = 2,
 248         HALMAC_NETWORK_AP = 3,
 249         HALMAC_NETWORK_UNDEFINE = 0x7F,
 250 };
 251
 252 /* Transfer mode select */
 253 enum halmac_trnsfer_mode_select {
 254         HALMAC_TRNSFER_NORMAL = 0x0,
 255         HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
 256         HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
 257         HALMAC_TRNSFER_UNDEFINE = 0x7F,
 258 };
 259
 260 /* Queue select */
 261 enum halmac_dma_mapping {
 262         HALMAC_DMA_MAPPING_EXTRA = 0,
 263         HALMAC_DMA_MAPPING_LOW = 1,
 264         HALMAC_DMA_MAPPING_NORMAL = 2,
 265         HALMAC_DMA_MAPPING_HIGH = 3,
 266         HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
 267 };
 268
 269 #define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
 270 #define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
 271 #define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
 272 #define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
 273 #define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
 274
 275 /* TXDESC queue select TID */
 276 enum halmac_txdesc_queue_tid {
 277         HALMAC_TXDESC_QSEL_TID0 = 0,
 278         HALMAC_TXDESC_QSEL_TID1 = 1,
 279         HALMAC_TXDESC_QSEL_TID2 = 2,
 280         HALMAC_TXDESC_QSEL_TID3 = 3,
 281         HALMAC_TXDESC_QSEL_TID4 = 4,
 282         HALMAC_TXDESC_QSEL_TID5 = 5,
 283         HALMAC_TXDESC_QSEL_TID6 = 6,
 284         HALMAC_TXDESC_QSEL_TID7 = 7,
 285         HALMAC_TXDESC_QSEL_TID8 = 8,
 286         HALMAC_TXDESC_QSEL_TID9 = 9,
 287         HALMAC_TXDESC_QSEL_TIDA = 10,
 288         HALMAC_TXDESC_QSEL_TIDB = 11,
 289         HALMAC_TXDESC_QSEL_TIDC = 12,
 290         HALMAC_TXDESC_QSEL_TIDD = 13,
 291         HALMAC_TXDESC_QSEL_TIDE = 14,
 292         HALMAC_TXDESC_QSEL_TIDF = 15,
 293
 294         HALMAC_TXDESC_QSEL_BEACON = 0x10,
 295         HALMAC_TXDESC_QSEL_HIGH = 0x11,
 296         HALMAC_TXDESC_QSEL_MGT = 0x12,
 297         HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
 298
 299         HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
 300 };
 301
 302 enum halmac_ptcl_queue {
 303         HALMAC_PTCL_QUEUE_VO = 0x0,
 304         HALMAC_PTCL_QUEUE_VI = 0x1,
 305         HALMAC_PTCL_QUEUE_BE = 0x2,
 306         HALMAC_PTCL_QUEUE_BK = 0x3,
 307         HALMAC_PTCL_QUEUE_MG = 0x4,
 308         HALMAC_PTCL_QUEUE_HI = 0x5,
 309         HALMAC_PTCL_QUEUE_NUM = 0x6,
 310         HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
 311 };
 312
 313 enum halmac_queue_select {
 314         HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
 315         HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
 316         HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
 317         HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
 318         HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
 319         HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
 320         HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
 321         HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
 322         HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
 323         HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
 324         HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
 325         HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
 326         HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
 327 };
 328
 329 /* USB burst size */
 330 enum halmac_usb_burst_size {
 331         HALMAC_USB_BURST_SIZE_3_0 = 0x0,
 332         HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
 333         HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
 334         HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
 335         HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
 336 };
 337
 338 /* HAL API  function parameters*/
 339 enum halmac_interface {
 340         HALMAC_INTERFACE_PCIE = 0x0,
 341         HALMAC_INTERFACE_USB = 0x1,
 342         HALMAC_INTERFACE_SDIO = 0x2,
 343         HALMAC_INTERFACE_AXI = 0x3,
 344         HALMAC_INTERFACE_UNDEFINE = 0x7F,
 345 };
 346
 347 enum halmac_rx_agg_mode {
 348         HALMAC_RX_AGG_MODE_NONE = 0x0,
 349         HALMAC_RX_AGG_MODE_DMA = 0x1,
 350         HALMAC_RX_AGG_MODE_USB = 0x2,
 351         HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
 352 };
 353
 354 struct halmac_rxagg_th {
 355         u8 drv_define;
 356         u8 timeout;
 357         u8 size;
 358 };
 359
 360 struct halmac_rxagg_cfg {
 361         enum halmac_rx_agg_mode mode;
 362         struct halmac_rxagg_th threshold;
 363 };
 364
 365 enum halmac_mac_power {
 366         HALMAC_MAC_POWER_OFF = 0x0,
 367         HALMAC_MAC_POWER_ON = 0x1,
 368         HALMAC_MAC_POWER_UNDEFINE = 0x7F,
 369 };
 370
 371 enum halmac_ps_state {
 372         HALMAC_PS_STATE_ACT = 0x0,
 373         HALMAC_PS_STATE_LPS = 0x1,
 374         HALMAC_PS_STATE_IPS = 0x2,
 375         HALMAC_PS_STATE_UNDEFINE = 0x7F,
 376 };
 377
 378 enum halmac_trx_mode {
 379         HALMAC_TRX_MODE_NORMAL = 0x0,
 380         HALMAC_TRX_MODE_TRXSHARE = 0x1,
 381         HALMAC_TRX_MODE_WMM = 0x2,
 382         HALMAC_TRX_MODE_P2P = 0x3,
 383         HALMAC_TRX_MODE_LOOPBACK = 0x4,
 384         HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
 385         HALMAC_TRX_MODE_MAX = 0x6,
 386         HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
 387         HALMAC_TRX_MODE_UNDEFINE = 0x7F,
 388 };
 389
 390 enum halmac_wireless_mode {
 391         HALMAC_WIRELESS_MODE_B = 0x0,
 392         HALMAC_WIRELESS_MODE_G = 0x1,
 393         HALMAC_WIRELESS_MODE_N = 0x2,
 394         HALMAC_WIRELESS_MODE_AC = 0x3,
 395         HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
 396 };
 397
 398 enum halmac_bw {
 399         HALMAC_BW_20 = 0x00,
 400         HALMAC_BW_40 = 0x01,
 401         HALMAC_BW_80 = 0x02,
 402         HALMAC_BW_160 = 0x03,
 403         HALMAC_BW_5 = 0x04,
 404         HALMAC_BW_10 = 0x05,
 405         HALMAC_BW_MAX = 0x06,
 406         HALMAC_BW_UNDEFINE = 0x7F,
 407 };
 408
 409 enum halmac_efuse_read_cfg {
 410         HALMAC_EFUSE_R_AUTO = 0x00,
 411         HALMAC_EFUSE_R_DRV = 0x01,
 412         HALMAC_EFUSE_R_FW = 0x02,
 413         HALMAC_EFUSE_R_UNDEFINE = 0x7F,
 414 };
 415
 416 enum halmac_dlfw_mem {
 417         HALMAC_DLFW_MEM_EMEM = 0x00,
 418         HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
 419 };
 420
 421 struct halmac_tx_desc {
 422         u32 dword0;
 423         u32 dword1;
 424         u32 dword2;
 425         u32 dword3;
 426         u32 dword4;
 427         u32 dword5;
 428         u32 dword6;
 429         u32 dword7;
 430         u32 dword8;
 431         u32 dword9;
 432         u32 dword10;
 433         u32 dword11;
 434 };
 435
 436 struct halmac_rx_desc {
 437         u32 dword0;
 438         u32 dword1;
 439         u32 dword2;
 440         u32 dword3;
 441         u32 dword4;
 442         u32 dword5;
 443 };
 444
 445 struct halmac_fwlps_option {
 446         u8 mode;
 447         u8 clk_request;
 448         u8 rlbm;
 449         u8 smart_ps;
 450         u8 awake_interval;
 451         u8 all_queue_uapsd;
 452         u8 pwr_state;
 453         u8 low_pwr_rx_beacon;
 454         u8 ant_auto_switch;
 455         u8 ps_allow_bt_high_priority;
 456         u8 protect_bcn;
 457         u8 silence_period;
 458         u8 fast_bt_connect;
 459         u8 two_antenna_en;
 460         u8 adopt_user_setting;
 461         u8 drv_bcn_early_shift;
 462         bool enter_32K;
 463 };
 464
 465 struct halmac_fwips_option {
 466         u8 adopt_user_setting;
 467 };
 468
 469 struct halmac_wowlan_option {
 470         u8 adopt_user_setting;
 471 };
 472
 473 struct halmac_bcn_ie_info {
 474         u8 func_en;
 475         u8 size_th;
 476         u8 timeout;
 477         u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
 478 };
 479
 480 enum halmac_reg_type {
 481         HALMAC_REG_TYPE_MAC = 0x0,
 482         HALMAC_REG_TYPE_BB = 0x1,
 483         HALMAC_REG_TYPE_RF = 0x2,
 484         HALMAC_REG_TYPE_UNDEFINE = 0x7F,
 485 };
 486
 487 enum halmac_parameter_cmd {
 488         /* HALMAC_PARAMETER_CMD_LLT                             = 0x1, */
 489         /* HALMAC_PARAMETER_CMD_R_EFUSE                 = 0x2, */
 490         /* HALMAC_PARAMETER_CMD_EFUSE_PATCH     = 0x3, */
 491         HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
 492         HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
 493         HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
 494         HALMAC_PARAMETER_CMD_RF_W = 0x7,
 495         HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
 496         HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
 497         HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
 498         HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
 499         HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
 500         HALMAC_PARAMETER_CMD_END = 0XFF,
 501 };
 502
 503 union halmac_parameter_content {
 504         struct _MAC_REG_W {
 505                 u32 value;
 506                 u32 msk;
 507                 u16 offset;
 508                 u8 msk_en;
 509         } MAC_REG_W;
 510         struct _BB_REG_W {
 511                 u32 value;
 512                 u32 msk;
 513                 u16 offset;
 514                 u8 msk_en;
 515         } BB_REG_W;
 516         struct _RF_REG_W {
 517                 u32 value;
 518                 u32 msk;
 519                 u8 offset;
 520                 u8 msk_en;
 521                 u8 rf_path;
 522         } RF_REG_W;
 523         struct _DELAY_TIME {
 524                 u32 rsvd1;
 525                 u32 rsvd2;
 526                 u16 delay_time;
 527                 u8 rsvd3;
 528         } DELAY_TIME;
 529 };
 530
 531 struct halmac_phy_parameter_info {
 532         enum halmac_parameter_cmd cmd_id;
 533         union halmac_parameter_content content;
 534 };
 535
 536 struct halmac_h2c_info {
 537         u16 h2c_seq_num; /* H2C sequence number */
 538         u8 in_use; /* 0 : empty 1 : used */
 539         enum halmac_h2c_return_code status;
 540 };
 541
 542 struct halmac_pg_efuse_info {
 543         u8 *efuse_map;
 544         u32 efuse_map_size;
 545         u8 *efuse_mask;
 546         u32 efuse_mask_size;
 547 };
 548
 549 struct halmac_txagg_buff_info {
 550         u8 *tx_agg_buf;
 551         u8 *curr_pkt_buf;
 552         u32 avai_buf_size;
 553         u32 total_pkt_size;
 554         u8 agg_num;
 555 };
 556
 557 struct halmac_config_para_info {
 558         u32 para_buf_size; /* Parameter buffer size */
 559         u8 *cfg_para_buf; /* Buffer for config parameter */
 560         u8 *para_buf_w; /* Write pointer of the parameter buffer */
 561         u32 para_num; /* Parameter numbers in parameter buffer */
 562         u32 avai_para_buf_size; /* Free size of parameter buffer */
 563         u32 offset_accumulation;
 564         u32 value_accumulation;
 565         enum halmac_data_type data_type; /*DataType which is passed to FW*/
 566         u8 datapack_segment; /*DataPack Segment, from segment0...*/
 567         bool full_fifo_mode; /* Used full tx fifo to save cfg parameter */
 568 };
 569
 570 struct halmac_hw_config_info {
 571         u32 efuse_size; /* Record efuse size */
 572         u32 eeprom_size; /* Record eeprom size */
 573         u32 bt_efuse_size; /* Record BT efuse size */
 574         u32 tx_fifo_size; /* Record tx fifo size */
 575         u32 rx_fifo_size; /* Record rx fifo size */
 576         u8 txdesc_size; /* Record tx desc size */
 577         u8 rxdesc_size; /* Record rx desc size */
 578         u32 page_size; /* Record page size */
 579         u16 tx_align_size;
 580         u8 page_size_2_power;
 581         u8 cam_entry_num; /* Record CAM entry number */
 582 };
 583
 584 struct halmac_sdio_free_space {
 585         u16 high_queue_number; /* Free space of HIQ */
 586         u16 normal_queue_number; /* Free space of MIDQ */
 587         u16 low_queue_number; /* Free space of LOWQ */
 588         u16 public_queue_number; /* Free space of PUBQ */
 589         u16 extra_queue_number; /* Free space of EXBQ */
 590         u8 ac_oqt_number;
 591         u8 non_ac_oqt_number;
 592         u8 ac_empty;
 593 };
 594
 595 enum hal_fifo_sel {
 596         HAL_FIFO_SEL_TX,
 597         HAL_FIFO_SEL_RX,
 598         HAL_FIFO_SEL_RSVD_PAGE,
 599         HAL_FIFO_SEL_REPORT,
 600         HAL_FIFO_SEL_LLT,
 601 };
 602
 603 enum halmac_drv_info {
 604         HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
 605         HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
 606         HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info appended */
 607         HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended */
 608         HALMAC_DRV_INFO_UNDEFINE,
 609 };
 610
 611 struct halmac_bt_coex_cmd {
 612         u8 element_id;
 613         u8 op_code;
 614         u8 op_code_ver;
 615         u8 req_num;
 616         u8 data0;
 617         u8 data1;
 618         u8 data2;
 619         u8 data3;
 620         u8 data4;
 621 };
 622
 623 enum halmac_pri_ch_idx {
 624         HALMAC_CH_IDX_UNDEFINE = 0,
 625         HALMAC_CH_IDX_1 = 1,
 626         HALMAC_CH_IDX_2 = 2,
 627         HALMAC_CH_IDX_3 = 3,
 628         HALMAC_CH_IDX_4 = 4,
 629         HALMAC_CH_IDX_MAX = 5,
 630 };
 631
 632 struct halmac_ch_info {
 633         enum halmac_cs_action_id action_id;
 634         enum halmac_bw bw;
 635         enum halmac_pri_ch_idx pri_ch_idx;
 636         u8 channel;
 637         u8 timeout;
 638         u8 extra_info;
 639 };
 640
 641 struct halmac_ch_extra_info {
 642         u8 extra_info;
 643         enum halmac_cs_extra_action_id extra_action_id;
 644         u8 extra_info_size;
 645         u8 *extra_info_data;
 646 };
 647
 648 enum halmac_cs_periodic_option {
 649         HALMAC_CS_PERIODIC_NONE,
 650         HALMAC_CS_PERIODIC_NORMAL,
 651         HALMAC_CS_PERIODIC_2_PHASE,
 652         HALMAC_CS_PERIODIC_SEAMLESS,
 653 };
 654
 655 struct halmac_ch_switch_option {
 656         enum halmac_bw dest_bw;
 657         enum halmac_cs_periodic_option periodic_option;
 658         enum halmac_pri_ch_idx dest_pri_ch_idx;
 659         /* u32 tsf_high; */
 660         u32 tsf_low;
 661         bool switch_en;
 662         u8 dest_ch_en;
 663         u8 absolute_time_en;
 664         u8 dest_ch;
 665         u8 normal_period;
 666         u8 normal_cycle;
 667         u8 phase_2_period;
 668 };
 669
 670 struct halmac_fw_version {
 671         u16 version;
 672         u8 sub_version;
 673         u8 sub_index;
 674         u16 h2c_version;
 675 };
 676
 677 enum halmac_rf_type {
 678         HALMAC_RF_1T2R = 0,
 679         HALMAC_RF_2T4R = 1,
 680         HALMAC_RF_2T2R = 2,
 681         HALMAC_RF_2T3R = 3,
 682         HALMAC_RF_1T1R = 4,
 683         HALMAC_RF_2T2R_GREEN = 5,
 684         HALMAC_RF_3T3R = 6,
 685         HALMAC_RF_3T4R = 7,
 686         HALMAC_RF_4T4R = 8,
 687         HALMAC_RF_MAX_TYPE = 0xF,
 688 };
 689
 690 struct halmac_general_info {
 691         u8 rfe_type;
 692         enum halmac_rf_type rf_type;
 693 };
 694
 695 struct halmac_pwr_tracking_para {
 696         u8 enable;
 697         u8 tx_pwr_index;
 698         u8 pwr_tracking_offset_value;
 699         u8 tssi_value;
 700 };
 701
 702 struct halmac_pwr_tracking_option {
 703         u8 type;
 704         u8 bbswing_index;
 705         struct halmac_pwr_tracking_para
 706                 pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
 707 };
 708
 709 struct halmac_nlo_cfg {
 710         u8 num_of_ssid;
 711         u8 num_of_hidden_ap;
 712         u8 rsvd[2];
 713         u32 pattern_check;
 714         u32 rsvd1;
 715         u32 rsvd2;
 716         u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
 717         u8 chiper_type[HALMAC_SUPPORT_NLO_NUM];
 718         u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
 719         u8 loc_probe_req[HALMAC_SUPPORT_PROBE_REQ_NUM];
 720         u8 rsvd4[56];
 721         u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
 722 };
 723
 724 enum halmac_data_rate {
 725         HALMAC_CCK1,
 726         HALMAC_CCK2,
 727         HALMAC_CCK5_5,
 728         HALMAC_CCK11,
 729         HALMAC_OFDM6,
 730         HALMAC_OFDM9,
 731         HALMAC_OFDM12,
 732         HALMAC_OFDM18,
 733         HALMAC_OFDM24,
 734         HALMAC_OFDM36,
 735         HALMAC_OFDM48,
 736         HALMAC_OFDM54,
 737         HALMAC_MCS0,
 738         HALMAC_MCS1,
 739         HALMAC_MCS2,
 740         HALMAC_MCS3,
 741         HALMAC_MCS4,
 742         HALMAC_MCS5,
 743         HALMAC_MCS6,
 744         HALMAC_MCS7,
 745         HALMAC_MCS8,
 746         HALMAC_MCS9,
 747         HALMAC_MCS10,
 748         HALMAC_MCS11,
 749         HALMAC_MCS12,
 750         HALMAC_MCS13,
 751         HALMAC_MCS14,
 752         HALMAC_MCS15,
 753         HALMAC_MCS16,
 754         HALMAC_MCS17,
 755         HALMAC_MCS18,
 756         HALMAC_MCS19,
 757         HALMAC_MCS20,
 758         HALMAC_MCS21,
 759         HALMAC_MCS22,
 760         HALMAC_MCS23,
 761         HALMAC_MCS24,
 762         HALMAC_MCS25,
 763         HALMAC_MCS26,
 764         HALMAC_MCS27,
 765         HALMAC_MCS28,
 766         HALMAC_MCS29,
 767         HALMAC_MCS30,
 768         HALMAC_MCS31,
 769         HALMAC_VHT_NSS1_MCS0,
 770         HALMAC_VHT_NSS1_MCS1,
 771         HALMAC_VHT_NSS1_MCS2,
 772         HALMAC_VHT_NSS1_MCS3,
 773         HALMAC_VHT_NSS1_MCS4,
 774         HALMAC_VHT_NSS1_MCS5,
 775         HALMAC_VHT_NSS1_MCS6,
 776         HALMAC_VHT_NSS1_MCS7,
 777         HALMAC_VHT_NSS1_MCS8,
 778         HALMAC_VHT_NSS1_MCS9,
 779         HALMAC_VHT_NSS2_MCS0,
 780         HALMAC_VHT_NSS2_MCS1,
 781         HALMAC_VHT_NSS2_MCS2,
 782         HALMAC_VHT_NSS2_MCS3,
 783         HALMAC_VHT_NSS2_MCS4,
 784         HALMAC_VHT_NSS2_MCS5,
 785         HALMAC_VHT_NSS2_MCS6,
 786         HALMAC_VHT_NSS2_MCS7,
 787         HALMAC_VHT_NSS2_MCS8,
 788         HALMAC_VHT_NSS2_MCS9,
 789         HALMAC_VHT_NSS3_MCS0,
 790         HALMAC_VHT_NSS3_MCS1,
 791         HALMAC_VHT_NSS3_MCS2,
 792         HALMAC_VHT_NSS3_MCS3,
 793         HALMAC_VHT_NSS3_MCS4,
 794         HALMAC_VHT_NSS3_MCS5,
 795         HALMAC_VHT_NSS3_MCS6,
 796         HALMAC_VHT_NSS3_MCS7,
 797         HALMAC_VHT_NSS3_MCS8,
 798         HALMAC_VHT_NSS3_MCS9,
 799         HALMAC_VHT_NSS4_MCS0,
 800         HALMAC_VHT_NSS4_MCS1,
 801         HALMAC_VHT_NSS4_MCS2,
 802         HALMAC_VHT_NSS4_MCS3,
 803         HALMAC_VHT_NSS4_MCS4,
 804         HALMAC_VHT_NSS4_MCS5,
 805         HALMAC_VHT_NSS4_MCS6,
 806         HALMAC_VHT_NSS4_MCS7,
 807         HALMAC_VHT_NSS4_MCS8,
 808         HALMAC_VHT_NSS4_MCS9
 809 };
 810
 811 enum halmac_rf_path {
 812         HALMAC_RF_PATH_A,
 813         HALMAC_RF_PATH_B,
 814         HALMAC_RF_PATH_C,
 815         HALMAC_RF_PATH_D
 816 };
 817
 818 enum halmac_snd_pkt_sel {
 819         HALMAC_UNI_NDPA,
 820         HALMAC_BMC_NDPA,
 821         HALMAC_NON_FINAL_BFRPRPOLL,
 822         HALMAC_FINAL_BFRPTPOLL,
 823 };
 824
 825 enum hal_security_type {
 826         HAL_SECURITY_TYPE_NONE = 0,
 827         HAL_SECURITY_TYPE_WEP40 = 1,
 828         HAL_SECURITY_TYPE_WEP104 = 2,
 829         HAL_SECURITY_TYPE_TKIP = 3,
 830         HAL_SECURITY_TYPE_AES128 = 4,
 831         HAL_SECURITY_TYPE_WAPI = 5,
 832         HAL_SECURITY_TYPE_AES256 = 6,
 833         HAL_SECURITY_TYPE_GCMP128 = 7,
 834         HAL_SECURITY_TYPE_GCMP256 = 8,
 835         HAL_SECURITY_TYPE_GCMSMS4 = 9,
 836         HAL_SECURITY_TYPE_BIP = 10,
 837         HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
 838 };
 839
 840 enum hal_intf_phy {
 841         HAL_INTF_PHY_USB2 = 0,
 842         HAL_INTF_PHY_USB3 = 1,
 843         HAL_INTF_PHY_PCIE_GEN1 = 2,
 844         HAL_INTF_PHY_PCIE_GEN2 = 3,
 845         HAL_INTF_PHY_UNDEFINE = 0x7F,
 846 };
 847
 848 enum halmac_dbg_msg_info {
 849         HALMAC_DBG_ERR,
 850         HALMAC_DBG_WARN,
 851         HALMAC_DBG_TRACE,
 852 };
 853
 854 enum halmac_dbg_msg_type {
 855         HALMAC_MSG_INIT,
 856         HALMAC_MSG_EFUSE,
 857         HALMAC_MSG_FW,
 858         HALMAC_MSG_H2C,
 859         HALMAC_MSG_PWR,
 860         HALMAC_MSG_SND,
 861         HALMAC_MSG_COMMON,
 862         HALMAC_MSG_DBI,
 863         HALMAC_MSG_MDIO,
 864         HALMAC_MSG_USB
 865 };
 866
 867 enum halmac_cmd_process_status {
 868         HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
 869         HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
 870         HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
 871         HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
 872         HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
 873         HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
 874 };
 875
 876 enum halmac_feature_id {
 877         HALMAC_FEATURE_CFG_PARA, /* Support */
 878         HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
 879         HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
 880         HALMAC_FEATURE_UPDATE_PACKET, /* Support */
 881         HALMAC_FEATURE_UPDATE_DATAPACK,
 882         HALMAC_FEATURE_RUN_DATAPACK,
 883         HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
 884         HALMAC_FEATURE_IQK, /* Support */
 885         HALMAC_FEATURE_POWER_TRACKING, /* Support */
 886         HALMAC_FEATURE_PSD, /* Support */
 887         HALMAC_FEATURE_ALL, /* Support, only for reset */
 888 };
 889
 890 enum halmac_drv_rsvd_pg_num {
 891         HALMAC_RSVD_PG_NUM16, /* 2K */
 892         HALMAC_RSVD_PG_NUM24, /* 3K */
 893         HALMAC_RSVD_PG_NUM32, /* 4K */
 894 };
 895
 896 enum halmac_pcie_cfg {
 897         HALMAC_PCIE_GEN1,
 898         HALMAC_PCIE_GEN2,
 899         HALMAC_PCIE_CFG_UNDEFINE,
 900 };
 901
 902 enum halmac_portid {
 903         HALMAC_PORTID0 = 0,
 904         HALMAC_PORTID1 = 1,
 905         HALMAC_PORTID2 = 2,
 906         HALMAC_PORTID3 = 3,
 907         HALMAC_PORTID4 = 4,
 908         HALMAC_PORTIDMAX
 909 };
 910
 911 struct halmac_p2pps {
 912         /*DW0*/
 913         u8 offload_en : 1;
 914         u8 role : 1;
 915         u8 ctwindow_en : 1;
 916         u8 noa_en : 1;
 917         u8 noa_sel : 1;
 918         u8 all_sta_sleep : 1;
 919         u8 discovery : 1;
 920         u8 rsvd2 : 1;
 921         u8 p2p_port_id;
 922         u8 p2p_group;
 923         u8 p2p_macid;
 924
 925         /*DW1*/
 926         u8 ctwindow_length;
 927         u8 rsvd3;
 928         u8 rsvd4;
 929         u8 rsvd5;
 930
 931         /*DW2*/
 932         u32 noa_duration_para;
 933
 934         /*DW3*/
 935         u32 noa_interval_para;
 936
 937         /*DW4*/
 938         u32 noa_start_time_para;
 939
 940         /*DW5*/
 941         u32 noa_count_para;
 942 };
 943
 944 /* Platform API setting */
 945 struct halmac_platform_api {
 946         /* R/W register */
 947         u8 (*SDIO_CMD52_READ)(void *driver_adapter, u32 offset);
 948         u8 (*SDIO_CMD53_READ_8)(void *driver_adapter, u32 offset);
 949         u16 (*SDIO_CMD53_READ_16)(void *driver_adapter, u32 offset);
 950         u32 (*SDIO_CMD53_READ_32)(void *driver_adapter, u32 offset);
 951         u8 (*SDIO_CMD53_READ_N)(void *driver_adapter, u32 offset, u32 size,
 952                                 u8 *data);
 953         void (*SDIO_CMD52_WRITE)(void *driver_adapter, u32 offset, u8 value);
 954         void (*SDIO_CMD53_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
 955         void (*SDIO_CMD53_WRITE_16)(void *driver_adapter, u32 offset,
 956                                     u16 value);
 957         void (*SDIO_CMD53_WRITE_32)(void *driver_adapter, u32 offset,
 958                                     u32 value);
 959         u8 (*REG_READ_8)(void *driver_adapter, u32 offset);
 960         u16 (*REG_READ_16)(void *driver_adapter, u32 offset);
 961         u32 (*REG_READ_32)(void *driver_adapter, u32 offset);
 962         void (*REG_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
 963         void (*REG_WRITE_16)(void *driver_adapter, u32 offset, u16 value);
 964         void (*REG_WRITE_32)(void *driver_adapter, u32 offset, u32 value);
 965
 966         /* send buf to reserved page, the tx_desc is not included in buf,
 967          * driver need to fill tx_desc with qsel = bcn
 968          */
 969         bool (*SEND_RSVD_PAGE)(void *driver_adapter, u8 *buf, u32 size);
 970         /* send buf to h2c queue, the tx_desc is not included in buf,
 971          * driver need to fill tx_desc with qsel = h2c
 972          */
 973         bool (*SEND_H2C_PKT)(void *driver_adapter, u8 *buf, u32 size);
 974
 975         bool (*EVENT_INDICATION)(void *driver_adapter,
 976                                  enum halmac_feature_id feature_id,
 977                                  enum halmac_cmd_process_status process_status,
 978                                  u8 *buf, u32 size);
 979 };
 980
 981 /*1->Little endian 0->Big endian*/
 982 #if HALMAC_SYSTEM_ENDIAN
 983
 984 #else
 985
 986 #endif
 987
 988 /* User can not use members in address_l_h, use address[6] is mandatory */
 989 union halmac_wlan_addr {
 990         u8 address[6]; /* WLAN address (MACID, BSSID, Brodcast ID).
 991                         * address[0] is lowest, address[5] is highest
 992                         */
 993         struct {
 994                 union {
 995                         u32 address_low;
 996                         __le32 le_address_low;
 997                         u8 address_low_b[4];
 998                 };
 999                 union {
1000                         u16 address_high;
1001                         __le16 le_address_high;
1002                         u8 address_high_b[2];
1003                 };
1004         } address_l_h;
1005 };
1006
1007 enum halmac_snd_role {
1008         HAL_BFER = 0,
1009         HAL_BFEE = 1,
1010 };
1011
1012 enum halmac_csi_seg_len {
1013         HAL_CSI_SEG_4K = 0,
1014         HAL_CSI_SEG_8K = 1,
1015         HAL_CSI_SEG_11K = 2,
1016 };
1017
1018 struct halmac_cfg_mumimo_para {
1019         enum halmac_snd_role role;
1020         bool sounding_sts[6];
1021         u16 grouping_bitmap;
1022         bool mu_tx_en;
1023         u32 given_gid_tab[2];
1024         u32 given_user_pos[4];
1025 };
1026
1027 struct halmac_su_bfer_init_para {
1028         u8 userid;
1029         u16 paid;
1030         u16 csi_para;
1031         union halmac_wlan_addr bfer_address;
1032 };
1033
1034 struct halmac_mu_bfee_init_para {
1035         u8 userid;
1036         u16 paid;
1037         u32 user_position_l;
1038         u32 user_position_h;
1039 };
1040
1041 struct halmac_mu_bfer_init_para {
1042         u16 paid;
1043         u16 csi_para;
1044         u16 my_aid;
1045         enum halmac_csi_seg_len csi_length_sel;
1046         union halmac_wlan_addr bfer_address;
1047 };
1048
1049 struct halmac_snd_info {
1050         u16 paid;
1051         u8 userid;
1052         enum halmac_data_rate ndpa_rate;
1053         u16 csi_para;
1054         u16 my_aid;
1055         enum halmac_data_rate csi_rate;
1056         enum halmac_csi_seg_len csi_length_sel;
1057         enum halmac_snd_role role;
1058         union halmac_wlan_addr bfer_address;
1059         enum halmac_bw bw;
1060         u8 txbf_en;
1061         struct halmac_su_bfer_init_para *su_bfer_init;
1062         struct halmac_mu_bfer_init_para *mu_bfer_init;
1063         struct halmac_mu_bfee_init_para *mu_bfee_init;
1064 };
1065
1066 struct halmac_cs_info {
1067         u8 *ch_info_buf;
1068         u8 *ch_info_buf_w;
1069         u8 extra_info_en;
1070         u32 buf_size; /* buffer size */
1071         u32 avai_buf_size; /* buffer size */
1072         u32 total_size;
1073         u32 accu_timeout;
1074         u32 ch_num;
1075 };
1076
1077 struct halmac_restore_info {
1078         u32 mac_register;
1079         u32 value;
1080         u8 length;
1081 };
1082
1083 struct halmac_event_trigger {
1084         u32 physical_efuse_map : 1;
1085         u32 logical_efuse_map : 1;
1086         u32 rsvd1 : 28;
1087 };
1088
1089 struct halmac_h2c_header_info {
1090         u16 sub_cmd_id;
1091         u16 content_size;
1092         bool ack;
1093 };
1094
1095 enum halmac_dlfw_state {
1096         HALMAC_DLFW_NONE = 0,
1097         HALMAC_DLFW_DONE = 1,
1098         HALMAC_GEN_INFO_SENT = 2,
1099         HALMAC_DLFW_UNDEFINED = 0x7F,
1100 };
1101
1102 enum halmac_efuse_cmd_construct_state {
1103         HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
1104         HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
1105         HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
1106         HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
1107         HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1108 };
1109
1110 enum halmac_cfg_para_cmd_construct_state {
1111         HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
1112         HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
1113         HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
1114         HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
1115         HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1116 };
1117
1118 enum halmac_scan_cmd_construct_state {
1119         HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
1120         HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
1121         HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
1122         HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
1123         HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
1124         HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1125 };
1126
1127 enum halmac_api_state {
1128         HALMAC_API_STATE_INIT = 0,
1129         HALMAC_API_STATE_HALT = 1,
1130         HALMAC_API_STATE_UNDEFINED = 0x7F,
1131 };
1132
1133 struct halmac_efuse_state_set {
1134         enum halmac_efuse_cmd_construct_state efuse_cmd_construct_state;
1135         enum halmac_cmd_process_status process_status;
1136         u8 fw_return_code;
1137         u16 seq_num;
1138 };
1139
1140 struct halmac_cfg_para_state_set {
1141         enum halmac_cfg_para_cmd_construct_state cfg_para_cmd_construct_state;
1142         enum halmac_cmd_process_status process_status;
1143         u8 fw_return_code;
1144         u16 seq_num;
1145 };
1146
1147 struct halmac_scan_state_set {
1148         enum halmac_scan_cmd_construct_state scan_cmd_construct_state;
1149         enum halmac_cmd_process_status process_status;
1150         u8 fw_return_code;
1151         u16 seq_num;
1152 };
1153
1154 struct halmac_update_packet_state_set {
1155         enum halmac_cmd_process_status process_status;
1156         u8 fw_return_code;
1157         u16 seq_num;
1158 };
1159
1160 struct halmac_iqk_state_set {
1161         enum halmac_cmd_process_status process_status;
1162         u8 fw_return_code;
1163         u16 seq_num;
1164 };
1165
1166 struct halmac_power_tracking_state_set {
1167         enum halmac_cmd_process_status process_status;
1168         u8 fw_return_code;
1169         u16 seq_num;
1170 };
1171
1172 struct halmac_psd_state_set {
1173         enum halmac_cmd_process_status process_status;
1174         u16 data_size;
1175         u16 segment_size;
1176         u8 *data;
1177         u8 fw_return_code;
1178         u16 seq_num;
1179 };
1180
1181 struct halmac_state {
1182         struct halmac_efuse_state_set
1183                 efuse_state_set; /* State machine + cmd process status */
1184         struct halmac_cfg_para_state_set
1185                 cfg_para_state_set; /* State machine + cmd process status */
1186         struct halmac_scan_state_set
1187                 scan_state_set; /* State machine + cmd process status */
1188         struct halmac_update_packet_state_set
1189                 update_packet_set; /* cmd process status */
1190         struct halmac_iqk_state_set iqk_set; /* cmd process status */
1191         struct halmac_power_tracking_state_set
1192                 power_tracking_set; /* cmd process status */
1193         struct halmac_psd_state_set psd_set; /* cmd process status */
1194         enum halmac_api_state api_state; /* Halmac api state */
1195         enum halmac_mac_power mac_power; /* 0 : power off, 1 : power on*/
1196         enum halmac_ps_state ps_state; /* power saving state */
1197         enum halmac_dlfw_state dlfw_state; /* download FW state */
1198 };
1199
1200 struct halmac_ver {
1201         u8 major_ver;
1202         u8 prototype_ver;
1203         u8 minor_ver;
1204 };
1205
1206 enum halmac_api_id {
1207         /*stuff, need to be the 1st*/
1208         HALMAC_API_STUFF = 0x0,
1209         /*stuff, need to be the 1st*/
1210         HALMAC_API_MAC_POWER_SWITCH = 0x1,
1211         HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
1212         HALMAC_API_CFG_MAC_ADDR = 0x3,
1213         HALMAC_API_CFG_BSSID = 0x4,
1214         HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
1215         HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
1216         HALMAC_API_INIT_SYSTEM_CFG = 0x7,
1217         HALMAC_API_INIT_TRX_CFG = 0x8,
1218         HALMAC_API_CFG_RX_AGGREGATION = 0x9,
1219         HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
1220         HALMAC_API_INIT_EDCA_CFG = 0xB,
1221         HALMAC_API_CFG_OPERATION_MODE = 0xC,
1222         HALMAC_API_CFG_CH_BW = 0xD,
1223         HALMAC_API_CFG_BW = 0xE,
1224         HALMAC_API_INIT_WMAC_CFG = 0xF,
1225         HALMAC_API_INIT_MAC_CFG = 0x10,
1226         HALMAC_API_INIT_SDIO_CFG = 0x11,
1227         HALMAC_API_INIT_USB_CFG = 0x12,
1228         HALMAC_API_INIT_PCIE_CFG = 0x13,
1229         HALMAC_API_INIT_INTERFACE_CFG = 0x14,
1230         HALMAC_API_DEINIT_SDIO_CFG = 0x15,
1231         HALMAC_API_DEINIT_USB_CFG = 0x16,
1232         HALMAC_API_DEINIT_PCIE_CFG = 0x17,
1233         HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
1234         HALMAC_API_GET_EFUSE_SIZE = 0x19,
1235         HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
1236         HALMAC_API_WRITE_EFUSE = 0x1B,
1237         HALMAC_API_READ_EFUSE = 0x1C,
1238         HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
1239         HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
1240         HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
1241         HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
1242         HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
1243         HALMAC_API_GET_C2H_INFO = 0x22,
1244         HALMAC_API_CFG_FWLPS_OPTION = 0x23,
1245         HALMAC_API_CFG_FWIPS_OPTION = 0x24,
1246         HALMAC_API_ENTER_WOWLAN = 0x25,
1247         HALMAC_API_LEAVE_WOWLAN = 0x26,
1248         HALMAC_API_ENTER_PS = 0x27,
1249         HALMAC_API_LEAVE_PS = 0x28,
1250         HALMAC_API_H2C_LB = 0x29,
1251         HALMAC_API_DEBUG = 0x2A,
1252         HALMAC_API_CFG_PARAMETER = 0x2B,
1253         HALMAC_API_UPDATE_PACKET = 0x2C,
1254         HALMAC_API_BCN_IE_FILTER = 0x2D,
1255         HALMAC_API_REG_READ_8 = 0x2E,
1256         HALMAC_API_REG_WRITE_8 = 0x2F,
1257         HALMAC_API_REG_READ_16 = 0x30,
1258         HALMAC_API_REG_WRITE_16 = 0x31,
1259         HALMAC_API_REG_READ_32 = 0x32,
1260         HALMAC_API_REG_WRITE_32 = 0x33,
1261         HALMAC_API_TX_ALLOWED_SDIO = 0x34,
1262         HALMAC_API_SET_BULKOUT_NUM = 0x35,
1263         HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
1264         HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
1265         HALMAC_API_TIMER_2S = 0x38,
1266         HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
1267         HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
1268         HALMAC_API_UPDATE_DATAPACK = 0x3B,
1269         HALMAC_API_RUN_DATAPACK = 0x3C,
1270         HALMAC_API_CFG_DRV_INFO = 0x3D,
1271         HALMAC_API_SEND_BT_COEX = 0x3E,
1272         HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
1273         HALMAC_API_GET_FIFO_SIZE = 0x40,
1274         HALMAC_API_DUMP_FIFO = 0x41,
1275         HALMAC_API_CFG_TXBF = 0x42,
1276         HALMAC_API_CFG_MUMIMO = 0x43,
1277         HALMAC_API_CFG_SOUNDING = 0x44,
1278         HALMAC_API_DEL_SOUNDING = 0x45,
1279         HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
1280         HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
1281         HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
1282         HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
1283         HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
1284         HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
1285         HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
1286         HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
1287
1288         HALMAC_API_ADD_CH_INFO = 0x4E,
1289         HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
1290         HALMAC_API_CTRL_CH_SWITCH = 0x50,
1291         HALMAC_API_CLEAR_CH_INFO = 0x51,
1292
1293         HALMAC_API_SEND_GENERAL_INFO = 0x52,
1294         HALMAC_API_START_IQK = 0x53,
1295         HALMAC_API_CTRL_PWR_TRACKING = 0x54,
1296         HALMAC_API_PSD = 0x55,
1297         HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
1298
1299         HALMAC_API_QUERY_STATE = 0x57,
1300         HALMAC_API_RESET_FEATURE = 0x58,
1301         HALMAC_API_CHECK_FW_STATUS = 0x59,
1302         HALMAC_API_DUMP_FW_DMEM = 0x5A,
1303         HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
1304
1305         HALMAC_API_INIT_OBJ = 0x5C,
1306         HALMAC_API_DEINIT_OBJ = 0x5D,
1307         HALMAC_API_CFG_LA_MODE = 0x5E,
1308         HALMAC_API_GET_HW_VALUE = 0x5F,
1309         HALMAC_API_SET_HW_VALUE = 0x60,
1310         HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
1311         HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
1312         HALMAC_API_WRITE_EFUSE_BT = 0x63,
1313         HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
1314         HALMAC_API_DL_DRV_RSVD_PG = 0x65,
1315         HALMAC_API_PCIE_SWITCH = 0x66,
1316         HALMAC_API_PHY_CFG = 0x67,
1317         HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
1318         HALMAC_API_CFG_CSI_RATE = 0x69,
1319         HALMAC_API_MAX
1320 };
1321
1322 struct halmac_api_record {
1323         enum halmac_api_id api_array[API_ARRAY_SIZE];
1324         u8 array_wptr;
1325 };
1326
1327 enum halmac_la_mode {
1328         HALMAC_LA_MODE_DISABLE = 0,
1329         HALMAC_LA_MODE_PARTIAL = 1,
1330         HALMAC_LA_MODE_FULL = 2,
1331         HALMAC_LA_MODE_UNDEFINE = 0x7F,
1332 };
1333
1334 enum halmac_rx_fifo_expanding_mode {
1335         HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
1336         HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
1337         HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
1338         HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
1339         HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
1340 };
1341
1342 enum halmac_sdio_cmd53_4byte_mode {
1343         HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
1344         HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
1345         HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
1346         HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
1347         HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
1348 };
1349
1350 enum halmac_usb_mode {
1351         HALMAC_USB_MODE_U2 = 1,
1352         HALMAC_USB_MODE_U3 = 2,
1353 };
1354
1355 enum halmac_hw_id {
1356         /* Get HW value */
1357         HALMAC_HW_RQPN_MAPPING = 0x00,
1358         HALMAC_HW_EFUSE_SIZE = 0x01,
1359         HALMAC_HW_EEPROM_SIZE = 0x02,
1360         HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
1361         HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
1362         HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
1363         HALMAC_HW_TXFIFO_SIZE = 0x06,
1364         HALMAC_HW_RSVD_PG_BNDY = 0x07,
1365         HALMAC_HW_CAM_ENTRY_NUM = 0x08,
1366         HALMAC_HW_IC_VERSION = 0x09,
1367         HALMAC_HW_PAGE_SIZE = 0x0A,
1368         HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B,
1369         HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C,
1370         HALMAC_HW_DRV_INFO_SIZE = 0x0D,
1371         HALMAC_HW_TXFF_ALLOCATION = 0x0E,
1372         HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F,
1373         HALMAC_HW_FW_HDR_SIZE = 0x10,
1374         HALMAC_HW_TX_DESC_SIZE = 0x11,
1375         HALMAC_HW_RX_DESC_SIZE = 0x12,
1376         HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13,
1377         /* Set HW value */
1378         HALMAC_HW_USB_MODE = 0x60,
1379         HALMAC_HW_SEQ_EN = 0x61,
1380         HALMAC_HW_BANDWIDTH = 0x62,
1381         HALMAC_HW_CHANNEL = 0x63,
1382         HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
1383         HALMAC_HW_EN_BB_RF = 0x65,
1384         HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
1385         HALMAC_HW_AMPDU_CONFIG = 0x67,
1386
1387         HALMAC_HW_ID_UNDEFINE = 0x7F,
1388 };
1389
1390 enum halmac_efuse_bank {
1391         HALMAC_EFUSE_BANK_WIFI = 0,
1392         HALMAC_EFUSE_BANK_BT = 1,
1393         HALMAC_EFUSE_BANK_BT_1 = 2,
1394         HALMAC_EFUSE_BANK_BT_2 = 3,
1395         HALMAC_EFUSE_BANK_MAX,
1396         HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
1397 };
1398
1399 struct halmac_txff_allocation {
1400         u16 tx_fifo_pg_num;
1401         u16 rsvd_pg_num;
1402         u16 rsvd_drv_pg_num;
1403         u16 ac_q_pg_num;
1404         u16 high_queue_pg_num;
1405         u16 low_queue_pg_num;
1406         u16 normal_queue_pg_num;
1407         u16 extra_queue_pg_num;
1408         u16 pub_queue_pg_num;
1409         u16 rsvd_pg_bndy;
1410         u16 rsvd_drv_pg_bndy;
1411         u16 rsvd_h2c_extra_info_pg_bndy;
1412         u16 rsvd_h2c_queue_pg_bndy;
1413         u16 rsvd_cpu_instr_pg_bndy;
1414         u16 rsvd_fw_txbuff_pg_bndy;
1415         enum halmac_la_mode la_mode;
1416         enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode;
1417 };
1418
1419 struct halmac_rqpn_map {
1420         enum halmac_dma_mapping dma_map_vo;
1421         enum halmac_dma_mapping dma_map_vi;
1422         enum halmac_dma_mapping dma_map_be;
1423         enum halmac_dma_mapping dma_map_bk;
1424         enum halmac_dma_mapping dma_map_mg;
1425         enum halmac_dma_mapping dma_map_hi;
1426 };
1427
1428 struct halmac_security_setting {
1429         u8 tx_encryption;
1430         u8 rx_decryption;
1431         u8 bip_enable;
1432 };
1433
1434 struct halmac_cam_entry_info {
1435         enum hal_security_type security_type;
1436         u32 key[4];
1437         u32 key_ext[4];
1438         u8 mac_address[6];
1439         u8 unicast;
1440         u8 key_id;
1441         u8 valid;
1442 };
1443
1444 struct halmac_cam_entry_format {
1445         u16 key_id : 2;
1446         u16 type : 3;
1447         u16 mic : 1;
1448         u16 grp : 1;
1449         u16 spp_mode : 1;
1450         u16 rpt_md : 1;
1451         u16 ext_sectype : 1;
1452         u16 mgnt : 1;
1453         u16 rsvd1 : 4;
1454         u16 valid : 1;
1455         u8 mac_address[6];
1456         u32 key[4];
1457         u32 rsvd[2];
1458 };
1459
1460 struct halmac_tx_page_threshold_info {
1461         u32 threshold;
1462         enum halmac_dma_mapping dma_queue_sel;
1463 };
1464
1465 struct halmac_ampdu_config {
1466         u8 max_agg_num;
1467 };
1468
1469 struct halmac_port_cfg {
1470         u8 port0_sync_tsf;
1471         u8 port1_sync_tsf;
1472 };
1473
1474 struct halmac_rqpn_ {
1475         enum halmac_trx_mode mode;
1476         enum halmac_dma_mapping dma_map_vo;
1477         enum halmac_dma_mapping dma_map_vi;
1478         enum halmac_dma_mapping dma_map_be;
1479         enum halmac_dma_mapping dma_map_bk;
1480         enum halmac_dma_mapping dma_map_mg;
1481         enum halmac_dma_mapping dma_map_hi;
1482 };
1483
1484 struct halmac_pg_num_ {
1485         enum halmac_trx_mode mode;
1486         u16 hq_num;
1487         u16 nq_num;
1488         u16 lq_num;
1489         u16 exq_num;
1490         u16 gap_num; /*used for loopback mode*/
1491 };
1492
1493 struct halmac_intf_phy_para_ {
1494         u16 offset;
1495         u16 value;
1496         u16 ip_sel;
1497         u16 cut;
1498         u16 plaform;
1499 };
1500
1501 struct halmac_iqk_para_ {
1502         u8 clear;
1503         u8 segment_iqk;
1504 };
1505
1506 /* Hal mac adapter */
1507 struct halmac_adapter {
1508         /* Dma mapping of protocol queues */
1509         enum halmac_dma_mapping halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM];
1510         /* low power state option */
1511         struct halmac_fwlps_option fwlps_option;
1512         /* mac address information, suppot 2 ports */
1513         union halmac_wlan_addr hal_mac_addr[HALMAC_PORTIDMAX];
1514         /* bss address information, suppot 2 ports */
1515         union halmac_wlan_addr hal_bss_addr[HALMAC_PORTIDMAX];
1516         /* Protect h2c_packet_seq packet*/
1517         spinlock_t h2c_seq_lock;
1518         /* Protect Efuse map memory of halmac_adapter */
1519         spinlock_t efuse_lock;
1520         struct halmac_config_para_info config_para_info;
1521         struct halmac_cs_info ch_sw_info;
1522         struct halmac_event_trigger event_trigger;
1523         /* HW related information */
1524         struct halmac_hw_config_info hw_config_info;
1525         struct halmac_sdio_free_space sdio_free_space;
1526         struct halmac_snd_info snd_info;
1527         /* Backup HalAdapter address */
1528         void *hal_adapter_backup;
1529         /* Driver or FW adapter address. Do not write this memory*/
1530         void *driver_adapter;
1531         u8 *hal_efuse_map;
1532         /* Record function pointer of halmac api */
1533         void *halmac_api;
1534         /* Record function pointer of platform api */
1535         struct halmac_platform_api *halmac_platform_api;
1536         /* Record efuse used memory */
1537         u32 efuse_end;
1538         u32 h2c_buf_free_space;
1539         u32 h2c_buff_size;
1540         u32 max_download_size;
1541         /* Chip ID, 8822B, 8821C... */
1542         enum halmac_chip_id chip_id;
1543         /* A cut, B cut... */
1544         enum halmac_chip_ver chip_version;
1545         struct halmac_fw_version fw_version;
1546         struct halmac_state halmac_state;
1547         /* Interface information, get from driver */
1548         enum halmac_interface halmac_interface;
1549         /* Noraml, WMM, P2P, LoopBack... */
1550         enum halmac_trx_mode trx_mode;
1551         struct halmac_txff_allocation txff_allocation;
1552         u8 h2c_packet_seq; /* current h2c packet sequence number */
1553         u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
1554         bool hal_efuse_map_valid;
1555         u8 efuse_segment_size;
1556         u8 rpwm_record; /* record rpwm value */
1557         bool low_clk; /*LPS 32K or IPS 32K*/
1558         u8 halmac_bulkout_num; /* USB bulkout num */
1559         struct halmac_api_record api_record; /* API record */
1560         bool gen_info_valid;
1561         struct halmac_general_info general_info;
1562         u8 drv_info_size;
1563         enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
1564 };
1565
1566 /* Function pointer of  Hal mac API */
1567 struct halmac_api {
1568         enum halmac_ret_status (*halmac_mac_power_switch)(
1569                 struct halmac_adapter *halmac_adapter,
1570                 enum halmac_mac_power halmac_power);
1571         enum halmac_ret_status (*halmac_download_firmware)(
1572                 struct halmac_adapter *halmac_adapter, u8 *hamacl_fw,
1573                 u32 halmac_fw_size);
1574         enum halmac_ret_status (*halmac_free_download_firmware)(
1575                 struct halmac_adapter *halmac_adapter,
1576                 enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
1577                 u32 halmac_fw_size);
1578         enum halmac_ret_status (*halmac_get_fw_version)(
1579                 struct halmac_adapter *halmac_adapter,
1580                 struct halmac_fw_version *fw_version);
1581         enum halmac_ret_status (*halmac_cfg_mac_addr)(
1582                 struct halmac_adapter *halmac_adapter, u8 halmac_port,
1583                 union halmac_wlan_addr *hal_address);
1584         enum halmac_ret_status (*halmac_cfg_bssid)(
1585                 struct halmac_adapter *halmac_adapter, u8 halmac_port,
1586                 union halmac_wlan_addr *hal_address);
1587         enum halmac_ret_status (*halmac_cfg_multicast_addr)(
1588                 struct halmac_adapter *halmac_adapter,
1589                 union halmac_wlan_addr *hal_address);
1590         enum halmac_ret_status (*halmac_pre_init_system_cfg)(
1591                 struct halmac_adapter *halmac_adapter);
1592         enum halmac_ret_status (*halmac_init_system_cfg)(
1593                 struct halmac_adapter *halmac_adapter);
1594         enum halmac_ret_status (*halmac_init_trx_cfg)(
1595                 struct halmac_adapter *halmac_adapter,
1596                 enum halmac_trx_mode mode);
1597         enum halmac_ret_status (*halmac_init_h2c)(
1598                 struct halmac_adapter *halmac_adapter);
1599         enum halmac_ret_status (*halmac_cfg_rx_aggregation)(
1600                 struct halmac_adapter *halmac_adapter,
1601                 struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
1602         enum halmac_ret_status (*halmac_init_protocol_cfg)(
1603                 struct halmac_adapter *halmac_adapter);
1604         enum halmac_ret_status (*halmac_init_edca_cfg)(
1605                 struct halmac_adapter *halmac_adapter);
1606         enum halmac_ret_status (*halmac_cfg_operation_mode)(
1607                 struct halmac_adapter *halmac_adapter,
1608                 enum halmac_wireless_mode wireless_mode);
1609         enum halmac_ret_status (*halmac_cfg_ch_bw)(
1610                 struct halmac_adapter *halmac_adapter, u8 channel,
1611                 enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
1612         enum halmac_ret_status (*halmac_cfg_bw)(
1613                 struct halmac_adapter *halmac_adapter, enum halmac_bw bw);
1614         enum halmac_ret_status (*halmac_init_wmac_cfg)(
1615                 struct halmac_adapter *halmac_adapter);
1616         enum halmac_ret_status (*halmac_init_mac_cfg)(
1617                 struct halmac_adapter *halmac_adapter,
1618                 enum halmac_trx_mode mode);
1619         enum halmac_ret_status (*halmac_init_sdio_cfg)(
1620                 struct halmac_adapter *halmac_adapter);
1621         enum halmac_ret_status (*halmac_init_usb_cfg)(
1622                 struct halmac_adapter *halmac_adapter);
1623         enum halmac_ret_status (*halmac_init_pcie_cfg)(
1624                 struct halmac_adapter *halmac_adapter);
1625         enum halmac_ret_status (*halmac_init_interface_cfg)(
1626                 struct halmac_adapter *halmac_adapter);
1627         enum halmac_ret_status (*halmac_deinit_sdio_cfg)(
1628                 struct halmac_adapter *halmac_adapter);
1629         enum halmac_ret_status (*halmac_deinit_usb_cfg)(
1630                 struct halmac_adapter *halmac_adapter);
1631         enum halmac_ret_status (*halmac_deinit_pcie_cfg)(
1632                 struct halmac_adapter *halmac_adapter);
1633         enum halmac_ret_status (*halmac_deinit_interface_cfg)(
1634                 struct halmac_adapter *halmac_adapter);
1635         enum halmac_ret_status (*halmac_get_efuse_size)(
1636                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1637         enum halmac_ret_status (*halmac_get_efuse_available_size)(
1638                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1639         enum halmac_ret_status (*halmac_dump_efuse_map)(
1640                 struct halmac_adapter *halmac_adapter,
1641                 enum halmac_efuse_read_cfg cfg);
1642         enum halmac_ret_status (*halmac_dump_efuse_map_bt)(
1643                 struct halmac_adapter *halmac_adapter,
1644                 enum halmac_efuse_bank halmac_efues_bank, u32 bt_efuse_map_size,
1645                 u8 *bt_efuse_map);
1646         enum halmac_ret_status (*halmac_write_efuse)(
1647                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1648                 u8 halmac_value);
1649         enum halmac_ret_status (*halmac_read_efuse)(
1650                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1651                 u8 *value);
1652         enum halmac_ret_status (*halmac_switch_efuse_bank)(
1653                 struct halmac_adapter *halmac_adapter,
1654                 enum halmac_efuse_bank halmac_efues_bank);
1655         enum halmac_ret_status (*halmac_write_efuse_bt)(
1656                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1657                 u8 halmac_value, enum halmac_efuse_bank halmac_efues_bank);
1658         enum halmac_ret_status (*halmac_get_logical_efuse_size)(
1659                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1660         enum halmac_ret_status (*halmac_dump_logical_efuse_map)(
1661                 struct halmac_adapter *halmac_adapter,
1662                 enum halmac_efuse_read_cfg cfg);
1663         enum halmac_ret_status (*halmac_write_logical_efuse)(
1664                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1665                 u8 halmac_value);
1666         enum halmac_ret_status (*halmac_read_logical_efuse)(
1667                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1668                 u8 *value);
1669         enum halmac_ret_status (*halmac_pg_efuse_by_map)(
1670                 struct halmac_adapter *halmac_adapter,
1671                 struct halmac_pg_efuse_info *pg_efuse_info,
1672                 enum halmac_efuse_read_cfg cfg);
1673         enum halmac_ret_status (*halmac_get_c2h_info)(
1674                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1675                 u32 halmac_size);
1676         enum halmac_ret_status (*halmac_cfg_fwlps_option)(
1677                 struct halmac_adapter *halmac_adapter,
1678                 struct halmac_fwlps_option *lps_option);
1679         enum halmac_ret_status (*halmac_cfg_fwips_option)(
1680                 struct halmac_adapter *halmac_adapter,
1681                 struct halmac_fwips_option *ips_option);
1682         enum halmac_ret_status (*halmac_enter_wowlan)(
1683                 struct halmac_adapter *halmac_adapter,
1684                 struct halmac_wowlan_option *wowlan_option);
1685         enum halmac_ret_status (*halmac_leave_wowlan)(
1686                 struct halmac_adapter *halmac_adapter);
1687         enum halmac_ret_status (*halmac_enter_ps)(
1688                 struct halmac_adapter *halmac_adapter,
1689                 enum halmac_ps_state ps_state);
1690         enum halmac_ret_status (*halmac_leave_ps)(
1691                 struct halmac_adapter *halmac_adapter);
1692         enum halmac_ret_status (*halmac_h2c_lb)(
1693                 struct halmac_adapter *halmac_adapter);
1694         enum halmac_ret_status (*halmac_debug)(
1695                 struct halmac_adapter *halmac_adapter);
1696         enum halmac_ret_status (*halmac_cfg_parameter)(
1697                 struct halmac_adapter *halmac_adapter,
1698                 struct halmac_phy_parameter_info *para_info, u8 full_fifo);
1699         enum halmac_ret_status (*halmac_update_packet)(
1700                 struct halmac_adapter *halmac_adapter,
1701                 enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
1702         enum halmac_ret_status (*halmac_bcn_ie_filter)(
1703                 struct halmac_adapter *halmac_adapter,
1704                 struct halmac_bcn_ie_info *bcn_ie_info);
1705         u8 (*halmac_reg_read_8)(struct halmac_adapter *halmac_adapter,
1706                                 u32 halmac_offset);
1707         enum halmac_ret_status (*halmac_reg_write_8)(
1708                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1709                 u8 halmac_data);
1710         u16 (*halmac_reg_read_16)(struct halmac_adapter *halmac_adapter,
1711                                   u32 halmac_offset);
1712         enum halmac_ret_status (*halmac_reg_write_16)(
1713                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1714                 u16 halmac_data);
1715         u32 (*halmac_reg_read_32)(struct halmac_adapter *halmac_adapter,
1716                                   u32 halmac_offset);
1717         u32 (*halmac_reg_read_indirect_32)(
1718                 struct halmac_adapter *halmac_adapter, u32 halmac_offset);
1719         u8 (*halmac_reg_sdio_cmd53_read_n)(
1720                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1721                 u32 halmac_size, u8 *halmac_data);
1722         enum halmac_ret_status (*halmac_reg_write_32)(
1723                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1724                 u32 halmac_data);
1725         enum halmac_ret_status (*halmac_tx_allowed_sdio)(
1726                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1727                 u32 halmac_size);
1728         enum halmac_ret_status (*halmac_set_bulkout_num)(
1729                 struct halmac_adapter *halmac_adapter, u8 bulkout_num);
1730         enum halmac_ret_status (*halmac_get_sdio_tx_addr)(
1731                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1732                 u32 halmac_size, u32 *pcmd53_addr);
1733         enum halmac_ret_status (*halmac_get_usb_bulkout_id)(
1734                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1735                 u32 halmac_size, u8 *bulkout_id);
1736         enum halmac_ret_status (*halmac_timer_2s)(
1737                 struct halmac_adapter *halmac_adapter);
1738         enum halmac_ret_status (*halmac_fill_txdesc_checksum)(
1739                 struct halmac_adapter *halmac_adapter, u8 *cur_desc);
1740         enum halmac_ret_status (*halmac_update_datapack)(
1741                 struct halmac_adapter *halmac_adapter,
1742                 enum halmac_data_type halmac_data_type,
1743                 struct halmac_phy_parameter_info *para_info);
1744         enum halmac_ret_status (*halmac_run_datapack)(
1745                 struct halmac_adapter *halmac_adapter,
1746                 enum halmac_data_type halmac_data_type);
1747         enum halmac_ret_status (*halmac_cfg_drv_info)(
1748                 struct halmac_adapter *halmac_adapter,
1749                 enum halmac_drv_info halmac_drv_info);
1750         enum halmac_ret_status (*halmac_send_bt_coex)(
1751                 struct halmac_adapter *halmac_adapter, u8 *bt_buf, u32 bt_size,
1752                 u8 ack);
1753         enum halmac_ret_status (*halmac_verify_platform_api)(
1754                 struct halmac_adapter *halmac_adapte);
1755         u32 (*halmac_get_fifo_size)(struct halmac_adapter *halmac_adapter,
1756                                     enum hal_fifo_sel halmac_fifo_sel);
1757         enum halmac_ret_status (*halmac_dump_fifo)(
1758                 struct halmac_adapter *halmac_adapter,
1759                 enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
1760                 u32 halmac_fifo_dump_size, u8 *fifo_map);
1761         enum halmac_ret_status (*halmac_cfg_txbf)(
1762                 struct halmac_adapter *halmac_adapter, u8 userid,
1763                 enum halmac_bw bw, u8 txbf_en);
1764         enum halmac_ret_status (*halmac_cfg_mumimo)(
1765                 struct halmac_adapter *halmac_adapter,
1766                 struct halmac_cfg_mumimo_para *cfgmu);
1767         enum halmac_ret_status (*halmac_cfg_sounding)(
1768                 struct halmac_adapter *halmac_adapter,
1769                 enum halmac_snd_role role, enum halmac_data_rate datarate);
1770         enum halmac_ret_status (*halmac_del_sounding)(
1771                 struct halmac_adapter *halmac_adapter,
1772                 enum halmac_snd_role role);
1773         enum halmac_ret_status (*halmac_su_bfer_entry_init)(
1774                 struct halmac_adapter *halmac_adapter,
1775                 struct halmac_su_bfer_init_para *su_bfer_init);
1776         enum halmac_ret_status (*halmac_su_bfee_entry_init)(
1777                 struct halmac_adapter *halmac_adapter, u8 userid, u16 paid);
1778         enum halmac_ret_status (*halmac_mu_bfer_entry_init)(
1779                 struct halmac_adapter *halmac_adapter,
1780                 struct halmac_mu_bfer_init_para *mu_bfer_init);
1781         enum halmac_ret_status (*halmac_mu_bfee_entry_init)(
1782                 struct halmac_adapter *halmac_adapter,
1783                 struct halmac_mu_bfee_init_para *mu_bfee_init);
1784         enum halmac_ret_status (*halmac_su_bfer_entry_del)(
1785                 struct halmac_adapter *halmac_adapter, u8 userid);
1786         enum halmac_ret_status (*halmac_su_bfee_entry_del)(
1787                 struct halmac_adapter *halmac_adapter, u8 userid);
1788         enum halmac_ret_status (*halmac_mu_bfer_entry_del)(
1789                 struct halmac_adapter *halmac_adapter);
1790         enum halmac_ret_status (*halmac_mu_bfee_entry_del)(
1791                 struct halmac_adapter *halmac_adapter, u8 userid);
1792         enum halmac_ret_status (*halmac_add_ch_info)(
1793                 struct halmac_adapter *halmac_adapter,
1794                 struct halmac_ch_info *ch_info);
1795         enum halmac_ret_status (*halmac_add_extra_ch_info)(
1796                 struct halmac_adapter *halmac_adapter,
1797                 struct halmac_ch_extra_info *ch_extra_info);
1798         enum halmac_ret_status (*halmac_ctrl_ch_switch)(
1799                 struct halmac_adapter *halmac_adapter,
1800                 struct halmac_ch_switch_option *cs_option);
1801         enum halmac_ret_status (*halmac_p2pps)(
1802                 struct halmac_adapter *halmac_adapter,
1803                 struct halmac_p2pps *p2p_ps);
1804         enum halmac_ret_status (*halmac_clear_ch_info)(
1805                 struct halmac_adapter *halmac_adapter);
1806         enum halmac_ret_status (*halmac_send_general_info)(
1807                 struct halmac_adapter *halmac_adapter,
1808                 struct halmac_general_info *pg_general_info);
1809         enum halmac_ret_status (*halmac_start_iqk)(
1810                 struct halmac_adapter *halmac_adapter,
1811                 struct halmac_iqk_para_ *iqk_para);
1812         enum halmac_ret_status (*halmac_ctrl_pwr_tracking)(
1813                 struct halmac_adapter *halmac_adapter,
1814                 struct halmac_pwr_tracking_option *pwr_tracking_opt);
1815         enum halmac_ret_status (*halmac_psd)(
1816                 struct halmac_adapter *halmac_adapter, u16 start_psd,
1817                 u16 end_psd);
1818         enum halmac_ret_status (*halmac_cfg_tx_agg_align)(
1819                 struct halmac_adapter *halmac_adapter, u8 enable,
1820                 u16 align_size);
1821         enum halmac_ret_status (*halmac_query_status)(
1822                 struct halmac_adapter *halmac_adapter,
1823                 enum halmac_feature_id feature_id,
1824                 enum halmac_cmd_process_status *process_status, u8 *data,
1825                 u32 *size);
1826         enum halmac_ret_status (*halmac_reset_feature)(
1827                 struct halmac_adapter *halmac_adapter,
1828                 enum halmac_feature_id feature_id);
1829         enum halmac_ret_status (*halmac_check_fw_status)(
1830                 struct halmac_adapter *halmac_adapter, bool *fw_status);
1831         enum halmac_ret_status (*halmac_dump_fw_dmem)(
1832                 struct halmac_adapter *halmac_adapter, u8 *dmem, u32 *size);
1833         enum halmac_ret_status (*halmac_cfg_max_dl_size)(
1834                 struct halmac_adapter *halmac_adapter, u32 size);
1835         enum halmac_ret_status (*halmac_cfg_la_mode)(
1836                 struct halmac_adapter *halmac_adapter,
1837                 enum halmac_la_mode la_mode);
1838         enum halmac_ret_status (*halmac_cfg_rx_fifo_expanding_mode)(
1839                 struct halmac_adapter *halmac_adapter,
1840                 enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
1841         enum halmac_ret_status (*halmac_config_security)(
1842                 struct halmac_adapter *halmac_adapter,
1843                 struct halmac_security_setting *sec_setting);
1844         u8 (*halmac_get_used_cam_entry_num)(
1845                 struct halmac_adapter *halmac_adapter,
1846                 enum hal_security_type sec_type);
1847         enum halmac_ret_status (*halmac_write_cam)(
1848                 struct halmac_adapter *halmac_adapter, u32 entry_index,
1849                 struct halmac_cam_entry_info *cam_entry_info);
1850         enum halmac_ret_status (*halmac_read_cam_entry)(
1851                 struct halmac_adapter *halmac_adapter, u32 entry_index,
1852                 struct halmac_cam_entry_format *content);
1853         enum halmac_ret_status (*halmac_clear_cam_entry)(
1854                 struct halmac_adapter *halmac_adapter, u32 entry_index);
1855         enum halmac_ret_status (*halmac_get_hw_value)(
1856                 struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
1857                 void *pvalue);
1858         enum halmac_ret_status (*halmac_set_hw_value)(
1859                 struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
1860                 void *pvalue);
1861         enum halmac_ret_status (*halmac_cfg_drv_rsvd_pg_num)(
1862                 struct halmac_adapter *halmac_adapter,
1863                 enum halmac_drv_rsvd_pg_num pg_num);
1864         enum halmac_ret_status (*halmac_get_chip_version)(
1865                 struct halmac_adapter *halmac_adapter,
1866                 struct halmac_ver *version);
1867         enum halmac_ret_status (*halmac_chk_txdesc)(
1868                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1869                 u32 halmac_size);
1870         enum halmac_ret_status (*halmac_dl_drv_rsvd_page)(
1871                 struct halmac_adapter *halmac_adapter, u8 pg_offset,
1872                 u8 *hal_buf, u32 size);
1873         enum halmac_ret_status (*halmac_pcie_switch)(
1874                 struct halmac_adapter *halmac_adapter,
1875                 enum halmac_pcie_cfg pcie_cfg);
1876         enum halmac_ret_status (*halmac_phy_cfg)(
1877                 struct halmac_adapter *halmac_adapter,
1878                 enum halmac_intf_phy_platform platform);
1879         enum halmac_ret_status (*halmac_cfg_csi_rate)(
1880                 struct halmac_adapter *halmac_adapter, u8 rssi, u8 current_rate,
1881                 u8 fixrate_en, u8 *new_rate);
1882         enum halmac_ret_status (*halmac_sdio_cmd53_4byte)(
1883                 struct halmac_adapter *halmac_adapter,
1884                 enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
1885         enum halmac_ret_status (*halmac_interface_integration_tuning)(
1886                 struct halmac_adapter *halmac_adapter);
1887         enum halmac_ret_status (*halmac_txfifo_is_empty)(
1888                 struct halmac_adapter *halmac_adapter, u32 chk_num);
1889 };
1890
1891 #define HALMAC_GET_API(phalmac_adapter)                                        \
1892         ((struct halmac_api *)phalmac_adapter->halmac_api)
1893
1894 static inline enum halmac_ret_status
1895 halmac_adapter_validate(struct halmac_adapter *halmac_adapter)
1896 {
1897         if ((!halmac_adapter) ||
1898             (halmac_adapter->hal_adapter_backup != halmac_adapter))
1899                 return HALMAC_RET_ADAPTER_INVALID;
1900
1901         return HALMAC_RET_SUCCESS;
1902 }
1903
1904 static inline enum halmac_ret_status
1905 halmac_api_validate(struct halmac_adapter *halmac_adapter)
1906 {
1907         if (halmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT)
1908                 return HALMAC_RET_API_INVALID;
1909
1910         return HALMAC_RET_SUCCESS;
1911 }
1912
1913 static inline enum halmac_ret_status
1914 halmac_fw_validate(struct halmac_adapter *halmac_adapter)
1915 {
1916         if (halmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
1917             halmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
1918                 return HALMAC_RET_NO_DLFW;
1919
1920         return HALMAC_RET_SUCCESS;
1921 }
1922
1923 #endif