drivers/staging/rtlwifi/halmac/halmac_type.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25 #ifndef _HALMAC_TYPE_H_
  26 #define _HALMAC_TYPE_H_
  27
  28 #include "halmac_2_platform.h"
  29 #include "halmac_fw_info.h"
  30 #include "halmac_intf_phy_cmd.h"
  31
  32 #define HALMAC_SCAN_CH_NUM_MAX 28
  33 #define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */
  34 #define HALMAC_PHY_PARAMETER_SIZE 12
  35 #define HALMAC_PHY_PARAMETER_MAX_NUM 128
  36 #define HALMAC_MAX_SSID_LEN 32
  37 #define HALMAC_SUPPORT_NLO_NUM 16
  38 #define HALMAC_SUPPORT_PROBE_REQ_NUM 8
  39 #define HALMC_DDMA_POLLING_COUNT 1000
  40 #define API_ARRAY_SIZE 32
  41
  42 /* platform api */
  43 #define PLATFORM_SDIO_CMD52_READ                                               \
  44         halmac_adapter->halmac_platform_api->SDIO_CMD52_READ
  45 #define PLATFORM_SDIO_CMD53_READ_8                                             \
  46         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_8
  47 #define PLATFORM_SDIO_CMD53_READ_16                                            \
  48         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_16
  49 #define PLATFORM_SDIO_CMD53_READ_32                                            \
  50         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_32
  51 #define PLATFORM_SDIO_CMD53_READ_N                                             \
  52         halmac_adapter->halmac_platform_api->SDIO_CMD53_READ_N
  53 #define PLATFORM_SDIO_CMD52_WRITE                                              \
  54         halmac_adapter->halmac_platform_api->SDIO_CMD52_WRITE
  55 #define PLATFORM_SDIO_CMD53_WRITE_8                                            \
  56         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_8
  57 #define PLATFORM_SDIO_CMD53_WRITE_16                                           \
  58         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_16
  59 #define PLATFORM_SDIO_CMD53_WRITE_32                                           \
  60         halmac_adapter->halmac_platform_api->SDIO_CMD53_WRITE_32
  61
  62 #define PLATFORM_REG_READ_8 halmac_adapter->halmac_platform_api->REG_READ_8
  63 #define PLATFORM_REG_READ_16 halmac_adapter->halmac_platform_api->REG_READ_16
  64 #define PLATFORM_REG_READ_32 halmac_adapter->halmac_platform_api->REG_READ_32
  65 #define PLATFORM_REG_WRITE_8 halmac_adapter->halmac_platform_api->REG_WRITE_8
  66 #define PLATFORM_REG_WRITE_16 halmac_adapter->halmac_platform_api->REG_WRITE_16
  67 #define PLATFORM_REG_WRITE_32 halmac_adapter->halmac_platform_api->REG_WRITE_32
  68
  69 #define PLATFORM_SEND_RSVD_PAGE                                                \
  70         halmac_adapter->halmac_platform_api->SEND_RSVD_PAGE
  71 #define PLATFORM_SEND_H2C_PKT halmac_adapter->halmac_platform_api->SEND_H2C_PKT
  72
  73 #define PLATFORM_EVENT_INDICATION                                              \
  74         halmac_adapter->halmac_platform_api->EVENT_INDICATION
  75
  76 #define HALMAC_RT_TRACE(drv_adapter, comp, level, fmt, ...)                    \
  77         RT_TRACE(drv_adapter, COMP_HALMAC, level, fmt, ##__VA_ARGS__)
  78
  79 #define HALMAC_REG_READ_8 halmac_api->halmac_reg_read_8
  80 #define HALMAC_REG_READ_16 halmac_api->halmac_reg_read_16
  81 #define HALMAC_REG_READ_32 halmac_api->halmac_reg_read_32
  82 #define HALMAC_REG_WRITE_8 halmac_api->halmac_reg_write_8
  83 #define HALMAC_REG_WRITE_16 halmac_api->halmac_reg_write_16
  84 #define HALMAC_REG_WRITE_32 halmac_api->halmac_reg_write_32
  85 #define HALMAC_REG_SDIO_CMD53_READ_N halmac_api->halmac_reg_sdio_cmd53_read_n
  86
  87 /* Swap Little-endian <-> Big-endia*/
  88
  89 /*1->Little endian 0->Big endian*/
  90 #if HALMAC_SYSTEM_ENDIAN
  91 #else
  92 #endif
  93
  94 #define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1)
  95 #define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
  96
  97 /* HALMAC API return status*/
  98 enum halmac_ret_status {
  99         HALMAC_RET_SUCCESS = 0x00,
 100         HALMAC_RET_SUCCESS_ENQUEUE = 0x01,
 101         HALMAC_RET_PLATFORM_API_NULL = 0x02,
 102         HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03,
 103         HALMAC_RET_MALLOC_FAIL = 0x04,
 104         HALMAC_RET_ADAPTER_INVALID = 0x05,
 105         HALMAC_RET_ITF_INCORRECT = 0x06,
 106         HALMAC_RET_DLFW_FAIL = 0x07,
 107         HALMAC_RET_PORT_NOT_SUPPORT = 0x08,
 108         HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09,
 109         HALMAC_RET_INIT_LLT_FAIL = 0x0A,
 110         HALMAC_RET_POWER_STATE_INVALID = 0x0B,
 111         HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C,
 112         HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D,
 113         HALMAC_RET_EFUSE_R_FAIL = 0x0E,
 114         HALMAC_RET_EFUSE_W_FAIL = 0x0F,
 115         HALMAC_RET_H2C_SW_RES_FAIL = 0x10,
 116         HALMAC_RET_SEND_H2C_FAIL = 0x11,
 117         HALMAC_RET_PARA_NOT_SUPPORT = 0x12,
 118         HALMAC_RET_PLATFORM_API_INCORRECT = 0x13,
 119         HALMAC_RET_ENDIAN_ERR = 0x14,
 120         HALMAC_RET_FW_SIZE_ERR = 0x15,
 121         HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16,
 122         HALMAC_RET_FAIL = 0x17,
 123         HALMAC_RET_CHANGE_PS_FAIL = 0x18,
 124         HALMAC_RET_CFG_PARA_FAIL = 0x19,
 125         HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A,
 126         HALMAC_RET_SCAN_FAIL = 0x1B,
 127         HALMAC_RET_STOP_SCAN_FAIL = 0x1C,
 128         HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D,
 129         HALMAC_RET_POWER_ON_FAIL = 0x1E,
 130         HALMAC_RET_POWER_OFF_FAIL = 0x1F,
 131         HALMAC_RET_RX_AGG_MODE_FAIL = 0x20,
 132         HALMAC_RET_DATA_BUF_NULL = 0x21,
 133         HALMAC_RET_DATA_SIZE_INCORRECT = 0x22,
 134         HALMAC_RET_QSEL_INCORRECT = 0x23,
 135         HALMAC_RET_DMA_MAP_INCORRECT = 0x24,
 136         HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25,
 137         HALMAC_RET_DDMA_FAIL = 0x26,
 138         HALMAC_RET_FW_CHECKSUM_FAIL = 0x27,
 139         HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28,
 140         HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29,
 141         HALMAC_RET_WRITE_DATA_FAIL = 0x2A,
 142         HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B,
 143         HALMAC_RET_NULL_POINTER = 0x2C,
 144         HALMAC_RET_PROBE_NOT_FOUND = 0x2D,
 145         HALMAC_RET_FW_NO_MEMORY = 0x2E,
 146         HALMAC_RET_H2C_STATUS_ERR = 0x2F,
 147         HALMAC_RET_GET_H2C_SPACE_ERR = 0x30,
 148         HALMAC_RET_H2C_SPACE_FULL = 0x31,
 149         HALMAC_RET_DATAPACK_NO_FOUND = 0x32,
 150         HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33,
 151         HALMAC_RET_TX_DMA_ERR = 0x34,
 152         HALMAC_RET_RX_DMA_ERR = 0x35,
 153         HALMAC_RET_CHIP_NOT_SUPPORT = 0x36,
 154         HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37,
 155         HALMAC_RET_CH_SW_SEQ_WRONG = 0x38,
 156         HALMAC_RET_CH_SW_NO_BUF = 0x39,
 157         HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A,
 158         HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B,
 159         HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C,
 160         HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D,
 161         HALMAC_RET_STATE_INCORRECT = 0x3E,
 162         HALMAC_RET_H2C_BUSY = 0x3F,
 163         HALMAC_RET_INVALID_FEATURE_ID = 0x40,
 164         HALMAC_RET_BUFFER_TOO_SMALL = 0x41,
 165         HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42,
 166         HALMAC_RET_BUSY_STATE = 0x43,
 167         HALMAC_RET_ERROR_STATE = 0x44,
 168         HALMAC_RET_API_INVALID = 0x45,
 169         HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46,
 170         HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47,
 171         HALMAC_RET_EEPROM_PARSING_FAIL = 0x48,
 172         HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49,
 173         HALMAC_RET_WRONG_ARGUMENT = 0x4A,
 174         HALMAC_RET_NOT_SUPPORT = 0x4B,
 175         HALMAC_RET_C2H_NOT_HANDLED = 0x4C,
 176         HALMAC_RET_PARA_SENDING = 0x4D,
 177         HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E,
 178         HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F,
 179         HALMAC_RET_SWITCH_CASE_ERROR = 0x50,
 180         HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51,
 181         HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52,
 182         HALMAC_RET_USB_MODE_UNCHANGE = 0x53,
 183         HALMAC_RET_NO_DLFW = 0x54,
 184         HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55,
 185         HALMAC_RET_BIP_NO_SUPPORT = 0x56,
 186         HALMAC_RET_ENTRY_INDEX_ERROR = 0x57,
 187         HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58,
 188         HALMAC_RET_DRV_DL_ERR = 0x59,
 189         HALMAC_RET_OQT_NOT_ENOUGH = 0x5A,
 190         HALMAC_RET_PWR_UNCHANGE = 0x5B,
 191         HALMAC_RET_FW_NO_SUPPORT = 0x60,
 192         HALMAC_RET_TXFIFO_NO_EMPTY = 0x61,
 193 };
 194
 195 enum halmac_mac_clock_hw_def {
 196         HALMAC_MAC_CLOCK_HW_DEF_80M = 0,
 197         HALMAC_MAC_CLOCK_HW_DEF_40M = 1,
 198         HALMAC_MAC_CLOCK_HW_DEF_20M = 2,
 199 };
 200
 201 /* Rx aggregation parameters */
 202 enum halmac_normal_rxagg_th_to {
 203         HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF,
 204         HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01,
 205 };
 206
 207 enum halmac_loopback_rxagg_th_to {
 208         HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF,
 209         HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01,
 210 };
 211
 212 /* Chip ID*/
 213 enum halmac_chip_id {
 214         HALMAC_CHIP_ID_8822B = 0,
 215         HALMAC_CHIP_ID_8821C = 1,
 216         HALMAC_CHIP_ID_8814B = 2,
 217         HALMAC_CHIP_ID_8197F = 3,
 218         HALMAC_CHIP_ID_UNDEFINE = 0x7F,
 219 };
 220
 221 enum halmac_chip_id_hw_def {
 222         HALMAC_CHIP_ID_HW_DEF_8723A = 0x01,
 223         HALMAC_CHIP_ID_HW_DEF_8188E = 0x02,
 224         HALMAC_CHIP_ID_HW_DEF_8881A = 0x03,
 225         HALMAC_CHIP_ID_HW_DEF_8812A = 0x04,
 226         HALMAC_CHIP_ID_HW_DEF_8821A = 0x05,
 227         HALMAC_CHIP_ID_HW_DEF_8723B = 0x06,
 228         HALMAC_CHIP_ID_HW_DEF_8192E = 0x07,
 229         HALMAC_CHIP_ID_HW_DEF_8814A = 0x08,
 230         HALMAC_CHIP_ID_HW_DEF_8821C = 0x09,
 231         HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A,
 232         HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B,
 233         HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C,
 234         HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D,
 235         HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E,
 236         HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F,
 237         HALMAC_CHIP_ID_HW_DEF_8814B = 0x10,
 238         HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F,
 239         HALMAC_CHIP_ID_HW_DEF_PS = 0xEA,
 240 };
 241
 242 /* Chip Version*/
 243 enum halmac_chip_ver {
 244         HALMAC_CHIP_VER_A_CUT = 0x00,
 245         HALMAC_CHIP_VER_B_CUT = 0x01,
 246         HALMAC_CHIP_VER_C_CUT = 0x02,
 247         HALMAC_CHIP_VER_D_CUT = 0x03,
 248         HALMAC_CHIP_VER_E_CUT = 0x04,
 249         HALMAC_CHIP_VER_F_CUT = 0x05,
 250         HALMAC_CHIP_VER_TEST = 0xFF,
 251         HALMAC_CHIP_VER_UNDEFINE = 0x7FFF,
 252 };
 253
 254 /* Network type select */
 255 enum halmac_network_type_select {
 256         HALMAC_NETWORK_NO_LINK = 0,
 257         HALMAC_NETWORK_ADHOC = 1,
 258         HALMAC_NETWORK_INFRASTRUCTURE = 2,
 259         HALMAC_NETWORK_AP = 3,
 260         HALMAC_NETWORK_UNDEFINE = 0x7F,
 261 };
 262
 263 /* Transfer mode select */
 264 enum halmac_trnsfer_mode_select {
 265         HALMAC_TRNSFER_NORMAL = 0x0,
 266         HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB,
 267         HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3,
 268         HALMAC_TRNSFER_UNDEFINE = 0x7F,
 269 };
 270
 271 /* Queue select */
 272 enum halmac_dma_mapping {
 273         HALMAC_DMA_MAPPING_EXTRA = 0,
 274         HALMAC_DMA_MAPPING_LOW = 1,
 275         HALMAC_DMA_MAPPING_NORMAL = 2,
 276         HALMAC_DMA_MAPPING_HIGH = 3,
 277         HALMAC_DMA_MAPPING_UNDEFINE = 0x7F,
 278 };
 279
 280 #define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH
 281 #define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL
 282 #define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW
 283 #define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA
 284 #define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE
 285
 286 /* TXDESC queue select TID */
 287 enum halmac_txdesc_queue_tid {
 288         HALMAC_TXDESC_QSEL_TID0 = 0,
 289         HALMAC_TXDESC_QSEL_TID1 = 1,
 290         HALMAC_TXDESC_QSEL_TID2 = 2,
 291         HALMAC_TXDESC_QSEL_TID3 = 3,
 292         HALMAC_TXDESC_QSEL_TID4 = 4,
 293         HALMAC_TXDESC_QSEL_TID5 = 5,
 294         HALMAC_TXDESC_QSEL_TID6 = 6,
 295         HALMAC_TXDESC_QSEL_TID7 = 7,
 296         HALMAC_TXDESC_QSEL_TID8 = 8,
 297         HALMAC_TXDESC_QSEL_TID9 = 9,
 298         HALMAC_TXDESC_QSEL_TIDA = 10,
 299         HALMAC_TXDESC_QSEL_TIDB = 11,
 300         HALMAC_TXDESC_QSEL_TIDC = 12,
 301         HALMAC_TXDESC_QSEL_TIDD = 13,
 302         HALMAC_TXDESC_QSEL_TIDE = 14,
 303         HALMAC_TXDESC_QSEL_TIDF = 15,
 304
 305         HALMAC_TXDESC_QSEL_BEACON = 0x10,
 306         HALMAC_TXDESC_QSEL_HIGH = 0x11,
 307         HALMAC_TXDESC_QSEL_MGT = 0x12,
 308         HALMAC_TXDESC_QSEL_H2C_CMD = 0x13,
 309
 310         HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F,
 311 };
 312
 313 enum halmac_ptcl_queue {
 314         HALMAC_PTCL_QUEUE_VO = 0x0,
 315         HALMAC_PTCL_QUEUE_VI = 0x1,
 316         HALMAC_PTCL_QUEUE_BE = 0x2,
 317         HALMAC_PTCL_QUEUE_BK = 0x3,
 318         HALMAC_PTCL_QUEUE_MG = 0x4,
 319         HALMAC_PTCL_QUEUE_HI = 0x5,
 320         HALMAC_PTCL_QUEUE_NUM = 0x6,
 321         HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F,
 322 };
 323
 324 enum halmac_queue_select {
 325         HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6,
 326         HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4,
 327         HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0,
 328         HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1,
 329         HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7,
 330         HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5,
 331         HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3,
 332         HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2,
 333         HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON,
 334         HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH,
 335         HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT,
 336         HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD,
 337         HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F,
 338 };
 339
 340 /* USB burst size */
 341 enum halmac_usb_burst_size {
 342         HALMAC_USB_BURST_SIZE_3_0 = 0x0,
 343         HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1,
 344         HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2,
 345         HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3,
 346         HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F,
 347 };
 348
 349 /* HAL API  function parameters*/
 350 enum halmac_interface {
 351         HALMAC_INTERFACE_PCIE = 0x0,
 352         HALMAC_INTERFACE_USB = 0x1,
 353         HALMAC_INTERFACE_SDIO = 0x2,
 354         HALMAC_INTERFACE_AXI = 0x3,
 355         HALMAC_INTERFACE_UNDEFINE = 0x7F,
 356 };
 357
 358 enum halmac_rx_agg_mode {
 359         HALMAC_RX_AGG_MODE_NONE = 0x0,
 360         HALMAC_RX_AGG_MODE_DMA = 0x1,
 361         HALMAC_RX_AGG_MODE_USB = 0x2,
 362         HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F,
 363 };
 364
 365 struct halmac_rxagg_th {
 366         u8 drv_define;
 367         u8 timeout;
 368         u8 size;
 369 };
 370
 371 struct halmac_rxagg_cfg {
 372         enum halmac_rx_agg_mode mode;
 373         struct halmac_rxagg_th threshold;
 374 };
 375
 376 enum halmac_mac_power {
 377         HALMAC_MAC_POWER_OFF = 0x0,
 378         HALMAC_MAC_POWER_ON = 0x1,
 379         HALMAC_MAC_POWER_UNDEFINE = 0x7F,
 380 };
 381
 382 enum halmac_ps_state {
 383         HALMAC_PS_STATE_ACT = 0x0,
 384         HALMAC_PS_STATE_LPS = 0x1,
 385         HALMAC_PS_STATE_IPS = 0x2,
 386         HALMAC_PS_STATE_UNDEFINE = 0x7F,
 387 };
 388
 389 enum halmac_trx_mode {
 390         HALMAC_TRX_MODE_NORMAL = 0x0,
 391         HALMAC_TRX_MODE_TRXSHARE = 0x1,
 392         HALMAC_TRX_MODE_WMM = 0x2,
 393         HALMAC_TRX_MODE_P2P = 0x3,
 394         HALMAC_TRX_MODE_LOOPBACK = 0x4,
 395         HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5,
 396         HALMAC_TRX_MODE_MAX = 0x6,
 397         HALMAC_TRX_MODE_WMM_LINUX = 0x7E,
 398         HALMAC_TRX_MODE_UNDEFINE = 0x7F,
 399 };
 400
 401 enum halmac_wireless_mode {
 402         HALMAC_WIRELESS_MODE_B = 0x0,
 403         HALMAC_WIRELESS_MODE_G = 0x1,
 404         HALMAC_WIRELESS_MODE_N = 0x2,
 405         HALMAC_WIRELESS_MODE_AC = 0x3,
 406         HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F,
 407 };
 408
 409 enum halmac_bw {
 410         HALMAC_BW_20 = 0x00,
 411         HALMAC_BW_40 = 0x01,
 412         HALMAC_BW_80 = 0x02,
 413         HALMAC_BW_160 = 0x03,
 414         HALMAC_BW_5 = 0x04,
 415         HALMAC_BW_10 = 0x05,
 416         HALMAC_BW_MAX = 0x06,
 417         HALMAC_BW_UNDEFINE = 0x7F,
 418 };
 419
 420 enum halmac_efuse_read_cfg {
 421         HALMAC_EFUSE_R_AUTO = 0x00,
 422         HALMAC_EFUSE_R_DRV = 0x01,
 423         HALMAC_EFUSE_R_FW = 0x02,
 424         HALMAC_EFUSE_R_UNDEFINE = 0x7F,
 425 };
 426
 427 enum halmac_dlfw_mem {
 428         HALMAC_DLFW_MEM_EMEM = 0x00,
 429         HALMAC_DLFW_MEM_UNDEFINE = 0x7F,
 430 };
 431
 432 struct halmac_tx_desc {
 433         u32 dword0;
 434         u32 dword1;
 435         u32 dword2;
 436         u32 dword3;
 437         u32 dword4;
 438         u32 dword5;
 439         u32 dword6;
 440         u32 dword7;
 441         u32 dword8;
 442         u32 dword9;
 443         u32 dword10;
 444         u32 dword11;
 445 };
 446
 447 struct halmac_rx_desc {
 448         u32 dword0;
 449         u32 dword1;
 450         u32 dword2;
 451         u32 dword3;
 452         u32 dword4;
 453         u32 dword5;
 454 };
 455
 456 struct halmac_fwlps_option {
 457         u8 mode;
 458         u8 clk_request;
 459         u8 rlbm;
 460         u8 smart_ps;
 461         u8 awake_interval;
 462         u8 all_queue_uapsd;
 463         u8 pwr_state;
 464         u8 low_pwr_rx_beacon;
 465         u8 ant_auto_switch;
 466         u8 ps_allow_bt_high_priority;
 467         u8 protect_bcn;
 468         u8 silence_period;
 469         u8 fast_bt_connect;
 470         u8 two_antenna_en;
 471         u8 adopt_user_setting;
 472         u8 drv_bcn_early_shift;
 473         bool enter_32K;
 474 };
 475
 476 struct halmac_fwips_option {
 477         u8 adopt_user_setting;
 478 };
 479
 480 struct halmac_wowlan_option {
 481         u8 adopt_user_setting;
 482 };
 483
 484 struct halmac_bcn_ie_info {
 485         u8 func_en;
 486         u8 size_th;
 487         u8 timeout;
 488         u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE];
 489 };
 490
 491 enum halmac_reg_type {
 492         HALMAC_REG_TYPE_MAC = 0x0,
 493         HALMAC_REG_TYPE_BB = 0x1,
 494         HALMAC_REG_TYPE_RF = 0x2,
 495         HALMAC_REG_TYPE_UNDEFINE = 0x7F,
 496 };
 497
 498 enum halmac_parameter_cmd {
 499         /* HALMAC_PARAMETER_CMD_LLT                             = 0x1, */
 500         /* HALMAC_PARAMETER_CMD_R_EFUSE                 = 0x2, */
 501         /* HALMAC_PARAMETER_CMD_EFUSE_PATCH     = 0x3, */
 502         HALMAC_PARAMETER_CMD_MAC_W8 = 0x4,
 503         HALMAC_PARAMETER_CMD_MAC_W16 = 0x5,
 504         HALMAC_PARAMETER_CMD_MAC_W32 = 0x6,
 505         HALMAC_PARAMETER_CMD_RF_W = 0x7,
 506         HALMAC_PARAMETER_CMD_BB_W8 = 0x8,
 507         HALMAC_PARAMETER_CMD_BB_W16 = 0x9,
 508         HALMAC_PARAMETER_CMD_BB_W32 = 0XA,
 509         HALMAC_PARAMETER_CMD_DELAY_US = 0X10,
 510         HALMAC_PARAMETER_CMD_DELAY_MS = 0X11,
 511         HALMAC_PARAMETER_CMD_END = 0XFF,
 512 };
 513
 514 union halmac_parameter_content {
 515         struct _MAC_REG_W {
 516                 u32 value;
 517                 u32 msk;
 518                 u16 offset;
 519                 u8 msk_en;
 520         } MAC_REG_W;
 521         struct _BB_REG_W {
 522                 u32 value;
 523                 u32 msk;
 524                 u16 offset;
 525                 u8 msk_en;
 526         } BB_REG_W;
 527         struct _RF_REG_W {
 528                 u32 value;
 529                 u32 msk;
 530                 u8 offset;
 531                 u8 msk_en;
 532                 u8 rf_path;
 533         } RF_REG_W;
 534         struct _DELAY_TIME {
 535                 u32 rsvd1;
 536                 u32 rsvd2;
 537                 u16 delay_time;
 538                 u8 rsvd3;
 539         } DELAY_TIME;
 540 };
 541
 542 struct halmac_phy_parameter_info {
 543         enum halmac_parameter_cmd cmd_id;
 544         union halmac_parameter_content content;
 545 };
 546
 547 struct halmac_h2c_info {
 548         u16 h2c_seq_num; /* H2C sequence number */
 549         u8 in_use; /* 0 : empty 1 : used */
 550         enum halmac_h2c_return_code status;
 551 };
 552
 553 struct halmac_pg_efuse_info {
 554         u8 *efuse_map;
 555         u32 efuse_map_size;
 556         u8 *efuse_mask;
 557         u32 efuse_mask_size;
 558 };
 559
 560 struct halmac_txagg_buff_info {
 561         u8 *tx_agg_buf;
 562         u8 *curr_pkt_buf;
 563         u32 avai_buf_size;
 564         u32 total_pkt_size;
 565         u8 agg_num;
 566 };
 567
 568 struct halmac_config_para_info {
 569         u32 para_buf_size; /* Parameter buffer size */
 570         u8 *cfg_para_buf; /* Buffer for config parameter */
 571         u8 *para_buf_w; /* Write pointer of the parameter buffer */
 572         u32 para_num; /* Parameter numbers in parameter buffer */
 573         u32 avai_para_buf_size; /* Free size of parameter buffer */
 574         u32 offset_accumulation;
 575         u32 value_accumulation;
 576         enum halmac_data_type data_type; /*DataType which is passed to FW*/
 577         u8 datapack_segment; /*DataPack Segment, from segment0...*/
 578         bool full_fifo_mode; /* Used full tx fifo to save cfg parameter */
 579 };
 580
 581 struct halmac_hw_config_info {
 582         u32 efuse_size; /* Record efuse size */
 583         u32 eeprom_size; /* Record eeprom size */
 584         u32 bt_efuse_size; /* Record BT efuse size */
 585         u32 tx_fifo_size; /* Record tx fifo size */
 586         u32 rx_fifo_size; /* Record rx fifo size */
 587         u8 txdesc_size; /* Record tx desc size */
 588         u8 rxdesc_size; /* Record rx desc size */
 589         u32 page_size; /* Record page size */
 590         u16 tx_align_size;
 591         u8 page_size_2_power;
 592         u8 cam_entry_num; /* Record CAM entry number */
 593 };
 594
 595 struct halmac_sdio_free_space {
 596         u16 high_queue_number; /* Free space of HIQ */
 597         u16 normal_queue_number; /* Free space of MIDQ */
 598         u16 low_queue_number; /* Free space of LOWQ */
 599         u16 public_queue_number; /* Free space of PUBQ */
 600         u16 extra_queue_number; /* Free space of EXBQ */
 601         u8 ac_oqt_number;
 602         u8 non_ac_oqt_number;
 603         u8 ac_empty;
 604 };
 605
 606 enum hal_fifo_sel {
 607         HAL_FIFO_SEL_TX,
 608         HAL_FIFO_SEL_RX,
 609         HAL_FIFO_SEL_RSVD_PAGE,
 610         HAL_FIFO_SEL_REPORT,
 611         HAL_FIFO_SEL_LLT,
 612 };
 613
 614 enum halmac_drv_info {
 615         HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */
 616         HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */
 617         HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info appended */
 618         HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended */
 619         HALMAC_DRV_INFO_UNDEFINE,
 620 };
 621
 622 struct halmac_bt_coex_cmd {
 623         u8 element_id;
 624         u8 op_code;
 625         u8 op_code_ver;
 626         u8 req_num;
 627         u8 data0;
 628         u8 data1;
 629         u8 data2;
 630         u8 data3;
 631         u8 data4;
 632 };
 633
 634 enum halmac_pri_ch_idx {
 635         HALMAC_CH_IDX_UNDEFINE = 0,
 636         HALMAC_CH_IDX_1 = 1,
 637         HALMAC_CH_IDX_2 = 2,
 638         HALMAC_CH_IDX_3 = 3,
 639         HALMAC_CH_IDX_4 = 4,
 640         HALMAC_CH_IDX_MAX = 5,
 641 };
 642
 643 struct halmac_ch_info {
 644         enum halmac_cs_action_id action_id;
 645         enum halmac_bw bw;
 646         enum halmac_pri_ch_idx pri_ch_idx;
 647         u8 channel;
 648         u8 timeout;
 649         u8 extra_info;
 650 };
 651
 652 struct halmac_ch_extra_info {
 653         u8 extra_info;
 654         enum halmac_cs_extra_action_id extra_action_id;
 655         u8 extra_info_size;
 656         u8 *extra_info_data;
 657 };
 658
 659 enum halmac_cs_periodic_option {
 660         HALMAC_CS_PERIODIC_NONE,
 661         HALMAC_CS_PERIODIC_NORMAL,
 662         HALMAC_CS_PERIODIC_2_PHASE,
 663         HALMAC_CS_PERIODIC_SEAMLESS,
 664 };
 665
 666 struct halmac_ch_switch_option {
 667         enum halmac_bw dest_bw;
 668         enum halmac_cs_periodic_option periodic_option;
 669         enum halmac_pri_ch_idx dest_pri_ch_idx;
 670         /* u32 tsf_high; */
 671         u32 tsf_low;
 672         bool switch_en;
 673         u8 dest_ch_en;
 674         u8 absolute_time_en;
 675         u8 dest_ch;
 676         u8 normal_period;
 677         u8 normal_cycle;
 678         u8 phase_2_period;
 679 };
 680
 681 struct halmac_fw_version {
 682         u16 version;
 683         u8 sub_version;
 684         u8 sub_index;
 685         u16 h2c_version;
 686 };
 687
 688 enum halmac_rf_type {
 689         HALMAC_RF_1T2R = 0,
 690         HALMAC_RF_2T4R = 1,
 691         HALMAC_RF_2T2R = 2,
 692         HALMAC_RF_2T3R = 3,
 693         HALMAC_RF_1T1R = 4,
 694         HALMAC_RF_2T2R_GREEN = 5,
 695         HALMAC_RF_3T3R = 6,
 696         HALMAC_RF_3T4R = 7,
 697         HALMAC_RF_4T4R = 8,
 698         HALMAC_RF_MAX_TYPE = 0xF,
 699 };
 700
 701 struct halmac_general_info {
 702         u8 rfe_type;
 703         enum halmac_rf_type rf_type;
 704 };
 705
 706 struct halmac_pwr_tracking_para {
 707         u8 enable;
 708         u8 tx_pwr_index;
 709         u8 pwr_tracking_offset_value;
 710         u8 tssi_value;
 711 };
 712
 713 struct halmac_pwr_tracking_option {
 714         u8 type;
 715         u8 bbswing_index;
 716         struct halmac_pwr_tracking_para
 717                 pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */
 718 };
 719
 720 struct halmac_nlo_cfg {
 721         u8 num_of_ssid;
 722         u8 num_of_hidden_ap;
 723         u8 rsvd[2];
 724         u32 pattern_check;
 725         u32 rsvd1;
 726         u32 rsvd2;
 727         u8 ssid_len[HALMAC_SUPPORT_NLO_NUM];
 728         u8 chiper_type[HALMAC_SUPPORT_NLO_NUM];
 729         u8 rsvd3[HALMAC_SUPPORT_NLO_NUM];
 730         u8 loc_probe_req[HALMAC_SUPPORT_PROBE_REQ_NUM];
 731         u8 rsvd4[56];
 732         u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN];
 733 };
 734
 735 enum halmac_data_rate {
 736         HALMAC_CCK1,
 737         HALMAC_CCK2,
 738         HALMAC_CCK5_5,
 739         HALMAC_CCK11,
 740         HALMAC_OFDM6,
 741         HALMAC_OFDM9,
 742         HALMAC_OFDM12,
 743         HALMAC_OFDM18,
 744         HALMAC_OFDM24,
 745         HALMAC_OFDM36,
 746         HALMAC_OFDM48,
 747         HALMAC_OFDM54,
 748         HALMAC_MCS0,
 749         HALMAC_MCS1,
 750         HALMAC_MCS2,
 751         HALMAC_MCS3,
 752         HALMAC_MCS4,
 753         HALMAC_MCS5,
 754         HALMAC_MCS6,
 755         HALMAC_MCS7,
 756         HALMAC_MCS8,
 757         HALMAC_MCS9,
 758         HALMAC_MCS10,
 759         HALMAC_MCS11,
 760         HALMAC_MCS12,
 761         HALMAC_MCS13,
 762         HALMAC_MCS14,
 763         HALMAC_MCS15,
 764         HALMAC_MCS16,
 765         HALMAC_MCS17,
 766         HALMAC_MCS18,
 767         HALMAC_MCS19,
 768         HALMAC_MCS20,
 769         HALMAC_MCS21,
 770         HALMAC_MCS22,
 771         HALMAC_MCS23,
 772         HALMAC_MCS24,
 773         HALMAC_MCS25,
 774         HALMAC_MCS26,
 775         HALMAC_MCS27,
 776         HALMAC_MCS28,
 777         HALMAC_MCS29,
 778         HALMAC_MCS30,
 779         HALMAC_MCS31,
 780         HALMAC_VHT_NSS1_MCS0,
 781         HALMAC_VHT_NSS1_MCS1,
 782         HALMAC_VHT_NSS1_MCS2,
 783         HALMAC_VHT_NSS1_MCS3,
 784         HALMAC_VHT_NSS1_MCS4,
 785         HALMAC_VHT_NSS1_MCS5,
 786         HALMAC_VHT_NSS1_MCS6,
 787         HALMAC_VHT_NSS1_MCS7,
 788         HALMAC_VHT_NSS1_MCS8,
 789         HALMAC_VHT_NSS1_MCS9,
 790         HALMAC_VHT_NSS2_MCS0,
 791         HALMAC_VHT_NSS2_MCS1,
 792         HALMAC_VHT_NSS2_MCS2,
 793         HALMAC_VHT_NSS2_MCS3,
 794         HALMAC_VHT_NSS2_MCS4,
 795         HALMAC_VHT_NSS2_MCS5,
 796         HALMAC_VHT_NSS2_MCS6,
 797         HALMAC_VHT_NSS2_MCS7,
 798         HALMAC_VHT_NSS2_MCS8,
 799         HALMAC_VHT_NSS2_MCS9,
 800         HALMAC_VHT_NSS3_MCS0,
 801         HALMAC_VHT_NSS3_MCS1,
 802         HALMAC_VHT_NSS3_MCS2,
 803         HALMAC_VHT_NSS3_MCS3,
 804         HALMAC_VHT_NSS3_MCS4,
 805         HALMAC_VHT_NSS3_MCS5,
 806         HALMAC_VHT_NSS3_MCS6,
 807         HALMAC_VHT_NSS3_MCS7,
 808         HALMAC_VHT_NSS3_MCS8,
 809         HALMAC_VHT_NSS3_MCS9,
 810         HALMAC_VHT_NSS4_MCS0,
 811         HALMAC_VHT_NSS4_MCS1,
 812         HALMAC_VHT_NSS4_MCS2,
 813         HALMAC_VHT_NSS4_MCS3,
 814         HALMAC_VHT_NSS4_MCS4,
 815         HALMAC_VHT_NSS4_MCS5,
 816         HALMAC_VHT_NSS4_MCS6,
 817         HALMAC_VHT_NSS4_MCS7,
 818         HALMAC_VHT_NSS4_MCS8,
 819         HALMAC_VHT_NSS4_MCS9
 820 };
 821
 822 enum halmac_rf_path {
 823         HALMAC_RF_PATH_A,
 824         HALMAC_RF_PATH_B,
 825         HALMAC_RF_PATH_C,
 826         HALMAC_RF_PATH_D
 827 };
 828
 829 enum halmac_snd_pkt_sel {
 830         HALMAC_UNI_NDPA,
 831         HALMAC_BMC_NDPA,
 832         HALMAC_NON_FINAL_BFRPRPOLL,
 833         HALMAC_FINAL_BFRPTPOLL,
 834 };
 835
 836 enum hal_security_type {
 837         HAL_SECURITY_TYPE_NONE = 0,
 838         HAL_SECURITY_TYPE_WEP40 = 1,
 839         HAL_SECURITY_TYPE_WEP104 = 2,
 840         HAL_SECURITY_TYPE_TKIP = 3,
 841         HAL_SECURITY_TYPE_AES128 = 4,
 842         HAL_SECURITY_TYPE_WAPI = 5,
 843         HAL_SECURITY_TYPE_AES256 = 6,
 844         HAL_SECURITY_TYPE_GCMP128 = 7,
 845         HAL_SECURITY_TYPE_GCMP256 = 8,
 846         HAL_SECURITY_TYPE_GCMSMS4 = 9,
 847         HAL_SECURITY_TYPE_BIP = 10,
 848         HAL_SECURITY_TYPE_UNDEFINE = 0x7F,
 849 };
 850
 851 enum hal_intf_phy {
 852         HAL_INTF_PHY_USB2 = 0,
 853         HAL_INTF_PHY_USB3 = 1,
 854         HAL_INTF_PHY_PCIE_GEN1 = 2,
 855         HAL_INTF_PHY_PCIE_GEN2 = 3,
 856         HAL_INTF_PHY_UNDEFINE = 0x7F,
 857 };
 858
 859 enum halmac_dbg_msg_info {
 860         HALMAC_DBG_ERR,
 861         HALMAC_DBG_WARN,
 862         HALMAC_DBG_TRACE,
 863 };
 864
 865 enum halmac_dbg_msg_type {
 866         HALMAC_MSG_INIT,
 867         HALMAC_MSG_EFUSE,
 868         HALMAC_MSG_FW,
 869         HALMAC_MSG_H2C,
 870         HALMAC_MSG_PWR,
 871         HALMAC_MSG_SND,
 872         HALMAC_MSG_COMMON,
 873         HALMAC_MSG_DBI,
 874         HALMAC_MSG_MDIO,
 875         HALMAC_MSG_USB
 876 };
 877
 878 enum halmac_cmd_process_status {
 879         HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */
 880         HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */
 881         HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */
 882         HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */
 883         HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */
 884         HALMAC_CMD_PROCESS_UNDEFINE = 0x7F,
 885 };
 886
 887 enum halmac_feature_id {
 888         HALMAC_FEATURE_CFG_PARA, /* Support */
 889         HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */
 890         HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */
 891         HALMAC_FEATURE_UPDATE_PACKET, /* Support */
 892         HALMAC_FEATURE_UPDATE_DATAPACK,
 893         HALMAC_FEATURE_RUN_DATAPACK,
 894         HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */
 895         HALMAC_FEATURE_IQK, /* Support */
 896         HALMAC_FEATURE_POWER_TRACKING, /* Support */
 897         HALMAC_FEATURE_PSD, /* Support */
 898         HALMAC_FEATURE_ALL, /* Support, only for reset */
 899 };
 900
 901 enum halmac_drv_rsvd_pg_num {
 902         HALMAC_RSVD_PG_NUM16, /* 2K */
 903         HALMAC_RSVD_PG_NUM24, /* 3K */
 904         HALMAC_RSVD_PG_NUM32, /* 4K */
 905 };
 906
 907 enum halmac_pcie_cfg {
 908         HALMAC_PCIE_GEN1,
 909         HALMAC_PCIE_GEN2,
 910         HALMAC_PCIE_CFG_UNDEFINE,
 911 };
 912
 913 enum halmac_portid {
 914         HALMAC_PORTID0 = 0,
 915         HALMAC_PORTID1 = 1,
 916         HALMAC_PORTID2 = 2,
 917         HALMAC_PORTID3 = 3,
 918         HALMAC_PORTID4 = 4,
 919         HALMAC_PORTIDMAX
 920 };
 921
 922 struct halmac_p2pps {
 923         /*DW0*/
 924         u8 offload_en : 1;
 925         u8 role : 1;
 926         u8 ctwindow_en : 1;
 927         u8 noa_en : 1;
 928         u8 noa_sel : 1;
 929         u8 all_sta_sleep : 1;
 930         u8 discovery : 1;
 931         u8 rsvd2 : 1;
 932         u8 p2p_port_id;
 933         u8 p2p_group;
 934         u8 p2p_macid;
 935
 936         /*DW1*/
 937         u8 ctwindow_length;
 938         u8 rsvd3;
 939         u8 rsvd4;
 940         u8 rsvd5;
 941
 942         /*DW2*/
 943         u32 noa_duration_para;
 944
 945         /*DW3*/
 946         u32 noa_interval_para;
 947
 948         /*DW4*/
 949         u32 noa_start_time_para;
 950
 951         /*DW5*/
 952         u32 noa_count_para;
 953 };
 954
 955 /* Platform API setting */
 956 struct halmac_platform_api {
 957         /* R/W register */
 958         u8 (*SDIO_CMD52_READ)(void *driver_adapter, u32 offset);
 959         u8 (*SDIO_CMD53_READ_8)(void *driver_adapter, u32 offset);
 960         u16 (*SDIO_CMD53_READ_16)(void *driver_adapter, u32 offset);
 961         u32 (*SDIO_CMD53_READ_32)(void *driver_adapter, u32 offset);
 962         u8 (*SDIO_CMD53_READ_N)(void *driver_adapter, u32 offset, u32 size,
 963                                 u8 *data);
 964         void (*SDIO_CMD52_WRITE)(void *driver_adapter, u32 offset, u8 value);
 965         void (*SDIO_CMD53_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
 966         void (*SDIO_CMD53_WRITE_16)(void *driver_adapter, u32 offset,
 967                                     u16 value);
 968         void (*SDIO_CMD53_WRITE_32)(void *driver_adapter, u32 offset,
 969                                     u32 value);
 970         u8 (*REG_READ_8)(void *driver_adapter, u32 offset);
 971         u16 (*REG_READ_16)(void *driver_adapter, u32 offset);
 972         u32 (*REG_READ_32)(void *driver_adapter, u32 offset);
 973         void (*REG_WRITE_8)(void *driver_adapter, u32 offset, u8 value);
 974         void (*REG_WRITE_16)(void *driver_adapter, u32 offset, u16 value);
 975         void (*REG_WRITE_32)(void *driver_adapter, u32 offset, u32 value);
 976
 977         /* send buf to reserved page, the tx_desc is not included in buf,
 978          * driver need to fill tx_desc with qsel = bcn
 979          */
 980         bool (*SEND_RSVD_PAGE)(void *driver_adapter, u8 *buf, u32 size);
 981         /* send buf to h2c queue, the tx_desc is not included in buf,
 982          * driver need to fill tx_desc with qsel = h2c
 983          */
 984         bool (*SEND_H2C_PKT)(void *driver_adapter, u8 *buf, u32 size);
 985
 986         bool (*EVENT_INDICATION)(void *driver_adapter,
 987                                  enum halmac_feature_id feature_id,
 988                                  enum halmac_cmd_process_status process_status,
 989                                  u8 *buf, u32 size);
 990 };
 991
 992 /*1->Little endian 0->Big endian*/
 993 #if HALMAC_SYSTEM_ENDIAN
 994
 995 #else
 996
 997 #endif
 998
 999 /* User can not use members in address_l_h, use address[6] is mandatory */
1000 union halmac_wlan_addr {
1001         u8 address[6]; /* WLAN address (MACID, BSSID, Brodcast ID).
1002                         * address[0] is lowest, address[5] is highest
1003                         */
1004         struct {
1005                 union {
1006                         u32 address_low;
1007                         __le32 le_address_low;
1008                         u8 address_low_b[4];
1009                 };
1010                 union {
1011                         u16 address_high;
1012                         __le16 le_address_high;
1013                         u8 address_high_b[2];
1014                 };
1015         } address_l_h;
1016 };
1017
1018 enum halmac_snd_role {
1019         HAL_BFER = 0,
1020         HAL_BFEE = 1,
1021 };
1022
1023 enum halmac_csi_seg_len {
1024         HAL_CSI_SEG_4K = 0,
1025         HAL_CSI_SEG_8K = 1,
1026         HAL_CSI_SEG_11K = 2,
1027 };
1028
1029 struct halmac_cfg_mumimo_para {
1030         enum halmac_snd_role role;
1031         bool sounding_sts[6];
1032         u16 grouping_bitmap;
1033         bool mu_tx_en;
1034         u32 given_gid_tab[2];
1035         u32 given_user_pos[4];
1036 };
1037
1038 struct halmac_su_bfer_init_para {
1039         u8 userid;
1040         u16 paid;
1041         u16 csi_para;
1042         union halmac_wlan_addr bfer_address;
1043 };
1044
1045 struct halmac_mu_bfee_init_para {
1046         u8 userid;
1047         u16 paid;
1048         u32 user_position_l;
1049         u32 user_position_h;
1050 };
1051
1052 struct halmac_mu_bfer_init_para {
1053         u16 paid;
1054         u16 csi_para;
1055         u16 my_aid;
1056         enum halmac_csi_seg_len csi_length_sel;
1057         union halmac_wlan_addr bfer_address;
1058 };
1059
1060 struct halmac_snd_info {
1061         u16 paid;
1062         u8 userid;
1063         enum halmac_data_rate ndpa_rate;
1064         u16 csi_para;
1065         u16 my_aid;
1066         enum halmac_data_rate csi_rate;
1067         enum halmac_csi_seg_len csi_length_sel;
1068         enum halmac_snd_role role;
1069         union halmac_wlan_addr bfer_address;
1070         enum halmac_bw bw;
1071         u8 txbf_en;
1072         struct halmac_su_bfer_init_para *su_bfer_init;
1073         struct halmac_mu_bfer_init_para *mu_bfer_init;
1074         struct halmac_mu_bfee_init_para *mu_bfee_init;
1075 };
1076
1077 struct halmac_cs_info {
1078         u8 *ch_info_buf;
1079         u8 *ch_info_buf_w;
1080         u8 extra_info_en;
1081         u32 buf_size; /* buffer size */
1082         u32 avai_buf_size; /* buffer size */
1083         u32 total_size;
1084         u32 accu_timeout;
1085         u32 ch_num;
1086 };
1087
1088 struct halmac_restore_info {
1089         u32 mac_register;
1090         u32 value;
1091         u8 length;
1092 };
1093
1094 struct halmac_event_trigger {
1095         u32 physical_efuse_map : 1;
1096         u32 logical_efuse_map : 1;
1097         u32 rsvd1 : 28;
1098 };
1099
1100 struct halmac_h2c_header_info {
1101         u16 sub_cmd_id;
1102         u16 content_size;
1103         bool ack;
1104 };
1105
1106 enum halmac_dlfw_state {
1107         HALMAC_DLFW_NONE = 0,
1108         HALMAC_DLFW_DONE = 1,
1109         HALMAC_GEN_INFO_SENT = 2,
1110         HALMAC_DLFW_UNDEFINED = 0x7F,
1111 };
1112
1113 enum halmac_efuse_cmd_construct_state {
1114         HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0,
1115         HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1,
1116         HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2,
1117         HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3,
1118         HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1119 };
1120
1121 enum halmac_cfg_para_cmd_construct_state {
1122         HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0,
1123         HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1,
1124         HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2,
1125         HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3,
1126         HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1127 };
1128
1129 enum halmac_scan_cmd_construct_state {
1130         HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0,
1131         HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1,
1132         HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2,
1133         HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3,
1134         HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4,
1135         HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F,
1136 };
1137
1138 enum halmac_api_state {
1139         HALMAC_API_STATE_INIT = 0,
1140         HALMAC_API_STATE_HALT = 1,
1141         HALMAC_API_STATE_UNDEFINED = 0x7F,
1142 };
1143
1144 struct halmac_efuse_state_set {
1145         enum halmac_efuse_cmd_construct_state efuse_cmd_construct_state;
1146         enum halmac_cmd_process_status process_status;
1147         u8 fw_return_code;
1148         u16 seq_num;
1149 };
1150
1151 struct halmac_cfg_para_state_set {
1152         enum halmac_cfg_para_cmd_construct_state cfg_para_cmd_construct_state;
1153         enum halmac_cmd_process_status process_status;
1154         u8 fw_return_code;
1155         u16 seq_num;
1156 };
1157
1158 struct halmac_scan_state_set {
1159         enum halmac_scan_cmd_construct_state scan_cmd_construct_state;
1160         enum halmac_cmd_process_status process_status;
1161         u8 fw_return_code;
1162         u16 seq_num;
1163 };
1164
1165 struct halmac_update_packet_state_set {
1166         enum halmac_cmd_process_status process_status;
1167         u8 fw_return_code;
1168         u16 seq_num;
1169 };
1170
1171 struct halmac_iqk_state_set {
1172         enum halmac_cmd_process_status process_status;
1173         u8 fw_return_code;
1174         u16 seq_num;
1175 };
1176
1177 struct halmac_power_tracking_state_set {
1178         enum halmac_cmd_process_status process_status;
1179         u8 fw_return_code;
1180         u16 seq_num;
1181 };
1182
1183 struct halmac_psd_state_set {
1184         enum halmac_cmd_process_status process_status;
1185         u16 data_size;
1186         u16 segment_size;
1187         u8 *data;
1188         u8 fw_return_code;
1189         u16 seq_num;
1190 };
1191
1192 struct halmac_state {
1193         struct halmac_efuse_state_set
1194                 efuse_state_set; /* State machine + cmd process status */
1195         struct halmac_cfg_para_state_set
1196                 cfg_para_state_set; /* State machine + cmd process status */
1197         struct halmac_scan_state_set
1198                 scan_state_set; /* State machine + cmd process status */
1199         struct halmac_update_packet_state_set
1200                 update_packet_set; /* cmd process status */
1201         struct halmac_iqk_state_set iqk_set; /* cmd process status */
1202         struct halmac_power_tracking_state_set
1203                 power_tracking_set; /* cmd process status */
1204         struct halmac_psd_state_set psd_set; /* cmd process status */
1205         enum halmac_api_state api_state; /* Halmac api state */
1206         enum halmac_mac_power mac_power; /* 0 : power off, 1 : power on*/
1207         enum halmac_ps_state ps_state; /* power saving state */
1208         enum halmac_dlfw_state dlfw_state; /* download FW state */
1209 };
1210
1211 struct halmac_ver {
1212         u8 major_ver;
1213         u8 prototype_ver;
1214         u8 minor_ver;
1215 };
1216
1217 enum halmac_api_id {
1218         /*stuff, need to be the 1st*/
1219         HALMAC_API_STUFF = 0x0,
1220         /*stuff, need to be the 1st*/
1221         HALMAC_API_MAC_POWER_SWITCH = 0x1,
1222         HALMAC_API_DOWNLOAD_FIRMWARE = 0x2,
1223         HALMAC_API_CFG_MAC_ADDR = 0x3,
1224         HALMAC_API_CFG_BSSID = 0x4,
1225         HALMAC_API_CFG_MULTICAST_ADDR = 0x5,
1226         HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6,
1227         HALMAC_API_INIT_SYSTEM_CFG = 0x7,
1228         HALMAC_API_INIT_TRX_CFG = 0x8,
1229         HALMAC_API_CFG_RX_AGGREGATION = 0x9,
1230         HALMAC_API_INIT_PROTOCOL_CFG = 0xA,
1231         HALMAC_API_INIT_EDCA_CFG = 0xB,
1232         HALMAC_API_CFG_OPERATION_MODE = 0xC,
1233         HALMAC_API_CFG_CH_BW = 0xD,
1234         HALMAC_API_CFG_BW = 0xE,
1235         HALMAC_API_INIT_WMAC_CFG = 0xF,
1236         HALMAC_API_INIT_MAC_CFG = 0x10,
1237         HALMAC_API_INIT_SDIO_CFG = 0x11,
1238         HALMAC_API_INIT_USB_CFG = 0x12,
1239         HALMAC_API_INIT_PCIE_CFG = 0x13,
1240         HALMAC_API_INIT_INTERFACE_CFG = 0x14,
1241         HALMAC_API_DEINIT_SDIO_CFG = 0x15,
1242         HALMAC_API_DEINIT_USB_CFG = 0x16,
1243         HALMAC_API_DEINIT_PCIE_CFG = 0x17,
1244         HALMAC_API_DEINIT_INTERFACE_CFG = 0x18,
1245         HALMAC_API_GET_EFUSE_SIZE = 0x19,
1246         HALMAC_API_DUMP_EFUSE_MAP = 0x1A,
1247         HALMAC_API_WRITE_EFUSE = 0x1B,
1248         HALMAC_API_READ_EFUSE = 0x1C,
1249         HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D,
1250         HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E,
1251         HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F,
1252         HALMAC_API_READ_LOGICAL_EFUSE = 0x20,
1253         HALMAC_API_PG_EFUSE_BY_MAP = 0x21,
1254         HALMAC_API_GET_C2H_INFO = 0x22,
1255         HALMAC_API_CFG_FWLPS_OPTION = 0x23,
1256         HALMAC_API_CFG_FWIPS_OPTION = 0x24,
1257         HALMAC_API_ENTER_WOWLAN = 0x25,
1258         HALMAC_API_LEAVE_WOWLAN = 0x26,
1259         HALMAC_API_ENTER_PS = 0x27,
1260         HALMAC_API_LEAVE_PS = 0x28,
1261         HALMAC_API_H2C_LB = 0x29,
1262         HALMAC_API_DEBUG = 0x2A,
1263         HALMAC_API_CFG_PARAMETER = 0x2B,
1264         HALMAC_API_UPDATE_PACKET = 0x2C,
1265         HALMAC_API_BCN_IE_FILTER = 0x2D,
1266         HALMAC_API_REG_READ_8 = 0x2E,
1267         HALMAC_API_REG_WRITE_8 = 0x2F,
1268         HALMAC_API_REG_READ_16 = 0x30,
1269         HALMAC_API_REG_WRITE_16 = 0x31,
1270         HALMAC_API_REG_READ_32 = 0x32,
1271         HALMAC_API_REG_WRITE_32 = 0x33,
1272         HALMAC_API_TX_ALLOWED_SDIO = 0x34,
1273         HALMAC_API_SET_BULKOUT_NUM = 0x35,
1274         HALMAC_API_GET_SDIO_TX_ADDR = 0x36,
1275         HALMAC_API_GET_USB_BULKOUT_ID = 0x37,
1276         HALMAC_API_TIMER_2S = 0x38,
1277         HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39,
1278         HALMAC_API_SEND_ORIGINAL_H2C = 0x3A,
1279         HALMAC_API_UPDATE_DATAPACK = 0x3B,
1280         HALMAC_API_RUN_DATAPACK = 0x3C,
1281         HALMAC_API_CFG_DRV_INFO = 0x3D,
1282         HALMAC_API_SEND_BT_COEX = 0x3E,
1283         HALMAC_API_VERIFY_PLATFORM_API = 0x3F,
1284         HALMAC_API_GET_FIFO_SIZE = 0x40,
1285         HALMAC_API_DUMP_FIFO = 0x41,
1286         HALMAC_API_CFG_TXBF = 0x42,
1287         HALMAC_API_CFG_MUMIMO = 0x43,
1288         HALMAC_API_CFG_SOUNDING = 0x44,
1289         HALMAC_API_DEL_SOUNDING = 0x45,
1290         HALMAC_API_SU_BFER_ENTRY_INIT = 0x46,
1291         HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47,
1292         HALMAC_API_MU_BFER_ENTRY_INIT = 0x48,
1293         HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49,
1294         HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A,
1295         HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B,
1296         HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C,
1297         HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D,
1298
1299         HALMAC_API_ADD_CH_INFO = 0x4E,
1300         HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F,
1301         HALMAC_API_CTRL_CH_SWITCH = 0x50,
1302         HALMAC_API_CLEAR_CH_INFO = 0x51,
1303
1304         HALMAC_API_SEND_GENERAL_INFO = 0x52,
1305         HALMAC_API_START_IQK = 0x53,
1306         HALMAC_API_CTRL_PWR_TRACKING = 0x54,
1307         HALMAC_API_PSD = 0x55,
1308         HALMAC_API_CFG_TX_AGG_ALIGN = 0x56,
1309
1310         HALMAC_API_QUERY_STATE = 0x57,
1311         HALMAC_API_RESET_FEATURE = 0x58,
1312         HALMAC_API_CHECK_FW_STATUS = 0x59,
1313         HALMAC_API_DUMP_FW_DMEM = 0x5A,
1314         HALMAC_API_CFG_MAX_DL_SIZE = 0x5B,
1315
1316         HALMAC_API_INIT_OBJ = 0x5C,
1317         HALMAC_API_DEINIT_OBJ = 0x5D,
1318         HALMAC_API_CFG_LA_MODE = 0x5E,
1319         HALMAC_API_GET_HW_VALUE = 0x5F,
1320         HALMAC_API_SET_HW_VALUE = 0x60,
1321         HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61,
1322         HALMAC_API_SWITCH_EFUSE_BANK = 0x62,
1323         HALMAC_API_WRITE_EFUSE_BT = 0x63,
1324         HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64,
1325         HALMAC_API_DL_DRV_RSVD_PG = 0x65,
1326         HALMAC_API_PCIE_SWITCH = 0x66,
1327         HALMAC_API_PHY_CFG = 0x67,
1328         HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68,
1329         HALMAC_API_CFG_CSI_RATE = 0x69,
1330         HALMAC_API_MAX
1331 };
1332
1333 struct halmac_api_record {
1334         enum halmac_api_id api_array[API_ARRAY_SIZE];
1335         u8 array_wptr;
1336 };
1337
1338 enum halmac_la_mode {
1339         HALMAC_LA_MODE_DISABLE = 0,
1340         HALMAC_LA_MODE_PARTIAL = 1,
1341         HALMAC_LA_MODE_FULL = 2,
1342         HALMAC_LA_MODE_UNDEFINE = 0x7F,
1343 };
1344
1345 enum halmac_rx_fifo_expanding_mode {
1346         HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0,
1347         HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1,
1348         HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2,
1349         HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3,
1350         HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F,
1351 };
1352
1353 enum halmac_sdio_cmd53_4byte_mode {
1354         HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0,
1355         HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1,
1356         HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2,
1357         HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3,
1358         HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F,
1359 };
1360
1361 enum halmac_usb_mode {
1362         HALMAC_USB_MODE_U2 = 1,
1363         HALMAC_USB_MODE_U3 = 2,
1364 };
1365
1366 enum halmac_hw_id {
1367         /* Get HW value */
1368         HALMAC_HW_RQPN_MAPPING = 0x00,
1369         HALMAC_HW_EFUSE_SIZE = 0x01,
1370         HALMAC_HW_EEPROM_SIZE = 0x02,
1371         HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03,
1372         HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04,
1373         HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05,
1374         HALMAC_HW_TXFIFO_SIZE = 0x06,
1375         HALMAC_HW_RSVD_PG_BNDY = 0x07,
1376         HALMAC_HW_CAM_ENTRY_NUM = 0x08,
1377         HALMAC_HW_IC_VERSION = 0x09,
1378         HALMAC_HW_PAGE_SIZE = 0x0A,
1379         HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B,
1380         HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C,
1381         HALMAC_HW_DRV_INFO_SIZE = 0x0D,
1382         HALMAC_HW_TXFF_ALLOCATION = 0x0E,
1383         HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F,
1384         HALMAC_HW_FW_HDR_SIZE = 0x10,
1385         HALMAC_HW_TX_DESC_SIZE = 0x11,
1386         HALMAC_HW_RX_DESC_SIZE = 0x12,
1387         HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13,
1388         /* Set HW value */
1389         HALMAC_HW_USB_MODE = 0x60,
1390         HALMAC_HW_SEQ_EN = 0x61,
1391         HALMAC_HW_BANDWIDTH = 0x62,
1392         HALMAC_HW_CHANNEL = 0x63,
1393         HALMAC_HW_PRI_CHANNEL_IDX = 0x64,
1394         HALMAC_HW_EN_BB_RF = 0x65,
1395         HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66,
1396         HALMAC_HW_AMPDU_CONFIG = 0x67,
1397
1398         HALMAC_HW_ID_UNDEFINE = 0x7F,
1399 };
1400
1401 enum halmac_efuse_bank {
1402         HALMAC_EFUSE_BANK_WIFI = 0,
1403         HALMAC_EFUSE_BANK_BT = 1,
1404         HALMAC_EFUSE_BANK_BT_1 = 2,
1405         HALMAC_EFUSE_BANK_BT_2 = 3,
1406         HALMAC_EFUSE_BANK_MAX,
1407         HALMAC_EFUSE_BANK_UNDEFINE = 0X7F,
1408 };
1409
1410 struct halmac_txff_allocation {
1411         u16 tx_fifo_pg_num;
1412         u16 rsvd_pg_num;
1413         u16 rsvd_drv_pg_num;
1414         u16 ac_q_pg_num;
1415         u16 high_queue_pg_num;
1416         u16 low_queue_pg_num;
1417         u16 normal_queue_pg_num;
1418         u16 extra_queue_pg_num;
1419         u16 pub_queue_pg_num;
1420         u16 rsvd_pg_bndy;
1421         u16 rsvd_drv_pg_bndy;
1422         u16 rsvd_h2c_extra_info_pg_bndy;
1423         u16 rsvd_h2c_queue_pg_bndy;
1424         u16 rsvd_cpu_instr_pg_bndy;
1425         u16 rsvd_fw_txbuff_pg_bndy;
1426         enum halmac_la_mode la_mode;
1427         enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode;
1428 };
1429
1430 struct halmac_rqpn_map {
1431         enum halmac_dma_mapping dma_map_vo;
1432         enum halmac_dma_mapping dma_map_vi;
1433         enum halmac_dma_mapping dma_map_be;
1434         enum halmac_dma_mapping dma_map_bk;
1435         enum halmac_dma_mapping dma_map_mg;
1436         enum halmac_dma_mapping dma_map_hi;
1437 };
1438
1439 struct halmac_security_setting {
1440         u8 tx_encryption;
1441         u8 rx_decryption;
1442         u8 bip_enable;
1443 };
1444
1445 struct halmac_cam_entry_info {
1446         enum hal_security_type security_type;
1447         u32 key[4];
1448         u32 key_ext[4];
1449         u8 mac_address[6];
1450         u8 unicast;
1451         u8 key_id;
1452         u8 valid;
1453 };
1454
1455 struct halmac_cam_entry_format {
1456         u16 key_id : 2;
1457         u16 type : 3;
1458         u16 mic : 1;
1459         u16 grp : 1;
1460         u16 spp_mode : 1;
1461         u16 rpt_md : 1;
1462         u16 ext_sectype : 1;
1463         u16 mgnt : 1;
1464         u16 rsvd1 : 4;
1465         u16 valid : 1;
1466         u8 mac_address[6];
1467         u32 key[4];
1468         u32 rsvd[2];
1469 };
1470
1471 struct halmac_tx_page_threshold_info {
1472         u32 threshold;
1473         enum halmac_dma_mapping dma_queue_sel;
1474 };
1475
1476 struct halmac_ampdu_config {
1477         u8 max_agg_num;
1478 };
1479
1480 struct halmac_port_cfg {
1481         u8 port0_sync_tsf;
1482         u8 port1_sync_tsf;
1483 };
1484
1485 struct halmac_rqpn_ {
1486         enum halmac_trx_mode mode;
1487         enum halmac_dma_mapping dma_map_vo;
1488         enum halmac_dma_mapping dma_map_vi;
1489         enum halmac_dma_mapping dma_map_be;
1490         enum halmac_dma_mapping dma_map_bk;
1491         enum halmac_dma_mapping dma_map_mg;
1492         enum halmac_dma_mapping dma_map_hi;
1493 };
1494
1495 struct halmac_pg_num_ {
1496         enum halmac_trx_mode mode;
1497         u16 hq_num;
1498         u16 nq_num;
1499         u16 lq_num;
1500         u16 exq_num;
1501         u16 gap_num; /*used for loopback mode*/
1502 };
1503
1504 struct halmac_intf_phy_para_ {
1505         u16 offset;
1506         u16 value;
1507         u16 ip_sel;
1508         u16 cut;
1509         u16 plaform;
1510 };
1511
1512 struct halmac_iqk_para_ {
1513         u8 clear;
1514         u8 segment_iqk;
1515 };
1516
1517 /* Hal mac adapter */
1518 struct halmac_adapter {
1519         /* Dma mapping of protocol queues */
1520         enum halmac_dma_mapping halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM];
1521         /* low power state option */
1522         struct halmac_fwlps_option fwlps_option;
1523         /* mac address information, suppot 2 ports */
1524         union halmac_wlan_addr hal_mac_addr[HALMAC_PORTIDMAX];
1525         /* bss address information, suppot 2 ports */
1526         union halmac_wlan_addr hal_bss_addr[HALMAC_PORTIDMAX];
1527         /* Protect h2c_packet_seq packet*/
1528         spinlock_t h2c_seq_lock;
1529         /* Protect Efuse map memory of halmac_adapter */
1530         spinlock_t efuse_lock;
1531         struct halmac_config_para_info config_para_info;
1532         struct halmac_cs_info ch_sw_info;
1533         struct halmac_event_trigger event_trigger;
1534         /* HW related information */
1535         struct halmac_hw_config_info hw_config_info;
1536         struct halmac_sdio_free_space sdio_free_space;
1537         struct halmac_snd_info snd_info;
1538         /* Backup HalAdapter address */
1539         void *hal_adapter_backup;
1540         /* Driver or FW adapter address. Do not write this memory*/
1541         void *driver_adapter;
1542         u8 *hal_efuse_map;
1543         /* Record function pointer of halmac api */
1544         void *halmac_api;
1545         /* Record function pointer of platform api */
1546         struct halmac_platform_api *halmac_platform_api;
1547         /* Record efuse used memory */
1548         u32 efuse_end;
1549         u32 h2c_buf_free_space;
1550         u32 h2c_buff_size;
1551         u32 max_download_size;
1552         /* Chip ID, 8822B, 8821C... */
1553         enum halmac_chip_id chip_id;
1554         /* A cut, B cut... */
1555         enum halmac_chip_ver chip_version;
1556         struct halmac_fw_version fw_version;
1557         struct halmac_state halmac_state;
1558         /* Interface information, get from driver */
1559         enum halmac_interface halmac_interface;
1560         /* Noraml, WMM, P2P, LoopBack... */
1561         enum halmac_trx_mode trx_mode;
1562         struct halmac_txff_allocation txff_allocation;
1563         u8 h2c_packet_seq; /* current h2c packet sequence number */
1564         u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */
1565         bool hal_efuse_map_valid;
1566         u8 efuse_segment_size;
1567         u8 rpwm_record; /* record rpwm value */
1568         bool low_clk; /*LPS 32K or IPS 32K*/
1569         u8 halmac_bulkout_num; /* USB bulkout num */
1570         struct halmac_api_record api_record; /* API record */
1571         bool gen_info_valid;
1572         struct halmac_general_info general_info;
1573         u8 drv_info_size;
1574         enum halmac_sdio_cmd53_4byte_mode sdio_cmd53_4byte;
1575 };
1576
1577 /* Function pointer of  Hal mac API */
1578 struct halmac_api {
1579         enum halmac_ret_status (*halmac_mac_power_switch)(
1580                 struct halmac_adapter *halmac_adapter,
1581                 enum halmac_mac_power halmac_power);
1582         enum halmac_ret_status (*halmac_download_firmware)(
1583                 struct halmac_adapter *halmac_adapter, u8 *hamacl_fw,
1584                 u32 halmac_fw_size);
1585         enum halmac_ret_status (*halmac_free_download_firmware)(
1586                 struct halmac_adapter *halmac_adapter,
1587                 enum halmac_dlfw_mem dlfw_mem, u8 *hamacl_fw,
1588                 u32 halmac_fw_size);
1589         enum halmac_ret_status (*halmac_get_fw_version)(
1590                 struct halmac_adapter *halmac_adapter,
1591                 struct halmac_fw_version *fw_version);
1592         enum halmac_ret_status (*halmac_cfg_mac_addr)(
1593                 struct halmac_adapter *halmac_adapter, u8 halmac_port,
1594                 union halmac_wlan_addr *hal_address);
1595         enum halmac_ret_status (*halmac_cfg_bssid)(
1596                 struct halmac_adapter *halmac_adapter, u8 halmac_port,
1597                 union halmac_wlan_addr *hal_address);
1598         enum halmac_ret_status (*halmac_cfg_multicast_addr)(
1599                 struct halmac_adapter *halmac_adapter,
1600                 union halmac_wlan_addr *hal_address);
1601         enum halmac_ret_status (*halmac_pre_init_system_cfg)(
1602                 struct halmac_adapter *halmac_adapter);
1603         enum halmac_ret_status (*halmac_init_system_cfg)(
1604                 struct halmac_adapter *halmac_adapter);
1605         enum halmac_ret_status (*halmac_init_trx_cfg)(
1606                 struct halmac_adapter *halmac_adapter,
1607                 enum halmac_trx_mode mode);
1608         enum halmac_ret_status (*halmac_init_h2c)(
1609                 struct halmac_adapter *halmac_adapter);
1610         enum halmac_ret_status (*halmac_cfg_rx_aggregation)(
1611                 struct halmac_adapter *halmac_adapter,
1612                 struct halmac_rxagg_cfg *phalmac_rxagg_cfg);
1613         enum halmac_ret_status (*halmac_init_protocol_cfg)(
1614                 struct halmac_adapter *halmac_adapter);
1615         enum halmac_ret_status (*halmac_init_edca_cfg)(
1616                 struct halmac_adapter *halmac_adapter);
1617         enum halmac_ret_status (*halmac_cfg_operation_mode)(
1618                 struct halmac_adapter *halmac_adapter,
1619                 enum halmac_wireless_mode wireless_mode);
1620         enum halmac_ret_status (*halmac_cfg_ch_bw)(
1621                 struct halmac_adapter *halmac_adapter, u8 channel,
1622                 enum halmac_pri_ch_idx pri_ch_idx, enum halmac_bw bw);
1623         enum halmac_ret_status (*halmac_cfg_bw)(
1624                 struct halmac_adapter *halmac_adapter, enum halmac_bw bw);
1625         enum halmac_ret_status (*halmac_init_wmac_cfg)(
1626                 struct halmac_adapter *halmac_adapter);
1627         enum halmac_ret_status (*halmac_init_mac_cfg)(
1628                 struct halmac_adapter *halmac_adapter,
1629                 enum halmac_trx_mode mode);
1630         enum halmac_ret_status (*halmac_init_sdio_cfg)(
1631                 struct halmac_adapter *halmac_adapter);
1632         enum halmac_ret_status (*halmac_init_usb_cfg)(
1633                 struct halmac_adapter *halmac_adapter);
1634         enum halmac_ret_status (*halmac_init_pcie_cfg)(
1635                 struct halmac_adapter *halmac_adapter);
1636         enum halmac_ret_status (*halmac_init_interface_cfg)(
1637                 struct halmac_adapter *halmac_adapter);
1638         enum halmac_ret_status (*halmac_deinit_sdio_cfg)(
1639                 struct halmac_adapter *halmac_adapter);
1640         enum halmac_ret_status (*halmac_deinit_usb_cfg)(
1641                 struct halmac_adapter *halmac_adapter);
1642         enum halmac_ret_status (*halmac_deinit_pcie_cfg)(
1643                 struct halmac_adapter *halmac_adapter);
1644         enum halmac_ret_status (*halmac_deinit_interface_cfg)(
1645                 struct halmac_adapter *halmac_adapter);
1646         enum halmac_ret_status (*halmac_get_efuse_size)(
1647                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1648         enum halmac_ret_status (*halmac_get_efuse_available_size)(
1649                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1650         enum halmac_ret_status (*halmac_dump_efuse_map)(
1651                 struct halmac_adapter *halmac_adapter,
1652                 enum halmac_efuse_read_cfg cfg);
1653         enum halmac_ret_status (*halmac_dump_efuse_map_bt)(
1654                 struct halmac_adapter *halmac_adapter,
1655                 enum halmac_efuse_bank halmac_efues_bank, u32 bt_efuse_map_size,
1656                 u8 *bt_efuse_map);
1657         enum halmac_ret_status (*halmac_write_efuse)(
1658                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1659                 u8 halmac_value);
1660         enum halmac_ret_status (*halmac_read_efuse)(
1661                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1662                 u8 *value);
1663         enum halmac_ret_status (*halmac_switch_efuse_bank)(
1664                 struct halmac_adapter *halmac_adapter,
1665                 enum halmac_efuse_bank halmac_efues_bank);
1666         enum halmac_ret_status (*halmac_write_efuse_bt)(
1667                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1668                 u8 halmac_value, enum halmac_efuse_bank halmac_efues_bank);
1669         enum halmac_ret_status (*halmac_get_logical_efuse_size)(
1670                 struct halmac_adapter *halmac_adapter, u32 *halmac_size);
1671         enum halmac_ret_status (*halmac_dump_logical_efuse_map)(
1672                 struct halmac_adapter *halmac_adapter,
1673                 enum halmac_efuse_read_cfg cfg);
1674         enum halmac_ret_status (*halmac_write_logical_efuse)(
1675                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1676                 u8 halmac_value);
1677         enum halmac_ret_status (*halmac_read_logical_efuse)(
1678                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1679                 u8 *value);
1680         enum halmac_ret_status (*halmac_pg_efuse_by_map)(
1681                 struct halmac_adapter *halmac_adapter,
1682                 struct halmac_pg_efuse_info *pg_efuse_info,
1683                 enum halmac_efuse_read_cfg cfg);
1684         enum halmac_ret_status (*halmac_get_c2h_info)(
1685                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1686                 u32 halmac_size);
1687         enum halmac_ret_status (*halmac_cfg_fwlps_option)(
1688                 struct halmac_adapter *halmac_adapter,
1689                 struct halmac_fwlps_option *lps_option);
1690         enum halmac_ret_status (*halmac_cfg_fwips_option)(
1691                 struct halmac_adapter *halmac_adapter,
1692                 struct halmac_fwips_option *ips_option);
1693         enum halmac_ret_status (*halmac_enter_wowlan)(
1694                 struct halmac_adapter *halmac_adapter,
1695                 struct halmac_wowlan_option *wowlan_option);
1696         enum halmac_ret_status (*halmac_leave_wowlan)(
1697                 struct halmac_adapter *halmac_adapter);
1698         enum halmac_ret_status (*halmac_enter_ps)(
1699                 struct halmac_adapter *halmac_adapter,
1700                 enum halmac_ps_state ps_state);
1701         enum halmac_ret_status (*halmac_leave_ps)(
1702                 struct halmac_adapter *halmac_adapter);
1703         enum halmac_ret_status (*halmac_h2c_lb)(
1704                 struct halmac_adapter *halmac_adapter);
1705         enum halmac_ret_status (*halmac_debug)(
1706                 struct halmac_adapter *halmac_adapter);
1707         enum halmac_ret_status (*halmac_cfg_parameter)(
1708                 struct halmac_adapter *halmac_adapter,
1709                 struct halmac_phy_parameter_info *para_info, u8 full_fifo);
1710         enum halmac_ret_status (*halmac_update_packet)(
1711                 struct halmac_adapter *halmac_adapter,
1712                 enum halmac_packet_id pkt_id, u8 *pkt, u32 pkt_size);
1713         enum halmac_ret_status (*halmac_bcn_ie_filter)(
1714                 struct halmac_adapter *halmac_adapter,
1715                 struct halmac_bcn_ie_info *bcn_ie_info);
1716         u8 (*halmac_reg_read_8)(struct halmac_adapter *halmac_adapter,
1717                                 u32 halmac_offset);
1718         enum halmac_ret_status (*halmac_reg_write_8)(
1719                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1720                 u8 halmac_data);
1721         u16 (*halmac_reg_read_16)(struct halmac_adapter *halmac_adapter,
1722                                   u32 halmac_offset);
1723         enum halmac_ret_status (*halmac_reg_write_16)(
1724                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1725                 u16 halmac_data);
1726         u32 (*halmac_reg_read_32)(struct halmac_adapter *halmac_adapter,
1727                                   u32 halmac_offset);
1728         u32 (*halmac_reg_read_indirect_32)(
1729                 struct halmac_adapter *halmac_adapter, u32 halmac_offset);
1730         u8 (*halmac_reg_sdio_cmd53_read_n)(
1731                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1732                 u32 halmac_size, u8 *halmac_data);
1733         enum halmac_ret_status (*halmac_reg_write_32)(
1734                 struct halmac_adapter *halmac_adapter, u32 halmac_offset,
1735                 u32 halmac_data);
1736         enum halmac_ret_status (*halmac_tx_allowed_sdio)(
1737                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1738                 u32 halmac_size);
1739         enum halmac_ret_status (*halmac_set_bulkout_num)(
1740                 struct halmac_adapter *halmac_adapter, u8 bulkout_num);
1741         enum halmac_ret_status (*halmac_get_sdio_tx_addr)(
1742                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1743                 u32 halmac_size, u32 *pcmd53_addr);
1744         enum halmac_ret_status (*halmac_get_usb_bulkout_id)(
1745                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1746                 u32 halmac_size, u8 *bulkout_id);
1747         enum halmac_ret_status (*halmac_timer_2s)(
1748                 struct halmac_adapter *halmac_adapter);
1749         enum halmac_ret_status (*halmac_fill_txdesc_checksum)(
1750                 struct halmac_adapter *halmac_adapter, u8 *cur_desc);
1751         enum halmac_ret_status (*halmac_update_datapack)(
1752                 struct halmac_adapter *halmac_adapter,
1753                 enum halmac_data_type halmac_data_type,
1754                 struct halmac_phy_parameter_info *para_info);
1755         enum halmac_ret_status (*halmac_run_datapack)(
1756                 struct halmac_adapter *halmac_adapter,
1757                 enum halmac_data_type halmac_data_type);
1758         enum halmac_ret_status (*halmac_cfg_drv_info)(
1759                 struct halmac_adapter *halmac_adapter,
1760                 enum halmac_drv_info halmac_drv_info);
1761         enum halmac_ret_status (*halmac_send_bt_coex)(
1762                 struct halmac_adapter *halmac_adapter, u8 *bt_buf, u32 bt_size,
1763                 u8 ack);
1764         enum halmac_ret_status (*halmac_verify_platform_api)(
1765                 struct halmac_adapter *halmac_adapte);
1766         u32 (*halmac_get_fifo_size)(struct halmac_adapter *halmac_adapter,
1767                                     enum hal_fifo_sel halmac_fifo_sel);
1768         enum halmac_ret_status (*halmac_dump_fifo)(
1769                 struct halmac_adapter *halmac_adapter,
1770                 enum hal_fifo_sel halmac_fifo_sel, u32 halmac_start_addr,
1771                 u32 halmac_fifo_dump_size, u8 *fifo_map);
1772         enum halmac_ret_status (*halmac_cfg_txbf)(
1773                 struct halmac_adapter *halmac_adapter, u8 userid,
1774                 enum halmac_bw bw, u8 txbf_en);
1775         enum halmac_ret_status (*halmac_cfg_mumimo)(
1776                 struct halmac_adapter *halmac_adapter,
1777                 struct halmac_cfg_mumimo_para *cfgmu);
1778         enum halmac_ret_status (*halmac_cfg_sounding)(
1779                 struct halmac_adapter *halmac_adapter,
1780                 enum halmac_snd_role role, enum halmac_data_rate datarate);
1781         enum halmac_ret_status (*halmac_del_sounding)(
1782                 struct halmac_adapter *halmac_adapter,
1783                 enum halmac_snd_role role);
1784         enum halmac_ret_status (*halmac_su_bfer_entry_init)(
1785                 struct halmac_adapter *halmac_adapter,
1786                 struct halmac_su_bfer_init_para *su_bfer_init);
1787         enum halmac_ret_status (*halmac_su_bfee_entry_init)(
1788                 struct halmac_adapter *halmac_adapter, u8 userid, u16 paid);
1789         enum halmac_ret_status (*halmac_mu_bfer_entry_init)(
1790                 struct halmac_adapter *halmac_adapter,
1791                 struct halmac_mu_bfer_init_para *mu_bfer_init);
1792         enum halmac_ret_status (*halmac_mu_bfee_entry_init)(
1793                 struct halmac_adapter *halmac_adapter,
1794                 struct halmac_mu_bfee_init_para *mu_bfee_init);
1795         enum halmac_ret_status (*halmac_su_bfer_entry_del)(
1796                 struct halmac_adapter *halmac_adapter, u8 userid);
1797         enum halmac_ret_status (*halmac_su_bfee_entry_del)(
1798                 struct halmac_adapter *halmac_adapter, u8 userid);
1799         enum halmac_ret_status (*halmac_mu_bfer_entry_del)(
1800                 struct halmac_adapter *halmac_adapter);
1801         enum halmac_ret_status (*halmac_mu_bfee_entry_del)(
1802                 struct halmac_adapter *halmac_adapter, u8 userid);
1803         enum halmac_ret_status (*halmac_add_ch_info)(
1804                 struct halmac_adapter *halmac_adapter,
1805                 struct halmac_ch_info *ch_info);
1806         enum halmac_ret_status (*halmac_add_extra_ch_info)(
1807                 struct halmac_adapter *halmac_adapter,
1808                 struct halmac_ch_extra_info *ch_extra_info);
1809         enum halmac_ret_status (*halmac_ctrl_ch_switch)(
1810                 struct halmac_adapter *halmac_adapter,
1811                 struct halmac_ch_switch_option *cs_option);
1812         enum halmac_ret_status (*halmac_p2pps)(
1813                 struct halmac_adapter *halmac_adapter,
1814                 struct halmac_p2pps *p2p_ps);
1815         enum halmac_ret_status (*halmac_clear_ch_info)(
1816                 struct halmac_adapter *halmac_adapter);
1817         enum halmac_ret_status (*halmac_send_general_info)(
1818                 struct halmac_adapter *halmac_adapter,
1819                 struct halmac_general_info *pg_general_info);
1820         enum halmac_ret_status (*halmac_start_iqk)(
1821                 struct halmac_adapter *halmac_adapter,
1822                 struct halmac_iqk_para_ *iqk_para);
1823         enum halmac_ret_status (*halmac_ctrl_pwr_tracking)(
1824                 struct halmac_adapter *halmac_adapter,
1825                 struct halmac_pwr_tracking_option *pwr_tracking_opt);
1826         enum halmac_ret_status (*halmac_psd)(
1827                 struct halmac_adapter *halmac_adapter, u16 start_psd,
1828                 u16 end_psd);
1829         enum halmac_ret_status (*halmac_cfg_tx_agg_align)(
1830                 struct halmac_adapter *halmac_adapter, u8 enable,
1831                 u16 align_size);
1832         enum halmac_ret_status (*halmac_query_status)(
1833                 struct halmac_adapter *halmac_adapter,
1834                 enum halmac_feature_id feature_id,
1835                 enum halmac_cmd_process_status *process_status, u8 *data,
1836                 u32 *size);
1837         enum halmac_ret_status (*halmac_reset_feature)(
1838                 struct halmac_adapter *halmac_adapter,
1839                 enum halmac_feature_id feature_id);
1840         enum halmac_ret_status (*halmac_check_fw_status)(
1841                 struct halmac_adapter *halmac_adapter, bool *fw_status);
1842         enum halmac_ret_status (*halmac_dump_fw_dmem)(
1843                 struct halmac_adapter *halmac_adapter, u8 *dmem, u32 *size);
1844         enum halmac_ret_status (*halmac_cfg_max_dl_size)(
1845                 struct halmac_adapter *halmac_adapter, u32 size);
1846         enum halmac_ret_status (*halmac_cfg_la_mode)(
1847                 struct halmac_adapter *halmac_adapter,
1848                 enum halmac_la_mode la_mode);
1849         enum halmac_ret_status (*halmac_cfg_rx_fifo_expanding_mode)(
1850                 struct halmac_adapter *halmac_adapter,
1851                 enum halmac_rx_fifo_expanding_mode rx_fifo_expanding_mode);
1852         enum halmac_ret_status (*halmac_config_security)(
1853                 struct halmac_adapter *halmac_adapter,
1854                 struct halmac_security_setting *sec_setting);
1855         u8 (*halmac_get_used_cam_entry_num)(
1856                 struct halmac_adapter *halmac_adapter,
1857                 enum hal_security_type sec_type);
1858         enum halmac_ret_status (*halmac_write_cam)(
1859                 struct halmac_adapter *halmac_adapter, u32 entry_index,
1860                 struct halmac_cam_entry_info *cam_entry_info);
1861         enum halmac_ret_status (*halmac_read_cam_entry)(
1862                 struct halmac_adapter *halmac_adapter, u32 entry_index,
1863                 struct halmac_cam_entry_format *content);
1864         enum halmac_ret_status (*halmac_clear_cam_entry)(
1865                 struct halmac_adapter *halmac_adapter, u32 entry_index);
1866         enum halmac_ret_status (*halmac_get_hw_value)(
1867                 struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
1868                 void *pvalue);
1869         enum halmac_ret_status (*halmac_set_hw_value)(
1870                 struct halmac_adapter *halmac_adapter, enum halmac_hw_id hw_id,
1871                 void *pvalue);
1872         enum halmac_ret_status (*halmac_cfg_drv_rsvd_pg_num)(
1873                 struct halmac_adapter *halmac_adapter,
1874                 enum halmac_drv_rsvd_pg_num pg_num);
1875         enum halmac_ret_status (*halmac_get_chip_version)(
1876                 struct halmac_adapter *halmac_adapter,
1877                 struct halmac_ver *version);
1878         enum halmac_ret_status (*halmac_chk_txdesc)(
1879                 struct halmac_adapter *halmac_adapter, u8 *halmac_buf,
1880                 u32 halmac_size);
1881         enum halmac_ret_status (*halmac_dl_drv_rsvd_page)(
1882                 struct halmac_adapter *halmac_adapter, u8 pg_offset,
1883                 u8 *hal_buf, u32 size);
1884         enum halmac_ret_status (*halmac_pcie_switch)(
1885                 struct halmac_adapter *halmac_adapter,
1886                 enum halmac_pcie_cfg pcie_cfg);
1887         enum halmac_ret_status (*halmac_phy_cfg)(
1888                 struct halmac_adapter *halmac_adapter,
1889                 enum halmac_intf_phy_platform platform);
1890         enum halmac_ret_status (*halmac_cfg_csi_rate)(
1891                 struct halmac_adapter *halmac_adapter, u8 rssi, u8 current_rate,
1892                 u8 fixrate_en, u8 *new_rate);
1893         enum halmac_ret_status (*halmac_sdio_cmd53_4byte)(
1894                 struct halmac_adapter *halmac_adapter,
1895                 enum halmac_sdio_cmd53_4byte_mode cmd53_4byte_mode);
1896         enum halmac_ret_status (*halmac_interface_integration_tuning)(
1897                 struct halmac_adapter *halmac_adapter);
1898         enum halmac_ret_status (*halmac_txfifo_is_empty)(
1899                 struct halmac_adapter *halmac_adapter, u32 chk_num);
1900 };
1901
1902 #define HALMAC_GET_API(phalmac_adapter)                                        \
1903         ((struct halmac_api *)phalmac_adapter->halmac_api)
1904
1905 static inline enum halmac_ret_status
1906 halmac_adapter_validate(struct halmac_adapter *halmac_adapter)
1907 {
1908         if ((!halmac_adapter) ||
1909             (halmac_adapter->hal_adapter_backup != halmac_adapter))
1910                 return HALMAC_RET_ADAPTER_INVALID;
1911
1912         return HALMAC_RET_SUCCESS;
1913 }
1914
1915 static inline enum halmac_ret_status
1916 halmac_api_validate(struct halmac_adapter *halmac_adapter)
1917 {
1918         if (halmac_adapter->halmac_state.api_state != HALMAC_API_STATE_INIT)
1919                 return HALMAC_RET_API_INVALID;
1920
1921         return HALMAC_RET_SUCCESS;
1922 }
1923
1924 static inline enum halmac_ret_status
1925 halmac_fw_validate(struct halmac_adapter *halmac_adapter)
1926 {
1927         if (halmac_adapter->halmac_state.dlfw_state != HALMAC_DLFW_DONE &&
1928             halmac_adapter->halmac_state.dlfw_state != HALMAC_GEN_INFO_SENT)
1929                 return HALMAC_RET_NO_DLFW;
1930
1931         return HALMAC_RET_SUCCESS;
1932 }
1933
1934 #endif