1 /******************************************************************************
3 * Copyright(c) 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
25 #ifndef __HALMAC_COM_REG_H__
26 #define __HALMAC_COM_REG_H__
27 /*-------------------------Modification Log-----------------------------------
28 * For Page0, it is based on Combo_And_WL_Only_Page0_Reg.xls SVN524
29 * The supported IC are 8723A, 8881A, 8723B, 8192E, 8881A
30 * 8812A and 8188E is not included in page0 register
32 * For other pages, it is based on MAC_Register.doc SVN502
33 * Most IC is the same with 8812A
34 *-------------------------Modification Log-----------------------------------
37 /*--------------------------Include File--------------------------------------*/
38 /*--------------------------Include File--------------------------------------*/
40 #define REG_SYS_ISO_CTRL 0x0000
42 #define REG_SDIO_TX_CTRL 0x10250000
44 #define REG_SYS_FUNC_EN 0x0002
45 #define REG_SYS_PW_CTRL 0x0004
46 #define REG_SYS_CLK_CTRL 0x0008
47 #define REG_SYS_EEPROM_CTRL 0x000A
48 #define REG_EE_VPD 0x000C
49 #define REG_SYS_SWR_CTRL1 0x0010
50 #define REG_SYS_SWR_CTRL2 0x0014
52 #define REG_SDIO_HIMR 0x10250014
54 #define REG_SYS_SWR_CTRL3 0x0018
56 #define REG_SDIO_HISR 0x10250018
58 #define REG_RSV_CTRL 0x001C
60 #define REG_SDIO_RX_REQ_LEN 0x1025001C
62 #define REG_RF_CTRL 0x001F
64 #define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F
66 #define REG_AFE_LDO_CTRL 0x0020
68 #define REG_SDIO_FREE_TXPG 0x10250020
70 #define REG_AFE_CTRL1 0x0024
72 #define REG_SDIO_FREE_TXPG2 0x10250024
74 #define REG_AFE_CTRL2 0x0028
76 #define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028
78 #define REG_AFE_CTRL3 0x002C
79 #define REG_EFUSE_CTRL 0x0030
81 #define REG_SDIO_HTSFR_INFO 0x10250030
83 #define REG_LDO_EFUSE_CTRL 0x0034
84 #define REG_PWR_OPTION_CTRL 0x0038
86 #define REG_SDIO_HCPWM1_V2 0x10250038
87 #define REG_SDIO_HCPWM2_V2 0x1025003A
89 #define REG_CAL_TIMER 0x003C
90 #define REG_ACLK_MON 0x003E
91 #define REG_GPIO_MUXCFG 0x0040
93 #define REG_SDIO_INDIRECT_REG_CFG 0x10250040
95 #define REG_GPIO_PIN_CTRL 0x0044
97 #define REG_SDIO_INDIRECT_REG_DATA 0x10250044
99 #define REG_GPIO_INTM 0x0048
100 #define REG_LED_CFG 0x004C
101 #define REG_FSIMR 0x0050
102 #define REG_FSISR 0x0054
103 #define REG_HSIMR 0x0058
104 #define REG_HSISR 0x005C
105 #define REG_GPIO_EXT_CTRL 0x0060
107 #define REG_SDIO_H2C 0x10250060
109 #define REG_PAD_CTRL1 0x0064
111 #define REG_SDIO_C2H 0x10250064
113 #define REG_WL_BT_PWR_CTRL 0x0068
115 #define REG_SDM_DEBUG 0x006C
117 #define REG_SYS_SDIO_CTRL 0x0070
119 #define REG_HCI_OPT_CTRL 0x0074
121 #define REG_AFE_CTRL4 0x0078
123 #define REG_LDO_SWR_CTRL 0x007C
125 #define REG_MCUFW_CTRL 0x0080
127 #define REG_SDIO_HRPWM1 0x10250080
128 #define REG_SDIO_HRPWM2 0x10250082
130 #define REG_MCU_TST_CFG 0x0084
132 #define REG_SDIO_HPS_CLKR 0x10250084
133 #define REG_SDIO_BUS_CTRL 0x10250085
135 #define REG_SDIO_HSUS_CTRL 0x10250086
137 #define REG_HMEBOX_E0_E1 0x0088
139 #define REG_SDIO_RESPONSE_TIMER 0x10250088
141 #define REG_SDIO_CMD_CRC 0x1025008A
143 #define REG_HMEBOX_E2_E3 0x008C
144 #define REG_WLLPS_CTRL 0x0090
146 #define REG_SDIO_HSISR 0x10250090
147 #define REG_SDIO_HSIMR 0x10250091
149 #define REG_AFE_CTRL5 0x0094
151 #define REG_GPIO_DEBOUNCE_CTRL 0x0098
152 #define REG_RPWM2 0x009C
153 #define REG_SYSON_FSM_MON 0x00A0
155 #define REG_AFE_CTRL6 0x00A4
157 #define REG_PMC_DBG_CTRL1 0x00A8
159 #define REG_AFE_CTRL7 0x00AC
161 #define REG_HIMR0 0x00B0
162 #define REG_HISR0 0x00B4
163 #define REG_HIMR1 0x00B8
164 #define REG_HISR1 0x00BC
165 #define REG_DBG_PORT_SEL 0x00C0
167 #define REG_SDIO_ERR_RPT 0x102500C0
168 #define REG_SDIO_CMD_ERRCNT 0x102500C1
169 #define REG_SDIO_DATA_ERRCNT 0x102500C2
171 #define REG_PAD_CTRL2 0x00C4
173 #define REG_SDIO_CMD_ERR_CONTENT 0x102500C4
175 #define REG_SDIO_CRC_ERR_IDX 0x102500C9
176 #define REG_SDIO_DATA_CRC 0x102500CA
177 #define REG_SDIO_DATA_REPLY_TIME 0x102500CB
179 #define REG_PMC_DBG_CTRL2 0x00CC
180 #define REG_BIST_CTRL 0x00D0
181 #define REG_BIST_RPT 0x00D4
182 #define REG_MEM_CTRL 0x00D8
184 #define REG_AFE_CTRL8 0x00DC
186 #define REG_USB_SIE_INTF 0x00E0
187 #define REG_PCIE_MIO_INTF 0x00E4
188 #define REG_PCIE_MIO_INTD 0x00E8
190 #define REG_WLRF1 0x00EC
192 #define REG_SYS_CFG1 0x00F0
193 #define REG_SYS_STATUS1 0x00F4
194 #define REG_SYS_STATUS2 0x00F8
195 #define REG_SYS_CFG2 0x00FC
196 #define REG_CR 0x0100
198 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106
200 #define REG_TSF_CLK_STATE 0x0108
201 #define REG_TXDMA_PQ_MAP 0x010C
202 #define REG_TRXFF_BNDY 0x0114
204 #define REG_PTA_I2C_MBOX 0x0118
206 #define REG_RXFF_BNDY 0x011C
208 #define REG_FE1IMR 0x0120
210 #define REG_FE1ISR 0x0124
212 #define REG_CPWM 0x012C
213 #define REG_FWIMR 0x0130
214 #define REG_FWISR 0x0134
215 #define REG_FTIMR 0x0138
216 #define REG_FTISR 0x013C
217 #define REG_PKTBUF_DBG_CTRL 0x0140
218 #define REG_PKTBUF_DBG_DATA_L 0x0144
219 #define REG_PKTBUF_DBG_DATA_H 0x0148
220 #define REG_CPWM2 0x014C
221 #define REG_TC0_CTRL 0x0150
222 #define REG_TC1_CTRL 0x0154
223 #define REG_TC2_CTRL 0x0158
224 #define REG_TC3_CTRL 0x015C
225 #define REG_TC4_CTRL 0x0160
226 #define REG_TCUNIT_BASE 0x0164
227 #define REG_TC5_CTRL 0x0168
228 #define REG_TC6_CTRL 0x016C
229 #define REG_MBIST_FAIL 0x0170
230 #define REG_MBIST_START_PAUSE 0x0174
231 #define REG_MBIST_DONE 0x0178
233 #define REG_MBIST_FAIL_NRML 0x017C
235 #define REG_AES_DECRPT_DATA 0x0180
236 #define REG_AES_DECRPT_CFG 0x0184
238 #define REG_TMETER 0x0190
239 #define REG_OSC_32K_CTRL 0x0194
240 #define REG_32K_CAL_REG1 0x0198
241 #define REG_C2HEVT 0x01A0
243 #define REG_C2HEVT_1 0x01A4
244 #define REG_C2HEVT_2 0x01A8
245 #define REG_C2HEVT_3 0x01AC
247 #define REG_SW_DEFINED_PAGE1 0x01B8
249 #define REG_MCUTST_I 0x01C0
250 #define REG_MCUTST_II 0x01C4
251 #define REG_FMETHR 0x01C8
252 #define REG_HMETFR 0x01CC
253 #define REG_HMEBOX0 0x01D0
254 #define REG_HMEBOX1 0x01D4
255 #define REG_HMEBOX2 0x01D8
256 #define REG_HMEBOX3 0x01DC
257 #define REG_LLT_INIT 0x01E0
259 #define REG_LLT_INIT_ADDR 0x01E4
261 #define REG_BB_ACCESS_CTRL 0x01E8
262 #define REG_BB_ACCESS_DATA 0x01EC
263 #define REG_HMEBOX_E0 0x01F0
264 #define REG_HMEBOX_E1 0x01F4
265 #define REG_HMEBOX_E2 0x01F8
266 #define REG_HMEBOX_E3 0x01FC
268 #define REG_FIFOPAGE_CTRL_1 0x0200
270 #define REG_FIFOPAGE_CTRL_2 0x0204
272 #define REG_AUTO_LLT_V1 0x0208
274 #define REG_TXDMA_OFFSET_CHK 0x020C
275 #define REG_TXDMA_STATUS 0x0210
277 #define REG_TX_DMA_DBG 0x0214
279 #define REG_TQPNT1 0x0218
280 #define REG_TQPNT2 0x021C
282 #define REG_TQPNT3 0x0220
284 #define REG_TQPNT4 0x0224
286 #define REG_RQPN_CTRL_1 0x0228
287 #define REG_RQPN_CTRL_2 0x022C
288 #define REG_FIFOPAGE_INFO_1 0x0230
289 #define REG_FIFOPAGE_INFO_2 0x0234
290 #define REG_FIFOPAGE_INFO_3 0x0238
291 #define REG_FIFOPAGE_INFO_4 0x023C
292 #define REG_FIFOPAGE_INFO_5 0x0240
294 #define REG_H2C_HEAD 0x0244
295 #define REG_H2C_TAIL 0x0248
296 #define REG_H2C_READ_ADDR 0x024C
297 #define REG_H2C_WR_ADDR 0x0250
298 #define REG_H2C_INFO 0x0254
300 #define REG_RXDMA_AGG_PG_TH 0x0280
301 #define REG_RXPKT_NUM 0x0284
302 #define REG_RXDMA_STATUS 0x0288
303 #define REG_RXDMA_DPR 0x028C
304 #define REG_RXDMA_MODE 0x0290
305 #define REG_C2H_PKT 0x0294
307 #define REG_FWFF_C2H 0x0298
308 #define REG_FWFF_CTRL 0x029C
309 #define REG_FWFF_PKT_INFO 0x02A0
311 #define REG_PCIE_CTRL 0x0300
313 #define REG_INT_MIG 0x0304
314 #define REG_BCNQ_TXBD_DESA 0x0308
315 #define REG_MGQ_TXBD_DESA 0x0310
316 #define REG_VOQ_TXBD_DESA 0x0318
317 #define REG_VIQ_TXBD_DESA 0x0320
318 #define REG_BEQ_TXBD_DESA 0x0328
319 #define REG_BKQ_TXBD_DESA 0x0330
320 #define REG_RXQ_RXBD_DESA 0x0338
321 #define REG_HI0Q_TXBD_DESA 0x0340
322 #define REG_HI1Q_TXBD_DESA 0x0348
323 #define REG_HI2Q_TXBD_DESA 0x0350
324 #define REG_HI3Q_TXBD_DESA 0x0358
325 #define REG_HI4Q_TXBD_DESA 0x0360
326 #define REG_HI5Q_TXBD_DESA 0x0368
327 #define REG_HI6Q_TXBD_DESA 0x0370
328 #define REG_HI7Q_TXBD_DESA 0x0378
329 #define REG_MGQ_TXBD_NUM 0x0380
330 #define REG_RX_RXBD_NUM 0x0382
331 #define REG_VOQ_TXBD_NUM 0x0384
332 #define REG_VIQ_TXBD_NUM 0x0386
333 #define REG_BEQ_TXBD_NUM 0x0388
334 #define REG_BKQ_TXBD_NUM 0x038A
335 #define REG_HI0Q_TXBD_NUM 0x038C
336 #define REG_HI1Q_TXBD_NUM 0x038E
337 #define REG_HI2Q_TXBD_NUM 0x0390
338 #define REG_HI3Q_TXBD_NUM 0x0392
339 #define REG_HI4Q_TXBD_NUM 0x0394
340 #define REG_HI5Q_TXBD_NUM 0x0396
341 #define REG_HI6Q_TXBD_NUM 0x0398
342 #define REG_HI7Q_TXBD_NUM 0x039A
343 #define REG_TSFTIMER_HCI 0x039C
344 #define REG_BD_RWPTR_CLR 0x039C
345 #define REG_VOQ_TXBD_IDX 0x03A0
346 #define REG_VIQ_TXBD_IDX 0x03A4
347 #define REG_BEQ_TXBD_IDX 0x03A8
348 #define REG_BKQ_TXBD_IDX 0x03AC
349 #define REG_MGQ_TXBD_IDX 0x03B0
350 #define REG_RXQ_RXBD_IDX 0x03B4
351 #define REG_HI0Q_TXBD_IDX 0x03B8
352 #define REG_HI1Q_TXBD_IDX 0x03BC
353 #define REG_HI2Q_TXBD_IDX 0x03C0
354 #define REG_HI3Q_TXBD_IDX 0x03C4
355 #define REG_HI4Q_TXBD_IDX 0x03C8
356 #define REG_HI5Q_TXBD_IDX 0x03CC
357 #define REG_HI6Q_TXBD_IDX 0x03D0
358 #define REG_HI7Q_TXBD_IDX 0x03D4
360 #define REG_DBG_SEL_V1 0x03D8
362 #define REG_PCIE_HRPWM1_V1 0x03D9
364 #define REG_PCIE_HCPWM1_V1 0x03DA
366 #define REG_PCIE_CTRL2 0x03DB
368 #define REG_PCIE_HRPWM2_V1 0x03DC
370 #define REG_PCIE_HCPWM2_V1 0x03DE
372 #define REG_PCIE_H2C_MSG_V1 0x03E0
374 #define REG_PCIE_C2H_MSG_V1 0x03E4
376 #define REG_DBI_WDATA_V1 0x03E8
378 #define REG_DBI_RDATA_V1 0x03EC
380 #define REG_DBI_FLAG_V1 0x03F0
382 #define REG_MDIO_V1 0x03F4
384 #define REG_PCIE_MIX_CFG 0x03F8
386 #define REG_HCI_MIX_CFG 0x03FC
388 #define REG_Q0_INFO 0x0400
389 #define REG_Q1_INFO 0x0404
390 #define REG_Q2_INFO 0x0408
391 #define REG_Q3_INFO 0x040C
392 #define REG_MGQ_INFO 0x0410
393 #define REG_HIQ_INFO 0x0414
394 #define REG_BCNQ_INFO 0x0418
395 #define REG_TXPKT_EMPTY 0x041A
396 #define REG_CPU_MGQ_INFO 0x041C
397 #define REG_FWHW_TXQ_CTRL 0x0420
399 #define REG_DATAFB_SEL 0x0423
401 #define REG_BCNQ_BDNY_V1 0x0424
403 #define REG_LIFETIME_EN 0x0426
405 #define REG_SPEC_SIFS 0x0428
406 #define REG_RETRY_LIMIT 0x042A
407 #define REG_TXBF_CTRL 0x042C
408 #define REG_DARFRC 0x0430
409 #define REG_RARFRC 0x0438
410 #define REG_RRSR 0x0440
411 #define REG_ARFR0 0x0444
412 #define REG_ARFR1_V1 0x044C
413 #define REG_CCK_CHECK 0x0454
415 #define REG_AMPDU_MAX_TIME_V1 0x0455
417 #define REG_BCNQ1_BDNY_V1 0x0456
419 #define REG_AMPDU_MAX_LENGTH 0x0458
420 #define REG_ACQ_STOP 0x045C
422 #define REG_NDPA_RATE 0x045D
424 #define REG_TX_HANG_CTRL 0x045E
425 #define REG_NDPA_OPT_CTRL 0x045F
427 #define REG_RD_RESP_PKT_TH 0x0463
428 #define REG_CMDQ_INFO 0x0464
429 #define REG_Q4_INFO 0x0468
430 #define REG_Q5_INFO 0x046C
431 #define REG_Q6_INFO 0x0470
432 #define REG_Q7_INFO 0x0474
434 #define REG_WMAC_LBK_BUF_HD_V1 0x0478
435 #define REG_MGQ_BDNY_V1 0x047A
437 #define REG_TXRPT_CTRL 0x047C
438 #define REG_INIRTS_RATE_SEL 0x0480
439 #define REG_BASIC_CFEND_RATE 0x0481
440 #define REG_STBC_CFEND_RATE 0x0482
441 #define REG_DATA_SC 0x0483
442 #define REG_MACID_SLEEP3 0x0484
443 #define REG_MACID_SLEEP1 0x0488
444 #define REG_ARFR2_V1 0x048C
445 #define REG_ARFR3_V1 0x0494
446 #define REG_ARFR4 0x049C
447 #define REG_ARFR5 0x04A4
448 #define REG_TXRPT_START_OFFSET 0x04AC
450 #define REG_POWER_STAGE1 0x04B4
452 #define REG_POWER_STAGE2 0x04B8
454 #define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC
455 #define REG_PKT_LIFE_TIME 0x04C0
456 #define REG_STBC_SETTING 0x04C4
457 #define REG_STBC_SETTING2 0x04C5
458 #define REG_QUEUE_CTRL 0x04C6
459 #define REG_SINGLE_AMPDU_CTRL 0x04C7
460 #define REG_PROT_MODE_CTRL 0x04C8
461 #define REG_BAR_MODE_CTRL 0x04CC
462 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF
463 #define REG_MACID_SLEEP2 0x04D0
464 #define REG_MACID_SLEEP 0x04D4
466 #define REG_HW_SEQ0 0x04D8
467 #define REG_HW_SEQ1 0x04DA
468 #define REG_HW_SEQ2 0x04DC
469 #define REG_HW_SEQ3 0x04DE
471 #define REG_NULL_PKT_STATUS_V1 0x04E0
473 #define REG_PTCL_ERR_STATUS 0x04E2
475 #define REG_NULL_PKT_STATUS_EXTEND 0x04E3
477 #define REG_VIDEO_ENHANCEMENT_FUN 0x04E4
479 #define REG_BT_POLLUTE_PKT_CNT 0x04E8
480 #define REG_PTCL_DBG 0x04EC
482 #define REG_CPUMGQ_TIMER_CTRL2 0x04F4
484 #define REG_DUMMY_PAGE4_V1 0x04FC
485 #define REG_MOREDATA 0x04FE
487 #define REG_EDCA_VO_PARAM 0x0500
488 #define REG_EDCA_VI_PARAM 0x0504
489 #define REG_EDCA_BE_PARAM 0x0508
490 #define REG_EDCA_BK_PARAM 0x050C
491 #define REG_BCNTCFG 0x0510
492 #define REG_PIFS 0x0512
493 #define REG_RDG_PIFS 0x0513
494 #define REG_SIFS 0x0514
495 #define REG_TSFTR_SYN_OFFSET 0x0518
496 #define REG_AGGR_BREAK_TIME 0x051A
497 #define REG_SLOT 0x051B
498 #define REG_TX_PTCL_CTRL 0x0520
499 #define REG_TXPAUSE 0x0522
500 #define REG_DIS_TXREQ_CLR 0x0523
501 #define REG_RD_CTRL 0x0524
502 #define REG_MBSSID_CTRL 0x0526
503 #define REG_P2PPS_CTRL 0x0527
504 #define REG_PKT_LIFETIME_CTRL 0x0528
505 #define REG_P2PPS_SPEC_STATE 0x052B
507 #define REG_BAR_TX_CTRL 0x0530
509 #define REG_QUEUE_INCOL_THR 0x0538
510 #define REG_QUEUE_INCOL_EN 0x053C
512 #define REG_TBTT_PROHIBIT 0x0540
513 #define REG_P2PPS_STATE 0x0543
514 #define REG_RD_NAV_NXT 0x0544
515 #define REG_NAV_PROT_LEN 0x0546
517 #define REG_BCN_CTRL 0x0550
519 #define REG_BCN_CTRL_CLINT0 0x0551
521 #define REG_MBID_NUM 0x0552
522 #define REG_DUAL_TSF_RST 0x0553
523 #define REG_MBSSID_BCN_SPACE 0x0554
524 #define REG_DRVERLYINT 0x0558
525 #define REG_BCNDMATIM 0x0559
526 #define REG_ATIMWND 0x055A
527 #define REG_USTIME_TSF 0x055C
528 #define REG_BCN_MAX_ERR 0x055D
529 #define REG_RXTSF_OFFSET_CCK 0x055E
530 #define REG_RXTSF_OFFSET_OFDM 0x055F
531 #define REG_TSFTR 0x0560
533 #define REG_FREERUN_CNT 0x0568
535 #define REG_ATIMWND1_V1 0x0570
537 #define REG_TBTT_PROHIBIT_INFRA 0x0571
539 #define REG_CTWND 0x0572
540 #define REG_BCNIVLCUNT 0x0573
541 #define REG_BCNDROPCTRL 0x0574
542 #define REG_HGQ_TIMEOUT_PERIOD 0x0575
544 #define REG_TXCMD_TIMEOUT_PERIOD 0x0576
545 #define REG_MISC_CTRL 0x0577
546 #define REG_BCN_CTRL_CLINT1 0x0578
547 #define REG_BCN_CTRL_CLINT2 0x0579
548 #define REG_BCN_CTRL_CLINT3 0x057A
550 #define REG_EXTEND_CTRL 0x057B
552 #define REG_P2PPS1_SPEC_STATE 0x057C
553 #define REG_P2PPS1_STATE 0x057D
554 #define REG_P2PPS2_SPEC_STATE 0x057E
555 #define REG_P2PPS2_STATE 0x057F
557 #define REG_PS_TIMER0 0x0580
559 #define REG_PS_TIMER1 0x0584
561 #define REG_PS_TIMER2 0x0588
563 #define REG_TBTT_CTN_AREA 0x058C
564 #define REG_FORCE_BCN_IFS 0x058E
565 #define REG_TXOP_MIN 0x0590
566 #define REG_PRE_BKF_TIME 0x0592
567 #define REG_CROSS_TXOP_CTRL 0x0593
569 #define REG_ATIMWND2 0x05A0
570 #define REG_ATIMWND3 0x05A1
571 #define REG_ATIMWND4 0x05A2
572 #define REG_ATIMWND5 0x05A3
573 #define REG_ATIMWND6 0x05A4
574 #define REG_ATIMWND7 0x05A5
575 #define REG_ATIMUGT 0x05A6
576 #define REG_HIQ_NO_LMT_EN 0x05A7
577 #define REG_DTIM_COUNTER_ROOT 0x05A8
578 #define REG_DTIM_COUNTER_VAP1 0x05A9
579 #define REG_DTIM_COUNTER_VAP2 0x05AA
580 #define REG_DTIM_COUNTER_VAP3 0x05AB
581 #define REG_DTIM_COUNTER_VAP4 0x05AC
582 #define REG_DTIM_COUNTER_VAP5 0x05AD
583 #define REG_DTIM_COUNTER_VAP6 0x05AE
584 #define REG_DTIM_COUNTER_VAP7 0x05AF
585 #define REG_DIS_ATIM 0x05B0
587 #define REG_EARLY_128US 0x05B1
588 #define REG_P2PPS1_CTRL 0x05B2
589 #define REG_P2PPS2_CTRL 0x05B3
590 #define REG_TIMER0_SRC_SEL 0x05B4
591 #define REG_NOA_UNIT_SEL 0x05B5
592 #define REG_P2POFF_DIS_TXTIME 0x05B7
593 #define REG_MBSSID_BCN_SPACE2 0x05B8
594 #define REG_MBSSID_BCN_SPACE3 0x05BC
596 #define REG_ACMHWCTRL 0x05C0
597 #define REG_ACMRSTCTRL 0x05C1
598 #define REG_ACMAVG 0x05C2
599 #define REG_VO_ADMTIME 0x05C4
600 #define REG_VI_ADMTIME 0x05C6
601 #define REG_BE_ADMTIME 0x05C8
602 #define REG_EDCA_RANDOM_GEN 0x05CC
603 #define REG_TXCMD_NOA_SEL 0x05CF
604 #define REG_NOA_PARAM 0x05E0
606 #define REG_P2P_RST 0x05F0
607 #define REG_SCHEDULER_RST 0x05F1
609 #define REG_SCH_TXCMD 0x05F8
610 #define REG_PAGE5_DUMMY 0x05FC
611 #define REG_WMAC_CR 0x0600
613 #define REG_WMAC_FWPKT_CR 0x0601
615 #define REG_BWOPMODE 0x0603
617 #define REG_TCR 0x0604
618 #define REG_RCR 0x0608
619 #define REG_RX_PKT_LIMIT 0x060C
620 #define REG_RX_DLK_TIME 0x060D
621 #define REG_RX_DRVINFO_SZ 0x060F
622 #define REG_MACID 0x0610
623 #define REG_BSSID 0x0618
624 #define REG_MAR 0x0620
625 #define REG_MBIDCAMCFG_1 0x0628
626 #define REG_MBIDCAMCFG_2 0x062C
628 #define REG_WMAC_TCR_TSFT_OFS 0x0630
629 #define REG_UDF_THSD 0x0632
630 #define REG_ZLD_NUM 0x0633
632 #define REG_STMP_THSD 0x0634
633 #define REG_WMAC_TXTIMEOUT 0x0635
634 #define REG_MCU_TEST_2_V1 0x0636
636 #define REG_USTIME_EDCA 0x0638
638 #define REG_MAC_SPEC_SIFS 0x063A
639 #define REG_RESP_SIFS_CCK 0x063C
640 #define REG_RESP_SIFS_OFDM 0x063E
641 #define REG_ACKTO 0x0640
642 #define REG_CTS2TO 0x0641
643 #define REG_EIFS 0x0642
645 #define REG_NAV_CTRL 0x0650
646 #define REG_BACAMCMD 0x0654
647 #define REG_BACAMCONTENT 0x0658
648 #define REG_LBDLY 0x0660
650 #define REG_WMAC_BACAM_RPMEN 0x0661
652 #define REG_TX_RX 0x0662
654 #define REG_WMAC_BITMAP_CTL 0x0663
656 #define REG_RXERR_RPT 0x0664
657 #define REG_WMAC_TRXPTCL_CTL 0x0668
658 #define REG_CAMCMD 0x0670
659 #define REG_CAMWRITE 0x0674
660 #define REG_CAMREAD 0x0678
661 #define REG_CAMDBG 0x067C
662 #define REG_SECCFG 0x0680
664 #define REG_RXFILTER_CATEGORY_1 0x0682
665 #define REG_RXFILTER_ACTION_1 0x0683
666 #define REG_RXFILTER_CATEGORY_2 0x0684
667 #define REG_RXFILTER_ACTION_2 0x0685
668 #define REG_RXFILTER_CATEGORY_3 0x0686
669 #define REG_RXFILTER_ACTION_3 0x0687
670 #define REG_RXFLTMAP3 0x0688
671 #define REG_RXFLTMAP4 0x068A
672 #define REG_RXFLTMAP5 0x068C
673 #define REG_RXFLTMAP6 0x068E
675 #define REG_WOW_CTRL 0x0690
677 #define REG_NAN_RX_TSF_FILTER 0x0691
679 #define REG_PS_RX_INFO 0x0692
680 #define REG_WMMPS_UAPSD_TID 0x0693
681 #define REG_LPNAV_CTRL 0x0694
683 #define REG_WKFMCAM_CMD 0x0698
684 #define REG_WKFMCAM_RWD 0x069C
686 #define REG_RXFLTMAP0 0x06A0
687 #define REG_RXFLTMAP1 0x06A2
688 #define REG_RXFLTMAP 0x06A4
689 #define REG_BCN_PSR_RPT 0x06A8
691 #define REG_FLC_RPC 0x06AC
692 #define REG_FLC_RPCT 0x06AD
693 #define REG_FLC_PTS 0x06AE
694 #define REG_FLC_TRPC 0x06AF
696 #define REG_RXPKTMON_CTRL 0x06B0
698 #define REG_STATE_MON 0x06B4
700 #define REG_ERROR_MON 0x06B8
701 #define REG_SEARCH_MACID 0x06BC
703 #define REG_BT_COEX_TABLE 0x06C0
705 #define REG_RXCMD_0 0x06D0
706 #define REG_RXCMD_1 0x06D4
708 #define REG_WMAC_RESP_TXINFO 0x06D8
710 #define REG_BBPSF_CTRL 0x06DC
712 #define REG_P2P_RX_BCN_NOA 0x06E0
713 #define REG_ASSOCIATED_BFMER0_INFO 0x06E4
714 #define REG_ASSOCIATED_BFMER1_INFO 0x06EC
715 #define REG_TX_CSI_RPT_PARAM_BW20 0x06F4
716 #define REG_TX_CSI_RPT_PARAM_BW40 0x06F8
717 #define REG_TX_CSI_RPT_PARAM_BW80 0x06FC
718 #define REG_MACID1 0x0700
720 #define REG_BSSID1 0x0708
722 #define REG_BCN_PSR_RPT1 0x0710
723 #define REG_ASSOCIATED_BFMEE_SEL 0x0714
724 #define REG_SND_PTCL_CTRL 0x0718
725 #define REG_RX_CSI_RPT_INFO 0x071C
726 #define REG_NS_ARP_CTRL 0x0720
727 #define REG_NS_ARP_INFO 0x0724
729 #define REG_BEAMFORMING_INFO_NSARP_V1 0x0728
731 #define REG_BEAMFORMING_INFO_NSARP 0x072C
733 #define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750
735 #define REG_WMAC_SWAES_CFG 0x0760
737 #define REG_BT_COEX_V2 0x0762
739 #define REG_BT_COEX 0x0764
741 #define REG_WLAN_ACT_MASK_CTRL 0x0768
743 #define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E
745 #define REG_BT_ACT_STATISTICS 0x0770
747 #define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778
749 #define REG_BT_STATUS_REPORT_REGISTER 0x077C
751 #define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780
753 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784
755 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785
757 #define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F
759 #define REG_BT_TDMA_TIME_REGISTER 0x0790
761 #define REG_BT_ACT_REGISTER 0x0794
763 #define REG_OBFF_CTRL_BASIC 0x0798
765 #define REG_OBFF_CTRL2_TIMER 0x079C
767 #define REG_LTR_CTRL_BASIC 0x07A0
769 #define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4
771 #define REG_LTR_IDLE_LATENCY_V1 0x07A8
772 #define REG_LTR_ACTIVE_LATENCY_V1 0x07AC
774 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0
776 #define REG_WMAC_PKTCNT_RWD 0x07B8
777 #define REG_WMAC_PKTCNT_CTRL 0x07BC
779 #define REG_IQ_DUMP 0x07C0
781 #define REG_WMAC_FTM_CTL 0x07CC
783 #define REG_WMAC_IQ_MDPK_FUNC 0x07CE
785 #define REG_WMAC_OPTION_FUNCTION 0x07D0
787 #define REG_RX_FILTER_FUNCTION 0x07DA
789 #define REG_NDP_SIG 0x07E0
790 #define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4
792 #define REG_RTS_ADDRESS_0 0x07F0
794 #define REG_RTS_ADDRESS_1 0x07F8
796 #define REG__RPFM_MAP1 0x07FE
798 #define REG_SYS_CFG3 0x1000
799 #define REG_SYS_CFG4 0x1034
801 #define REG_SYS_CFG5 0x1070
803 #define REG_CPU_DMEM_CON 0x1080
805 #define REG_BOOT_REASON 0x1088
806 #define REG_NFCPAD_CTRL 0x10A8
808 #define REG_HIMR2 0x10B0
809 #define REG_HISR2 0x10B4
810 #define REG_HIMR3 0x10B8
811 #define REG_HISR3 0x10BC
812 #define REG_SW_MDIO 0x10C0
813 #define REG_SW_FLUSH 0x10C4
815 #define REG_H2C_PKT_READADDR 0x10D0
816 #define REG_H2C_PKT_WRITEADDR 0x10D4
818 #define REG_MEM_PWR_CRTL 0x10D8
820 #define REG_FW_DBG0 0x10E0
821 #define REG_FW_DBG1 0x10E4
822 #define REG_FW_DBG2 0x10E8
823 #define REG_FW_DBG3 0x10EC
824 #define REG_FW_DBG4 0x10F0
825 #define REG_FW_DBG5 0x10F4
826 #define REG_FW_DBG6 0x10F8
827 #define REG_FW_DBG7 0x10FC
828 #define REG_CR_EXT 0x1100
829 #define REG_FWFF 0x1114
831 #define REG_RXFF_PTR_V1 0x1118
832 #define REG_RXFF_WTR_V1 0x111C
834 #define REG_FE2IMR 0x1120
835 #define REG_FE2ISR 0x1124
836 #define REG_FE3IMR 0x1128
837 #define REG_FE3ISR 0x112C
838 #define REG_FE4IMR 0x1130
839 #define REG_FE4ISR 0x1134
840 #define REG_FT1IMR 0x1138
841 #define REG_FT1ISR 0x113C
842 #define REG_SPWR0 0x1140
843 #define REG_SPWR1 0x1144
844 #define REG_SPWR2 0x1148
845 #define REG_SPWR3 0x114C
846 #define REG_POWSEQ 0x1150
848 #define REG_TC7_CTRL_V1 0x1158
849 #define REG_TC8_CTRL_V1 0x115C
851 #define REG_FT2IMR 0x11E0
852 #define REG_FT2ISR 0x11E4
854 #define REG_MSG2 0x11F0
855 #define REG_MSG3 0x11F4
856 #define REG_MSG4 0x11F8
857 #define REG_MSG5 0x11FC
858 #define REG_DDMA_CH0SA 0x1200
859 #define REG_DDMA_CH0DA 0x1204
860 #define REG_DDMA_CH0CTRL 0x1208
861 #define REG_DDMA_CH1SA 0x1210
862 #define REG_DDMA_CH1DA 0x1214
863 #define REG_DDMA_CH1CTRL 0x1218
864 #define REG_DDMA_CH2SA 0x1220
865 #define REG_DDMA_CH2DA 0x1224
866 #define REG_DDMA_CH2CTRL 0x1228
867 #define REG_DDMA_CH3SA 0x1230
868 #define REG_DDMA_CH3DA 0x1234
869 #define REG_DDMA_CH3CTRL 0x1238
870 #define REG_DDMA_CH4SA 0x1240
871 #define REG_DDMA_CH4DA 0x1244
872 #define REG_DDMA_CH4CTRL 0x1248
873 #define REG_DDMA_CH5SA 0x1250
874 #define REG_DDMA_CH5DA 0x1254
876 #define REG_REG_DDMA_CH5CTRL 0x1258
878 #define REG_DDMA_INT_MSK 0x12E0
879 #define REG_DDMA_CHSTATUS 0x12E8
880 #define REG_DDMA_CHKSUM 0x12F0
881 #define REG_DDMA_MONITOR 0x12FC
883 #define REG_STC_INT_CS 0x1300
884 #define REG_ST_INT_CFG 0x1304
885 #define REG_CMU_DLY_CTRL 0x1310
886 #define REG_CMU_DLY_CFG 0x1314
887 #define REG_H2CQ_TXBD_DESA 0x1320
888 #define REG_H2CQ_TXBD_NUM 0x1328
889 #define REG_H2CQ_TXBD_IDX 0x132C
890 #define REG_H2CQ_CSR 0x1330
892 #define REG_CHANGE_PCIE_SPEED 0x1350
894 #define REG_OLD_DEHANG 0x13F4
896 #define REG_Q0_Q1_INFO 0x1400
897 #define REG_Q2_Q3_INFO 0x1404
898 #define REG_Q4_Q5_INFO 0x1408
899 #define REG_Q6_Q7_INFO 0x140C
900 #define REG_MGQ_HIQ_INFO 0x1410
901 #define REG_CMDQ_BCNQ_INFO 0x1414
902 #define REG_USEREG_SETTING 0x1420
903 #define REG_AESIV_SETTING 0x1424
904 #define REG_BF0_TIME_SETTING 0x1428
905 #define REG_BF1_TIME_SETTING 0x142C
906 #define REG_BF_TIMEOUT_EN 0x1430
907 #define REG_MACID_RELEASE0 0x1434
908 #define REG_MACID_RELEASE1 0x1438
909 #define REG_MACID_RELEASE2 0x143C
910 #define REG_MACID_RELEASE3 0x1440
911 #define REG_MACID_RELEASE_SETTING 0x1444
912 #define REG_FAST_EDCA_VOVI_SETTING 0x1448
913 #define REG_FAST_EDCA_BEBK_SETTING 0x144C
914 #define REG_MACID_DROP0 0x1450
915 #define REG_MACID_DROP1 0x1454
916 #define REG_MACID_DROP2 0x1458
917 #define REG_MACID_DROP3 0x145C
919 #define REG_R_MACID_RELEASE_SUCCESS_0 0x1460
920 #define REG_R_MACID_RELEASE_SUCCESS_1 0x1464
921 #define REG_R_MACID_RELEASE_SUCCESS_2 0x1468
922 #define REG_R_MACID_RELEASE_SUCCESS_3 0x146C
923 #define REG_MGG_FIFO_CRTL 0x1470
924 #define REG_MGG_FIFO_INT 0x1474
925 #define REG_MGG_FIFO_LIFETIME 0x1478
926 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C
928 #define REG_MACID_SHCUT_OFFSET 0x1480
930 #define REG_MU_TX_CTL 0x14C0
931 #define REG_MU_STA_GID_VLD 0x14C4
932 #define REG_MU_STA_USER_POS_INFO 0x14C8
933 #define REG_MU_TRX_DBG_CNT 0x14D0
935 #define REG_CPUMGQ_TX_TIMER 0x1500
936 #define REG_PS_TIMER_A 0x1504
937 #define REG_PS_TIMER_B 0x1508
938 #define REG_PS_TIMER_C 0x150C
939 #define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510
940 #define REG_CPUMGQ_TX_TIMER_EARLY 0x1514
941 #define REG_PS_TIMER_A_EARLY 0x1515
942 #define REG_PS_TIMER_B_EARLY 0x1516
943 #define REG_PS_TIMER_C_EARLY 0x1517
945 #define REG_BCN_PSR_RPT2 0x1600
946 #define REG_BCN_PSR_RPT3 0x1604
947 #define REG_BCN_PSR_RPT4 0x1608
948 #define REG_A1_ADDR_MASK 0x160C
949 #define REG_MACID2 0x1620
950 #define REG_BSSID2 0x1628
951 #define REG_MACID3 0x1630
952 #define REG_BSSID3 0x1638
953 #define REG_MACID4 0x1640
954 #define REG_BSSID4 0x1648
956 #define REG_NOA_REPORT 0x1650
957 #define REG_PWRBIT_SETTING 0x1660
958 #define REG_WMAC_MU_BF_OPTION 0x167C
960 #define REG_WMAC_MU_ARB 0x167E
961 #define REG_WMAC_MU_OPTION 0x167F
962 #define REG_WMAC_MU_BF_CTL 0x1680
964 #define REG_WMAC_MU_BFRPT_PARA 0x1682
966 #define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684
967 #define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686
968 #define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688
969 #define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A
970 #define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C
971 #define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E
973 #define REG_TRANSMIT_ADDRSS_0 0x16A0
974 #define REG_TRANSMIT_ADDRSS_1 0x16A8
975 #define REG_TRANSMIT_ADDRSS_2 0x16B0
976 #define REG_TRANSMIT_ADDRSS_3 0x16B8
977 #define REG_TRANSMIT_ADDRSS_4 0x16C0
979 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700
980 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704
981 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708
983 /* ----------------------------------------------------- */
985 /* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */
987 /* ----------------------------------------------------- */
988 #define REG_RXPKTBUF_STARTADDR 0xFB00
989 #define REG_TXPKTBUF_STARTADDR 0xFC00
991 /* ----------------------------------------------------- */
993 /* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */
995 /* ----------------------------------------------------- */
996 #define REG_SYS_CTRL 0xFD00
997 #define REG_PONSTS_RPT1 0xFD01
998 #define REG_PONSTS_RPT2 0xFD02
999 #define REG_PONSTS_RPT3 0xFD03
1000 #define REG_PONSTS_RPT4 0xFD04 /* 0x84 */
1001 #define REG_PONSTS_RPT5 0xFD05 /* 0x85 */
1002 #define REG_8051ERRFLAG 0xFD08
1003 #define REG_8051ERRFLAG_MASK 0xFD09
1004 #define REG_TXADDRH 0xFD10 /* Tx Packet High address */
1005 #define REG_RXADDRH 0xFD11 /* Rx Packet High address */
1006 #define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf
1007 * high64k as external register
1010 #define REG_U3_STATE 0xFD48 /* (Read only)
1011 * [7:4] : usb3 changed last state.
1012 * [3:0] : usb3 state
1016 #define REG_OUTDATA0 0xFD50
1017 #define REG_OUTDATA1 0xFD54
1018 #define REG_OUTRDY 0xFD58 /* bit[0] : OutReady,
1019 * bit[1] : OutEmptyIntEn
1022 #define REG_INDATA0 0xFD60
1023 #define REG_INDATA1 0xFD64
1024 #define REG_INRDY 0xFD68 /* bit[0] : InReady,
1025 * bit[1] : InRdyIntEn
1028 /* MCU ERROR debug REG */
1029 #define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */
1030 #define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */
1031 #define REG_MCUERR_ACC 0xFD92
1032 #define REG_MCUERR_B 0xFD93
1033 #define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */
1034 #define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */
1035 #define REG_MCUERR_SP 0xFD96 /* SP[7:0] */
1036 #define REG_MCUERR_IE 0xFD97 /* IE[7:0] */
1037 #define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */
1038 #define REG_VERA_SIM 0xFD9F
1039 /* 0xFD99~0xFD9F are reserved.. */
1041 /* ----------------------------------------------------- */
1043 /* 0xFE00h ~ 0xFEFFh USB Configuration */
1045 /* ----------------------------------------------------- */
1047 /* RTS5101 USB Register Definition */
1048 #define REG_USB_SETUP_DEC_INT 0xFE00
1049 #define REG_USB_DMACTL 0xFE01
1050 #define REG_USB_IRQSTAT0 0xFE02
1051 #define REG_USB_IRQSTAT1 0xFE03
1052 #define REG_USB_IRQEN0 0xFE04
1053 #define REG_USB_IRQEN1 0xFE05
1054 #define REG_USB_AUTOPTRL 0xFE06
1055 #define REG_USB_AUTOPTRH 0xFE07
1056 #define REG_USB_AUTODAT 0xFE08
1058 #define REG_USB_SCRATCH0 0xFE09
1059 #define REG_USB_SCRATCH1 0xFE0A
1060 #define REG_USB_SEEPROM 0xFE0B
1061 #define REG_USB_GPIO0 0xFE0C
1062 #define REG_USB_GPIO0DIR 0xFE0D
1063 #define REG_USB_CLKSEL 0xFE0E
1064 #define REG_USB_BOOTCTL 0xFE0F
1066 #define REG_USB_USBCTL 0xFE10
1067 #define REG_USB_USBSTAT 0xFE11
1068 #define REG_USB_DEVADDR 0xFE12
1069 #define REG_USB_USBTEST 0xFE13
1070 #define REG_USB_FNUM0 0xFE14
1071 #define REG_USB_FNUM1 0xFE15
1073 #define REG_USB_EP_IDX 0xFE20
1074 #define REG_USB_EP_CFG 0xFE21
1075 #define REG_USB_EP_CTL 0xFE22
1076 #define REG_USB_EP_STAT 0xFE23
1077 #define REG_USB_EP_IRQ 0xFE24
1078 #define REG_USB_EP_IRQEN 0xFE25
1079 #define REG_USB_EP_MAXPKT0 0xFE26
1080 #define REG_USB_EP_MAXPKT1 0xFE27
1081 #define REG_USB_EP_DAT 0xFE28
1082 #define REG_USB_EP_BC0 0xFE29
1083 #define REG_USB_EP_BC1 0xFE2A
1084 #define REG_USB_EP_TC0 0xFE2B
1085 #define REG_USB_EP_TC1 0xFE2C
1086 #define REG_USB_EP_TC2 0xFE2D
1087 #define REG_USB_EP_CTL2 0xFE2E
1089 #define REG_USB_INFO 0xFE17
1090 #define REG_USB_SPECIAL_OPTION 0xFE55
1091 #define REG_USB_DMA_AGG_TO 0xFE5B
1092 #define REG_USB_AGG_TO 0xFE5C
1093 #define REG_USB_AGG_TH 0xFE5D
1095 #define REG_USB_VID 0xFE60
1096 #define REG_USB_PID 0xFE62
1097 #define REG_USB_OPT 0xFE64
1098 #define REG_USB_CONFIG 0xFE65 /* RX EP setting.
1099 * 0xFE65 Bit[3:0] : RXQ,
1103 * 0xFE66 Bit[3:0] : TXQ0,
1105 * 0xFE67 Bit[3:0] : TXQ2
1107 #define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]),
1108 * Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0])
1110 #define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]),
1111 * Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]),
1112 * Bit[1]: SE0_LVL (USB PHY 0xE5[7]),
1113 * Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1])
1115 #define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]),
1116 * Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]),
1117 * Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]),
1118 * Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]),
1119 * Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1])
1121 #define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */
1122 #define REG_USB_OPT2 0xFE6C
1123 #define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
1124 #define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max: 32 bytes*/
1125 #define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max: 48 bytes*/
1126 #define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max: 12 bytes*/
1128 #define REG_USB_ALTERNATE_SETTING 0xFE4F
1129 #define REG_USB_INT_BINTERVAL 0xFE6E
1130 #define REG_USB_GPS_EP_CONFIG 0xFE6D
1132 #endif /* __HALMAC_COM_REG_H__ */