1 /******************************************************************************
3 * Copyright(c) 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
25 #ifndef HALMAC_POWER_SEQUENCE_CMD
26 #define HALMAC_POWER_SEQUENCE_CMD
28 #include "halmac_2_platform.h"
29 #include "halmac_type.h"
31 #define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000
33 /* The value of cmd : 4 bits */
35 /* offset : the read register offset
36 * msk : the mask of the read value
37 * value : N/A, left by 0
38 * Note : dirver shall implement this function by read & msk
40 #define HALMAC_PWR_CMD_READ 0x00
42 * offset: the read register offset
43 * msk: the mask of the write bits
45 * Note: driver shall implement this cmd by read & msk after write
47 #define HALMAC_PWR_CMD_WRITE 0x01
48 /* offset: the read register offset
49 * msk: the mask of the polled value
50 * value: the value to be polled, masked by the msd field.
51 * Note: driver shall implement this cmd by
53 * if( (Read(offset) & msk) == (value & msk) )
55 * } while(not timeout);
57 #define HALMAC_PWR_CMD_POLLING 0x02
58 /* offset: the value to delay
60 * value: the unit of delay, 0: us, 1: ms
62 #define HALMAC_PWR_CMD_DELAY 0x03
67 #define HALMAC_PWR_CMD_END 0x04
69 /* The value of base : 4 bits */
71 /* define the base address of each block */
72 #define HALMAC_PWR_BASEADDR_MAC 0x00
73 #define HALMAC_PWR_BASEADDR_USB 0x01
74 #define HALMAC_PWR_BASEADDR_PCIE 0x02
75 #define HALMAC_PWR_BASEADDR_SDIO 0x03
77 /* The value of interface_msk : 4 bits */
78 #define HALMAC_PWR_INTF_SDIO_MSK BIT(0)
79 #define HALMAC_PWR_INTF_USB_MSK BIT(1)
80 #define HALMAC_PWR_INTF_PCI_MSK BIT(2)
81 #define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
83 /* The value of fab_msk : 4 bits */
84 #define HALMAC_PWR_FAB_TSMC_MSK BIT(0)
85 #define HALMAC_PWR_FAB_UMC_MSK BIT(1)
86 #define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
88 /* The value of cut_msk : 8 bits */
89 #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0)
90 #define HALMAC_PWR_CUT_A_MSK BIT(1)
91 #define HALMAC_PWR_CUT_B_MSK BIT(2)
92 #define HALMAC_PWR_CUT_C_MSK BIT(3)
93 #define HALMAC_PWR_CUT_D_MSK BIT(4)
94 #define HALMAC_PWR_CUT_E_MSK BIT(5)
95 #define HALMAC_PWR_CUT_F_MSK BIT(6)
96 #define HALMAC_PWR_CUT_G_MSK BIT(7)
97 #define HALMAC_PWR_CUT_ALL_MSK 0xFF
99 enum halmac_pwrseq_cmd_delay_unit_ {
100 HALMAC_PWRSEQ_DELAY_US,
101 HALMAC_PWRSEQ_DELAY_MS,
104 /*Don't care endian issue, because element of pwer seq vector is fixed address*/
105 struct halmac_wl_pwr_cfg_ {
109 u8 interface_msk : 4;