1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
13 u8 ampdu_enable;/* for enable Tx A-MPDU */
14 u8 tx_amsdu_enable;/* for enable Tx A-MSDU */
15 u8 bss_coexist;/* for 20/40 Bss coexist */
17 /* u8 baddbareq_issued[16]; */
18 u32 tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
19 u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
21 u8 rx_ampdu_min_spacing;
23 u8 ch_offset;/* PRIME_CHNL_OFFSET */
27 /* for processing Tx A-MPDU */
29 /* u8 ADDBA_retry_count; */
30 u8 candidate_tid_bitmap;
36 struct ieee80211_ht_cap ht_cap;
48 RT_HT_CAP_USE_TURBO_AGGR = 0x01,
49 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02,
50 RT_HT_CAP_USE_AMPDU = 0x04,
51 RT_HT_CAP_USE_WOW = 0x8,
52 RT_HT_CAP_USE_SOFTAP = 0x10,
53 RT_HT_CAP_USE_92SE = 0x20,
54 RT_HT_CAP_USE_88C_92C = 0x40,
55 RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */
59 RT_HT_CAP_USE_VIDEO_CLIENT = 0x01,
60 RT_HT_CAP_USE_JAGUAR_BCUT = 0x02,
61 RT_HT_CAP_USE_JAGUAR_CCUT = 0x04,
64 #define LDPC_HT_ENABLE_RX BIT0
65 #define LDPC_HT_ENABLE_TX BIT1
66 #define LDPC_HT_TEST_TX_ENABLE BIT2
67 #define LDPC_HT_CAP_TX BIT3
69 #define STBC_HT_ENABLE_RX BIT0
70 #define STBC_HT_ENABLE_TX BIT1
71 #define STBC_HT_TEST_TX_ENABLE BIT2
72 #define STBC_HT_CAP_TX BIT3
74 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
75 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
76 #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */
79 /* The HT Control field */
81 #define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 2, _val)
82 #define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+3, 0, 1, _val)
83 #define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+3, 0, 1)
85 /* 20/40 BSS Coexist */
86 #define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart), 0, 1, _val)
87 #define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart), 0, 1)
90 #define GET_HT_CAPABILITY_ELE_LDPC_CAP(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 1)
91 #define GET_HT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1)
93 #define GET_HT_CAPABILITY_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 2)
95 /* TXBF Capabilities */
96 #define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
97 #define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
98 #define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
99 #define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
100 #define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
102 #define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 10, 1)
103 #define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE((_pEleStart)+21, 15, 2)
105 #endif /* _RTL871X_HT_H_ */