1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
10 #include "odm_precomp.h"
11 #include <hal_btcoex.h>
16 /* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */
19 RT_MULTI_FUNC_NONE = 0x00,
20 RT_MULTI_FUNC_WIFI = 0x01,
21 RT_MULTI_FUNC_BT = 0x02,
22 RT_MULTI_FUNC_GPS = 0x04,
25 /* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */
27 enum RT_POLARITY_CTL {
28 RT_POLARITY_LOW_ACT = 0,
29 RT_POLARITY_HIGH_ACT = 1,
32 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */
33 enum RT_REGULATOR_MODE {
34 RT_SWITCHING_REGULATOR = 0,
39 RT_AMPDU_BURST_NONE = 0,
40 RT_AMPDU_BURST_92D = 1,
41 RT_AMPDU_BURST_88E = 2,
42 RT_AMPDU_BURST_8812_4 = 3,
43 RT_AMPDU_BURST_8812_8 = 4,
44 RT_AMPDU_BURST_8812_12 = 5,
45 RT_AMPDU_BURST_8812_15 = 6,
46 RT_AMPDU_BURST_8723B = 7,
49 #define CHANNEL_MAX_NUMBER 14+24+21 /* 14 is the max channel number */
50 #define CHANNEL_MAX_NUMBER_2G 14
51 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A" */
52 #define CHANNEL_MAX_NUMBER_5G_80M 7
53 #define CHANNEL_GROUP_MAX 3+9 /* ch1~3, ch4~9, ch10~14 total three groups */
54 #define MAX_PG_GROUP 13
56 /* Tx Power Limit Table Size */
57 #define MAX_REGULATION_NUM 4
58 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4
59 #define MAX_2_4G_BANDWIDTH_NUM 4
60 #define MAX_RATE_SECTION_NUM 10
61 #define MAX_5G_BANDWIDTH_NUM 4
63 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */
64 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */
67 /* duplicate code, will move to ODM ######### */
68 /* define IQK_MAC_REG_NUM 4 */
69 /* define IQK_ADDA_REG_NUM 16 */
71 /* define IQK_BB_REG_NUM 10 */
72 #define IQK_BB_REG_NUM_92C 9
73 #define IQK_BB_REG_NUM_92D 10
74 #define IQK_BB_REG_NUM_test 6
76 #define IQK_Matrix_Settings_NUM_92D 1+24+21
78 /* define HP_THERMAL_NUM 8 */
79 /* duplicate code, will move to ODM ######### */
82 SINGLEMAC_SINGLEPHY, /* SMSP */
83 DUALMAC_DUALPHY, /* DMDP */
84 DUALMAC_SINGLEPHY, /* DMSP */
87 #define PAGE_SIZE_128 128
88 #define PAGE_SIZE_256 256
89 #define PAGE_SIZE_512 512
94 #define DYNAMIC_FUNC_BT BIT0
101 /* Upper and Lower Signal threshold for Rate Adaptive */
102 int UndecoratedSmoothedPWDB;
103 int UndecoratedSmoothedCCK;
104 int EntryMinUndecoratedSmoothedPWDB;
105 int EntryMaxUndecoratedSmoothedPWDB;
106 int MinUndecoratedPWDBForDM;
107 int LastMinUndecoratedPWDBForDM;
109 s32 UndecoratedSmoothedBeacon;
111 /* duplicate code, will move to ODM ######### */
113 u8 bDynamicTxPowerEnable;
115 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */
117 /* for tx power tracking */
120 u8 bTXPowerTrackingInit;
121 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
124 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
133 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
135 u8 bAPKThermalMeterIgnore;
144 u32 ADDA_backup[IQK_ADDA_REG_NUM];
145 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
146 u32 IQK_BB_backup_recover[9];
147 u32 IQK_BB_backup[IQK_BB_REG_NUM];
149 u8 PowerIndex_backup[6];
158 u8 ThermalValue_HP[HP_THERMAL_NUM];
159 u8 ThermalValue_HP_index;
162 /* for TxPwrTracking2 */
168 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
170 u32 prv_traffic_idx; /* edca turbo */
171 /* duplicate code, will move to ODM ######### */
173 /* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */
178 struct hal_com_data {
179 HAL_VERSION VersionID;
180 enum RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */
181 enum RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */
182 enum RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */
185 u16 FirmwareVersionRev;
186 u16 FirmwareSubVersion;
187 u16 FirmwareSignature;
189 /* current WIFI_PHY values */
190 enum WIRELESS_MODE CurrentWirelessMode;
191 enum CHANNEL_WIDTH CurrentChannelBW;
192 enum BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */
193 enum BAND_TYPE BandSet;
195 u8 CurrentCenterFrequencyIndex1;
196 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
197 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */
201 u16 ForcedDataRate;/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */
214 u8 DefaultInitialGain[4];
215 /* EEPROM setting. */
220 u8 EEPROMSubCustomerID;
223 u8 EEPROMThermalMeter;
224 u8 EEPROMBluetoothCoexist;
225 u8 EEPROMBluetoothType;
226 u8 EEPROMBluetoothAntNum;
227 u8 EEPROMBluetoothAntIsolation;
228 u8 EEPROMBluetoothRadioShared;
229 u8 bTXPowerDataReadFromEEPORM;
230 u8 bAPKThermalMeterIgnore;
231 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */
234 u8 EfuseUsedPercentage;
239 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
240 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
241 /* If only one tx, only BW20 and OFDM are used. */
242 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
243 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
244 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
245 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
247 u8 Index5G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
248 u8 Index5G_BW80_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
249 s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
250 s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
251 s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
252 s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
257 u8 TxPwrInPercentage;
259 u8 TxPwrCalibrateRate;
260 /* TX power by rate table at most 4RF path. */
261 /* The register is */
262 /* VHT TX power by rate off setArray = */
263 /* Band:-2G&5G = 0 / 1 */
264 /* RF: at most 4*4 = ABCD = 0/1/2/3 */
265 /* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */
268 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
269 [TX_PWR_BY_RATE_NUM_RF]
270 [TX_PWR_BY_RATE_NUM_RF]
271 [TX_PWR_BY_RATE_NUM_RATE];
274 /* 2 Power Limit Table */
275 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
276 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
277 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */
278 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */
279 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */
281 /* Power Limit Table for 2.4G */
282 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
283 [MAX_2_4G_BANDWIDTH_NUM]
284 [MAX_RATE_SECTION_NUM]
285 [CHANNEL_MAX_NUMBER_2G]
288 /* Power Limit Table for 5G */
289 s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
290 [MAX_5G_BANDWIDTH_NUM]
291 [MAX_RATE_SECTION_NUM]
292 [CHANNEL_MAX_NUMBER_5G]
296 /* Store the original power by rate value of the base of each rate section of rf path A & B */
297 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
298 [TX_PWR_BY_RATE_NUM_RF]
299 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
300 u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
301 [TX_PWR_BY_RATE_NUM_RF]
302 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
304 /* For power group */
305 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
306 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
312 u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
313 /* The current Tx Power Level */
314 u8 CurrentCckTxPwrIdx;
315 u8 CurrentOfdm24GTxPwrIdx;
316 u8 CurrentBW2024GTxPwrIdx;
317 u8 CurrentBW4024GTxPwrIdx;
319 /* Read/write are allow for following hardware information variables */
321 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
322 u32 CCKTxPowerLevelOriginalOffset;
325 u32 AntennaTxPath; /* Antenna path Tx */
326 u32 AntennaRxPath; /* Antenna path Rx */
348 bool bChnlBWInitialized;
351 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */
352 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
353 u8 b1x1RecvCombine; /* for 1T1R receive combining */
355 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
357 struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */
364 /* for host message to fw */
369 /* Beacon function related global variable. */
382 u8 ant_path; /* for 8723B s0/s1 selection */
384 u8 u1ForcedIgiLb; /* forced IGI lower bound */
386 u8 bDumpRxPkt;/* for debug */
387 u8 bDumpTxPkt;/* for debug */
388 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */
390 /* 2010/08/09 MH Add CU power down mode. */
393 /* Add for dual MAC 0--Mac0 1--Mac1 */
399 /* 2010/12/10 MH Add for USB aggreation mode dynamic shceme. */
400 bool UsbRxHighSpeedMode;
402 /* 2010/11/22 MH Add for slim combo debug mode selective. */
403 /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */
406 /* u8 AMPDUDensity; */
408 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */
412 struct submit_ctx iqk_sctx;
414 enum RT_AMPDU_BURST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */
419 /* SDIO Tx FIFO related. */
420 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */
421 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
422 _lock SdioTxFIFOFreePageLock;
423 u8 SdioTxOQTMaxFreeSpace;
424 u8 SdioTxOQTFreeSpace;
427 /* SDIO Rx FIFO related. */
431 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */
433 struct dm_priv dmpriv;
436 /* For bluetooth co-existance */
437 BT_COEXIST bt_coexist;
439 /* Interrupt related register information. */
443 #ifdef CONFIG_BACKGROUND_NOISE_MONITOR
444 s16 noise[ODM_MAX_CHANNEL_NUM];
449 #define GET_HAL_DATA(__padapter) ((struct hal_com_data *)((__padapter)->HalData))
450 #define GET_HAL_RFPATH_NUM(__padapter) (((struct hal_com_data *)((__padapter)->HalData))->NumTotalRFPath)
451 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel)
452 #define GET_RF_TYPE(__padapter) (GET_HAL_DATA(__padapter)->rf_type)
454 #endif /* __HAL_DATA_H__ */