drivers/staging/rtl8723bs/hal/sdio_halinit.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #include <drv_types.h>
   8 #include <rtw_debug.h>
   9 #include <rtl8723b_hal.h>
  10
  11 #include "hal_com_h2c.h"
  12 /*
  13  * Description:
  14  *Call power on sequence to enable card
  15  *
  16  * Return:
  17  *_SUCCESS      enable success
  18  *_FAIL         enable fail
  19  */
  20 static u8 CardEnable(struct adapter *padapter)
  21 {
  22         u8 bMacPwrCtrlOn;
  23         u8 ret = _FAIL;
  24
  25
  26         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  27         if (!bMacPwrCtrlOn) {
  28                 /*  RSV_CTRL 0x1C[7:0] = 0x00 */
  29                 /*  unlock ISO/CLK/Power control register */
  30                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
  31
  32                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
  33                 if (ret == _SUCCESS) {
  34                         u8 bMacPwrCtrlOn = true;
  35                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  36                 }
  37         } else
  38                 ret = _SUCCESS;
  39
  40         return ret;
  41 }
  42
  43 static
  44 u8 _InitPowerOn_8723BS(struct adapter *padapter)
  45 {
  46         u8 value8;
  47         u16 value16;
  48         u32 value32;
  49         u8 ret;
  50 /*      u8 bMacPwrCtrlOn; */
  51
  52
  53         /*  all of these MUST be configured before power on */
  54
  55         /*  only cmd52 can be used before power on(card enable) */
  56         ret = CardEnable(padapter);
  57         if (!ret)
  58                 return _FAIL;
  59
  60         /*  Radio-Off Pin Trigger */
  61         value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
  62         value8 |= BIT(1); /*  Enable falling edge triggering interrupt */
  63         rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
  64         value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
  65         value8 |= BIT(1);
  66         rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
  67
  68         /*  Enable power down and GPIO interrupt */
  69         value16 = rtw_read16(padapter, REG_APS_FSMCO);
  70         value16 |= EnPDN; /*  Enable HW power down and RF on */
  71         rtw_write16(padapter, REG_APS_FSMCO, value16);
  72
  73         /*  Enable CMD53 R/W Operation */
  74 /*      bMacPwrCtrlOn = true; */
  75 /*      rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
  76
  77         rtw_write8(padapter, REG_CR, 0x00);
  78         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
  79         value16 = rtw_read16(padapter, REG_CR);
  80         value16 |= (
  81                 HCI_TXDMA_EN |
  82                 HCI_RXDMA_EN |
  83                 TXDMA_EN |
  84                 RXDMA_EN |
  85                 PROTOCOL_EN |
  86                 SCHEDULE_EN |
  87                 ENSEC |
  88                 CALTMR_EN
  89         );
  90         rtw_write16(padapter, REG_CR, value16);
  91
  92         hal_btcoex_PowerOnSetting(padapter);
  93
  94         /*  external switch to S1 */
  95         /*  0x38[11] = 0x1 */
  96         /*  0x4c[23] = 0x1 */
  97         /*  0x64[0] = 0 */
  98         value16 = rtw_read16(padapter, REG_PWR_DATA);
  99         /*  Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
 100         value16 |= BIT(11); /*  BIT_EEPRPAD_RFE_CTRL_EN */
 101         rtw_write16(padapter, REG_PWR_DATA, value16);
 102
 103         value32 = rtw_read32(padapter, REG_LEDCFG0);
 104         value32 |= BIT(23); /*  DPDT_SEL_EN, 1 for SW control */
 105         rtw_write32(padapter, REG_LEDCFG0, value32);
 106
 107         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
 108         value8 &= ~BIT(0); /*  BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
 109         rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
 110
 111         return _SUCCESS;
 112 }
 113
 114 /* Tx Page FIFO threshold */
 115 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
 116 {
 117         u16 HQ_threshold, NQ_threshold, LQ_threshold;
 118
 119         HQ_threshold = (numPubQ + numHQ + 1) >> 1;
 120         HQ_threshold |= (HQ_threshold << 8);
 121
 122         NQ_threshold = (numPubQ + numNQ + 1) >> 1;
 123         NQ_threshold |= (NQ_threshold << 8);
 124
 125         LQ_threshold = (numPubQ + numLQ + 1) >> 1;
 126         LQ_threshold |= (LQ_threshold << 8);
 127
 128         rtw_write16(padapter, 0x218, HQ_threshold);
 129         rtw_write16(padapter, 0x21A, NQ_threshold);
 130         rtw_write16(padapter, 0x21C, LQ_threshold);
 131 }
 132
 133 static void _InitQueueReservedPage(struct adapter *padapter)
 134 {
 135         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 136         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 137         u32 numHQ = 0;
 138         u32 numLQ = 0;
 139         u32 numNQ = 0;
 140         u32 numPubQ;
 141         u32 value32;
 142         u8 value8;
 143         bool bWiFiConfig        = pregistrypriv->wifi_spec;
 144
 145         if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 146                 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
 147
 148         if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 149                 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
 150
 151         /*  NOTE: This step shall be proceed before writing REG_RQPN. */
 152         if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 153                 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
 154
 155         numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
 156
 157         value8 = (u8)_NPQ(numNQ);
 158         rtw_write8(padapter, REG_RQPN_NPQ, value8);
 159
 160         /*  TX DMA */
 161         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 162         rtw_write32(padapter, REG_RQPN, value32);
 163
 164         rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
 165
 166         _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
 167 }
 168
 169 static void _InitTxBufferBoundary(struct adapter *padapter)
 170 {
 171         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 172
 173         /* u16 txdmactrl; */
 174         u8 txpktbuf_bndy;
 175
 176         if (!pregistrypriv->wifi_spec) {
 177                 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
 178         } else {
 179                 /* for WMM */
 180                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
 181         }
 182
 183         rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
 184         rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
 185         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
 186         rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 187         rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
 188 }
 189
 190 static void _InitNormalChipRegPriority(
 191         struct adapter *Adapter,
 192         u16 beQ,
 193         u16 bkQ,
 194         u16 viQ,
 195         u16 voQ,
 196         u16 mgtQ,
 197         u16 hiQ
 198 )
 199 {
 200         u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 201
 202         value16 |=
 203                 _TXDMA_BEQ_MAP(beQ)  |
 204                 _TXDMA_BKQ_MAP(bkQ)  |
 205                 _TXDMA_VIQ_MAP(viQ)  |
 206                 _TXDMA_VOQ_MAP(voQ)  |
 207                 _TXDMA_MGQ_MAP(mgtQ) |
 208                 _TXDMA_HIQ_MAP(hiQ);
 209
 210         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 211 }
 212
 213 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 214 {
 215         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 216
 217         u16 value = 0;
 218         switch (pHalData->OutEpQueueSel) {
 219         case TX_SELE_HQ:
 220                 value = QUEUE_HIGH;
 221                 break;
 222         case TX_SELE_LQ:
 223                 value = QUEUE_LOW;
 224                 break;
 225         case TX_SELE_NQ:
 226                 value = QUEUE_NORMAL;
 227                 break;
 228         default:
 229                 break;
 230         }
 231
 232         _InitNormalChipRegPriority(
 233                 Adapter, value, value, value, value, value, value
 234         );
 235
 236 }
 237
 238 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 239 {
 240         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 241         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 242         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 243
 244
 245         u16 valueHi = 0;
 246         u16 valueLow = 0;
 247
 248         switch (pHalData->OutEpQueueSel) {
 249         case (TX_SELE_HQ | TX_SELE_LQ):
 250                 valueHi = QUEUE_HIGH;
 251                 valueLow = QUEUE_LOW;
 252                 break;
 253         case (TX_SELE_NQ | TX_SELE_LQ):
 254                 valueHi = QUEUE_NORMAL;
 255                 valueLow = QUEUE_LOW;
 256                 break;
 257         case (TX_SELE_HQ | TX_SELE_NQ):
 258                 valueHi = QUEUE_HIGH;
 259                 valueLow = QUEUE_NORMAL;
 260                 break;
 261         default:
 262                 break;
 263         }
 264
 265         if (!pregistrypriv->wifi_spec) {
 266                 beQ = valueLow;
 267                 bkQ = valueLow;
 268                 viQ = valueHi;
 269                 voQ = valueHi;
 270                 mgtQ = valueHi;
 271                 hiQ = valueHi;
 272         } else {
 273                 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 274                 beQ = valueLow;
 275                 bkQ = valueHi;
 276                 viQ = valueHi;
 277                 voQ = valueLow;
 278                 mgtQ = valueHi;
 279                 hiQ = valueHi;
 280         }
 281
 282         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 283
 284 }
 285
 286 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
 287 {
 288         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 289         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 290
 291         if (!pregistrypriv->wifi_spec) {
 292                 /*  typical setting */
 293                 beQ = QUEUE_LOW;
 294                 bkQ = QUEUE_LOW;
 295                 viQ = QUEUE_NORMAL;
 296                 voQ = QUEUE_HIGH;
 297                 mgtQ = QUEUE_HIGH;
 298                 hiQ = QUEUE_HIGH;
 299         } else {
 300                 /*  for WMM */
 301                 beQ = QUEUE_LOW;
 302                 bkQ = QUEUE_NORMAL;
 303                 viQ = QUEUE_NORMAL;
 304                 voQ = QUEUE_HIGH;
 305                 mgtQ = QUEUE_HIGH;
 306                 hiQ = QUEUE_HIGH;
 307         }
 308         _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 309 }
 310
 311 static void _InitQueuePriority(struct adapter *Adapter)
 312 {
 313         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 314
 315         switch (pHalData->OutEpNumber) {
 316         case 1:
 317                 _InitNormalChipOneOutEpPriority(Adapter);
 318                 break;
 319         case 2:
 320                 _InitNormalChipTwoOutEpPriority(Adapter);
 321                 break;
 322         case 3:
 323                 _InitNormalChipThreeOutEpPriority(Adapter);
 324                 break;
 325         default:
 326                 break;
 327         }
 328
 329
 330 }
 331
 332 static void _InitPageBoundary(struct adapter *padapter)
 333 {
 334         /*  RX Page Boundary */
 335         u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
 336
 337         rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 338 }
 339
 340 static void _InitTransferPageSize(struct adapter *padapter)
 341 {
 342         /*  Tx page size is always 128. */
 343
 344         u8 value8;
 345         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 346         rtw_write8(padapter, REG_PBP, value8);
 347 }
 348
 349 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
 350 {
 351         rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 352 }
 353
 354 static void _InitNetworkType(struct adapter *padapter)
 355 {
 356         u32 value32;
 357
 358         value32 = rtw_read32(padapter, REG_CR);
 359
 360         /*  TODO: use the other function to set network type */
 361 /*      value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
 362         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 363
 364         rtw_write32(padapter, REG_CR, value32);
 365 }
 366
 367 static void _InitWMACSetting(struct adapter *padapter)
 368 {
 369         struct hal_com_data *pHalData;
 370         u16 value16;
 371
 372
 373         pHalData = GET_HAL_DATA(padapter);
 374
 375         pHalData->ReceiveConfig = 0;
 376         pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
 377         pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
 378         pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
 379         pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
 380         rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
 381
 382         /*  Accept all multicast address */
 383         rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
 384         rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
 385
 386         /*  Accept all data frames */
 387         value16 = 0xFFFF;
 388         rtw_write16(padapter, REG_RXFLTMAP2, value16);
 389
 390         /*  2010.09.08 hpfan */
 391         /*  Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
 392         /*  RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
 393         value16 = 0x400;
 394         rtw_write16(padapter, REG_RXFLTMAP1, value16);
 395
 396         /*  Accept all management frames */
 397         value16 = 0xFFFF;
 398         rtw_write16(padapter, REG_RXFLTMAP0, value16);
 399 }
 400
 401 static void _InitAdaptiveCtrl(struct adapter *padapter)
 402 {
 403         u16 value16;
 404         u32 value32;
 405
 406         /*  Response Rate Set */
 407         value32 = rtw_read32(padapter, REG_RRSR);
 408         value32 &= ~RATE_BITMAP_ALL;
 409         value32 |= RATE_RRSR_CCK_ONLY_1M;
 410         rtw_write32(padapter, REG_RRSR, value32);
 411
 412         /*  CF-END Threshold */
 413         /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
 414
 415         /*  SIFS (used in NAV) */
 416         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 417         rtw_write16(padapter, REG_SPEC_SIFS, value16);
 418
 419         /*  Retry Limit */
 420         value16 = _LRL(0x30) | _SRL(0x30);
 421         rtw_write16(padapter, REG_RL, value16);
 422 }
 423
 424 static void _InitEDCA(struct adapter *padapter)
 425 {
 426         /*  Set Spec SIFS (used in NAV) */
 427         rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
 428         rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
 429
 430         /*  Set SIFS for CCK */
 431         rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
 432
 433         /*  Set SIFS for OFDM */
 434         rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
 435
 436         /*  TXOP */
 437         rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 438         rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 439         rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
 440         rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
 441 }
 442
 443 static void _InitRetryFunction(struct adapter *padapter)
 444 {
 445         u8 value8;
 446
 447         value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
 448         value8 |= EN_AMPDU_RTY_NEW;
 449         rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
 450
 451         /*  Set ACK timeout */
 452         rtw_write8(padapter, REG_ACKTO, 0x40);
 453 }
 454
 455 static void HalRxAggr8723BSdio(struct adapter *padapter)
 456 {
 457         u8 valueDMATimeout;
 458         u8 valueDMAPageCount;
 459
 460         valueDMATimeout = 0x06;
 461         valueDMAPageCount = 0x06;
 462
 463         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
 464         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
 465 }
 466
 467 static void sdio_AggSettingRxUpdate(struct adapter *padapter)
 468 {
 469         u8 valueDMA;
 470         u8 valueRxAggCtrl = 0;
 471         u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
 472         u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
 473
 474         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 475         valueDMA |= RXDMA_AGG_EN;
 476         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 477
 478         valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 479         valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
 480         valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
 481         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
 482 }
 483
 484 static void _initSdioAggregationSetting(struct adapter *padapter)
 485 {
 486         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
 487
 488         /*  Tx aggregation setting */
 489 /*      sdio_AggSettingTxUpdate(padapter); */
 490
 491         /*  Rx aggregation setting */
 492         HalRxAggr8723BSdio(padapter);
 493
 494         sdio_AggSettingRxUpdate(padapter);
 495
 496         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 497         pHalData->UsbRxHighSpeedMode = false;
 498 }
 499
 500 static void _InitOperationMode(struct adapter *padapter)
 501 {
 502         struct mlme_ext_priv *pmlmeext;
 503         u8 regBwOpMode = 0;
 504
 505         pmlmeext = &padapter->mlmeextpriv;
 506
 507         /* 1 This part need to modified according to the rate set we filtered!! */
 508         /*  */
 509         /*  Set RRSR, RATR, and REG_BWOPMODE registers */
 510         /*  */
 511         switch (pmlmeext->cur_wireless_mode) {
 512         case WIRELESS_MODE_B:
 513                 regBwOpMode = BW_OPMODE_20MHZ;
 514                 break;
 515         case WIRELESS_MODE_G:
 516                 regBwOpMode = BW_OPMODE_20MHZ;
 517                 break;
 518         case WIRELESS_MODE_AUTO:
 519                 regBwOpMode = BW_OPMODE_20MHZ;
 520                 break;
 521         case WIRELESS_MODE_N_24G:
 522                 /*  It support CCK rate by default. */
 523                 /*  CCK rate will be filtered out only when associated AP does not support it. */
 524                 regBwOpMode = BW_OPMODE_20MHZ;
 525                 break;
 526
 527         default: /* for MacOSX compiler warning. */
 528                 break;
 529         }
 530
 531         rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
 532
 533 }
 534
 535 static void _InitInterrupt(struct adapter *padapter)
 536 {
 537         /*  HISR - turn all off */
 538         rtw_write32(padapter, REG_HISR, 0);
 539
 540         /*  HIMR - turn all off */
 541         rtw_write32(padapter, REG_HIMR, 0);
 542
 543         /*  */
 544         /*  Initialize and enable SDIO Host Interrupt. */
 545         /*  */
 546         InitInterrupt8723BSdio(padapter);
 547
 548         /*  */
 549         /*  Initialize system Host Interrupt. */
 550         /*  */
 551         InitSysInterrupt8723BSdio(padapter);
 552 }
 553
 554 static void _InitRFType(struct adapter *padapter)
 555 {
 556         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 557
 558         pHalData->rf_chip       = RF_6052;
 559 }
 560
 561 static void _RfPowerSave(struct adapter *padapter)
 562 {
 563 /* YJ, TODO */
 564 }
 565
 566 /*  */
 567 /*  2010/08/09 MH Add for power down check. */
 568 /*  */
 569 static bool HalDetectPwrDownMode(struct adapter *Adapter)
 570 {
 571         u8 tmpvalue;
 572         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 573         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 574
 575
 576         EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
 577
 578         /*  2010/08/25 MH INF priority > PDN Efuse value. */
 579         if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 580                 pHalData->pwrdown = true;
 581         else
 582                 pHalData->pwrdown = false;
 583
 584         return pHalData->pwrdown;
 585 }       /*  HalDetectPwrDownMode */
 586
 587 static u32 rtl8723bs_hal_init(struct adapter *padapter)
 588 {
 589         s32 ret;
 590         struct hal_com_data *pHalData;
 591         struct pwrctrl_priv *pwrctrlpriv;
 592         u32 NavUpper = WiFiNavUpperUs;
 593         u8 u1bTmp;
 594
 595         pHalData = GET_HAL_DATA(padapter);
 596         pwrctrlpriv = adapter_to_pwrctl(padapter);
 597
 598         if (
 599                 adapter_to_pwrctl(padapter)->bips_processing == true &&
 600                 adapter_to_pwrctl(padapter)->pre_ips_type == 0
 601         ) {
 602                 unsigned long start_time;
 603                 u8 cpwm_orig, cpwm_now;
 604                 u8 val8, bMacPwrCtrlOn = true;
 605
 606                 /* for polling cpwm */
 607                 cpwm_orig = 0;
 608                 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
 609
 610                 /* ser rpwm */
 611                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 612                 val8 &= 0x80;
 613                 val8 += 0x80;
 614                 val8 |= BIT(6);
 615                 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 616                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 617
 618                 /* do polling cpwm */
 619                 start_time = jiffies;
 620                 do {
 621
 622                         mdelay(1);
 623
 624                         rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
 625                         if ((cpwm_orig ^ cpwm_now) & 0x80)
 626                                 break;
 627
 628                         if (jiffies_to_msecs(jiffies - start_time) > 100)
 629                                 break;
 630
 631                 } while (1);
 632
 633                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
 634
 635                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 636
 637                 hal_btcoex_InitHwConfig(padapter, false);
 638
 639                 return _SUCCESS;
 640         }
 641
 642         /*  Disable Interrupt first. */
 643 /*      rtw_hal_disable_interrupt(padapter); */
 644
 645         ret = _InitPowerOn_8723BS(padapter);
 646         if (ret == _FAIL)
 647                 return _FAIL;
 648
 649         rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
 650
 651         ret = rtl8723b_FirmwareDownload(padapter, false);
 652         if (ret != _SUCCESS) {
 653                 padapter->bFWReady = false;
 654                 pHalData->fw_ractrl = false;
 655                 return ret;
 656         } else {
 657                 padapter->bFWReady = true;
 658                 pHalData->fw_ractrl = true;
 659         }
 660
 661         rtl8723b_InitializeFirmwareVars(padapter);
 662
 663 /*      SIC_Init(padapter); */
 664
 665         if (pwrctrlpriv->reg_rfoff)
 666                 pwrctrlpriv->rf_pwrstate = rf_off;
 667
 668         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 669         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 670         HalDetectPwrDownMode(padapter);
 671
 672         /*  Set RF type for BB/RF configuration */
 673         _InitRFType(padapter);
 674
 675         /*  Save target channel */
 676         /*  <Roger_Notes> Current Channel will be updated again later. */
 677         pHalData->CurrentChannel = 6;
 678
 679         ret = PHY_MACConfig8723B(padapter);
 680         if (ret != _SUCCESS)
 681                 return ret;
 682         /*  */
 683         /* d. Initialize BB related configurations. */
 684         /*  */
 685         ret = PHY_BBConfig8723B(padapter);
 686         if (ret != _SUCCESS)
 687                 return ret;
 688
 689         /*  If RF is on, we need to init RF. Otherwise, skip the procedure. */
 690         /*  We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
 691         /* if (pHalData->eRFPowerState == eRfOn) */
 692         {
 693                 ret = PHY_RFConfig8723B(padapter);
 694                 if (ret != _SUCCESS)
 695                         return ret;
 696         }
 697
 698         /*  */
 699         /*  Joseph Note: Keep RfRegChnlVal for later use. */
 700         /*  */
 701         pHalData->RfRegChnlVal[0] =
 702                 PHY_QueryRFReg(padapter, (enum rf_path)0, RF_CHNLBW, bRFRegOffsetMask);
 703         pHalData->RfRegChnlVal[1] =
 704                 PHY_QueryRFReg(padapter, (enum rf_path)1, RF_CHNLBW, bRFRegOffsetMask);
 705
 706
 707         /* if (!pHalData->bMACFuncEnable) { */
 708         _InitQueueReservedPage(padapter);
 709         _InitTxBufferBoundary(padapter);
 710
 711         /*  init LLT after tx buffer boundary is defined */
 712         ret = rtl8723b_InitLLTTable(padapter);
 713         if (ret != _SUCCESS)
 714                 return _FAIL;
 715
 716         /*  */
 717         _InitQueuePriority(padapter);
 718         _InitPageBoundary(padapter);
 719         _InitTransferPageSize(padapter);
 720
 721         /*  Get Rx PHY status in order to report RSSI and others. */
 722         _InitDriverInfoSize(padapter, DRVINFO_SZ);
 723         hal_init_macaddr(padapter);
 724         _InitNetworkType(padapter);
 725         _InitWMACSetting(padapter);
 726         _InitAdaptiveCtrl(padapter);
 727         _InitEDCA(padapter);
 728         _InitRetryFunction(padapter);
 729         _initSdioAggregationSetting(padapter);
 730         _InitOperationMode(padapter);
 731         rtl8723b_InitBeaconParameters(padapter);
 732         _InitInterrupt(padapter);
 733         _InitBurstPktLen_8723BS(padapter);
 734
 735         /* YJ, TODO */
 736         rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3);        /*  CCA */
 737         rtw_write8(padapter, 0x976, 0); /*  hpfan_todo: 2nd CCA related */
 738
 739         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /*  unit: 256us. 256ms */
 740         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /*  unit: 256us. 256ms */
 741
 742         invalidate_cam_all(padapter);
 743
 744         rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
 745                 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 746
 747         /*  Record original value for template. This is arough data, we can only use the data */
 748         /*  for power adjust. The value can not be adjustde according to different power!!! */
 749 /*      pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
 750 /*      pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
 751
 752         rtl8723b_InitAntenna_Selection(padapter);
 753
 754         /*  */
 755         /*  Disable BAR, suggested by Scott */
 756         /*  2010.04.09 add by hpfan */
 757         /*  */
 758         rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 759
 760         /*  HW SEQ CTRL */
 761         /*  set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 762         rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
 763
 764
 765         /*  */
 766         /*  Configure SDIO TxRx Control to enable Rx DMA timer masking. */
 767         /*  2010.02.24. */
 768         /*  */
 769         rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
 770
 771         _RfPowerSave(padapter);
 772
 773
 774         rtl8723b_InitHalDm(padapter);
 775
 776         /*  */
 777         /*  Update current Tx FIFO page status. */
 778         /*  */
 779         HalQueryTxBufferStatus8723BSdio(padapter);
 780         HalQueryTxOQTBufferStatus8723BSdio(padapter);
 781         pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
 782
 783         /*  Enable MACTXEN/MACRXEN block */
 784         u1bTmp = rtw_read8(padapter, REG_CR);
 785         u1bTmp |= (MACTXEN | MACRXEN);
 786         rtw_write8(padapter, REG_CR, u1bTmp);
 787
 788         rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
 789
 790         /* ack for xmit mgmt frames. */
 791         rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
 792
 793 /*      pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
 794
 795         {
 796                 pwrctrlpriv->rf_pwrstate = rf_on;
 797
 798                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 799                         struct pwrctrl_priv *pwrpriv;
 800                         unsigned long start_time;
 801                         u8 restore_iqk_rst;
 802                         u8 b2Ant;
 803                         u8 h2cCmdBuf;
 804
 805                         pwrpriv = adapter_to_pwrctl(padapter);
 806
 807                         PHY_LCCalibrate_8723B(&pHalData->odmpriv);
 808
 809                         /* Inform WiFi FW that it is the beginning of IQK */
 810                         h2cCmdBuf = 1;
 811                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
 812
 813                         start_time = jiffies;
 814                         do {
 815                                 if (rtw_read8(padapter, 0x1e7) & 0x01)
 816                                         break;
 817
 818                                 msleep(50);
 819                         } while (jiffies_to_msecs(jiffies - start_time) <= 400);
 820
 821                         hal_btcoex_IQKNotify(padapter, true);
 822
 823                         restore_iqk_rst = pwrpriv->bips_processing;
 824                         b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;
 825                         PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
 826                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
 827
 828                         hal_btcoex_IQKNotify(padapter, false);
 829
 830                         /* Inform WiFi FW that it is the finish of IQK */
 831                         h2cCmdBuf = 0;
 832                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
 833
 834                         ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
 835                 }
 836         }
 837
 838         /*  Init BT hw config. */
 839         hal_btcoex_InitHwConfig(padapter, false);
 840
 841         return _SUCCESS;
 842 }
 843
 844 /*  */
 845 /*  Description: */
 846 /*      RTL8723e card disable power sequence v003 which suggested by Scott. */
 847 /*  */
 848 /*  First created by tynli. 2011.01.28. */
 849 /*  */
 850 static void CardDisableRTL8723BSdio(struct adapter *padapter)
 851 {
 852         u8 u1bTmp;
 853         u8 bMacPwrCtrlOn;
 854
 855         /*  Run LPS WL RFOFF flow */
 856         HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
 857
 858         /*      ==== Reset digital sequence   ====== */
 859
 860         u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
 861         if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
 862                 rtl8723b_FirmwareSelfReset(padapter);
 863
 864         /*  Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
 865         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
 866         u1bTmp &= ~BIT(2);      /*  0x2[10], FEN_CPUEN */
 867         rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
 868
 869         /*  MCUFWDL 0x80[1:0]= 0 */
 870         /*  reset MCU ready status */
 871         rtw_write8(padapter, REG_MCUFWDL, 0);
 872
 873         /*  Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
 874         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
 875         u1bTmp &= ~BIT(0);
 876         rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
 877         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
 878         u1bTmp |= BIT(0);
 879         rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
 880
 881         /*      ==== Reset digital sequence end ====== */
 882
 883         bMacPwrCtrlOn = false;  /*  Disable CMD53 R/W */
 884         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 885         HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
 886 }
 887
 888 static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
 889 {
 890         struct dvobj_priv *psdpriv = padapter->dvobj;
 891         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
 892
 893         if (padapter->hw_init_completed) {
 894                 if (adapter_to_pwrctl(padapter)->bips_processing) {
 895                         if (padapter->netif_up) {
 896                                 int cnt = 0;
 897                                 u8 val8 = 0;
 898
 899                                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
 900                                 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
 901                                 do {
 902                                         val8 = rtw_read8(padapter, REG_HMETFR);
 903                                         cnt++;
 904                                         mdelay(10);
 905                                 } while (cnt < 100 && (val8 != 0));
 906                                 /* H2C done, enter 32k */
 907                                 if (val8 == 0) {
 908                                         /* ser rpwm to enter 32k */
 909                                         val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
 910                                         val8 += 0x80;
 911                                         val8 |= BIT(0);
 912                                         rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
 913                                         adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 914                                         cnt = val8 = 0;
 915                                         do {
 916                                                 val8 = rtw_read8(padapter, REG_CR);
 917                                                 cnt++;
 918                                                 mdelay(10);
 919                                         } while (cnt < 100 && (val8 != 0xEA));
 920                                 }
 921
 922                                 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
 923
 924                         } else {
 925                                 pdbgpriv->dbg_carddisable_cnt++;
 926                                 CardDisableRTL8723BSdio(padapter);
 927
 928                                 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
 929                         }
 930
 931                 } else {
 932                         pdbgpriv->dbg_carddisable_cnt++;
 933                         CardDisableRTL8723BSdio(padapter);
 934                 }
 935         } else
 936                 pdbgpriv->dbg_deinit_fail_cnt++;
 937
 938         return _SUCCESS;
 939 }
 940
 941 static u32 rtl8723bs_inirp_init(struct adapter *padapter)
 942 {
 943         return _SUCCESS;
 944 }
 945
 946 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter)
 947 {
 948         return _SUCCESS;
 949 }
 950
 951 static void rtl8723bs_init_default_value(struct adapter *padapter)
 952 {
 953         struct hal_com_data *pHalData;
 954
 955
 956         pHalData = GET_HAL_DATA(padapter);
 957
 958         rtl8723b_init_default_value(padapter);
 959
 960         /*  interface related variable */
 961         pHalData->SdioRxFIFOCnt = 0;
 962 }
 963
 964 static void rtl8723bs_interface_configure(struct adapter *padapter)
 965 {
 966         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 967         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 968         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 969         bool bWiFiConfig = pregistrypriv->wifi_spec;
 970
 971
 972         pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
 973         pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
 974         pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
 975
 976         if (bWiFiConfig)
 977                 pHalData->OutEpNumber = 2;
 978         else
 979                 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
 980
 981         switch (pHalData->OutEpNumber) {
 982         case 3:
 983                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
 984                 break;
 985         case 2:
 986                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
 987                 break;
 988         case 1:
 989                 pHalData->OutEpQueueSel = TX_SELE_HQ;
 990                 break;
 991         default:
 992                 break;
 993         }
 994
 995         Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
 996 }
 997
 998 /*  */
 999 /*      Description: */
1000 /*              We should set Efuse cell selection to WiFi cell in default. */
1001 /*  */
1002 /*      Assumption: */
1003 /*              PASSIVE_LEVEL */
1004 /*  */
1005 /*      Added by Roger, 2010.11.23. */
1006 /*  */
1007 static void _EfuseCellSel(struct adapter *padapter)
1008 {
1009         u32 value32;
1010
1011         value32 = rtw_read32(padapter, EFUSE_TEST);
1012         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1013         rtw_write32(padapter, EFUSE_TEST, value32);
1014 }
1015
1016 static void _ReadRFType(struct adapter *Adapter)
1017 {
1018         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1019
1020         pHalData->rf_chip = RF_6052;
1021 }
1022
1023
1024 static void Hal_EfuseParseMACAddr_8723BS(
1025         struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1026 )
1027 {
1028         u16 i;
1029         u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1030         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1031
1032         if (AutoLoadFail) {
1033 /*              sMacAddr[5] = (u8)GetRandomNumber(1, 254); */
1034                 for (i = 0; i < 6; i++)
1035                         pEEPROM->mac_addr[i] = sMacAddr[i];
1036         } else {
1037                 /* Read Permanent MAC address */
1038                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1039         }
1040 }
1041
1042 static void Hal_EfuseParseBoardType_8723BS(
1043         struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1044 )
1045 {
1046         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1047
1048         if (!AutoLoadFail) {
1049                 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1050                 if (pHalData->BoardType == 0xFF)
1051                         pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
1052         } else
1053                 pHalData->BoardType = 0;
1054 }
1055
1056 static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1057 {
1058         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1059         u8 *hwinfo = NULL;
1060
1061         /*  */
1062         /*  This part read and parse the eeprom/efuse content */
1063         /*  */
1064
1065         hwinfo = pEEPROM->efuse_eeprom_data;
1066
1067         Hal_InitPGData(padapter, hwinfo);
1068
1069         Hal_EfuseParseIDCode(padapter, hwinfo);
1070         Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1071
1072         Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1073
1074         Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1075         Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1076
1077         /*  */
1078         /*  Read Bluetooth co-exist and initialize */
1079         /*  */
1080         Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1081         Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1082         Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1083         Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1084         Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1085         Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1086         Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1087
1088         Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1089
1090         Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1091 }
1092
1093 static void _ReadPROMContent(struct adapter *padapter)
1094 {
1095         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1096         u8      eeValue;
1097
1098         eeValue = rtw_read8(padapter, REG_9346CR);
1099         /*  To check system boot selection. */
1100         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1101         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1102
1103 /*      pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1104
1105         _ReadEfuseInfo8723BS(padapter);
1106 }
1107
1108 static void _InitOtherVariable(struct adapter *Adapter)
1109 {
1110 }
1111
1112 /*  */
1113 /*      Description: */
1114 /*              Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1115 /*  */
1116 /*      Assumption: */
1117 /*              PASSIVE_LEVEL (SDIO interface) */
1118 /*  */
1119 /*  */
1120 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1121 {
1122         u8 val8;
1123
1124         /*  before access eFuse, make sure card enable has been called */
1125         if (!padapter->hw_init_completed)
1126                 _InitPowerOn_8723BS(padapter);
1127
1128
1129         val8 = rtw_read8(padapter, 0x4e);
1130         val8 |= BIT(6);
1131         rtw_write8(padapter, 0x4e, val8);
1132
1133         _EfuseCellSel(padapter);
1134         _ReadRFType(padapter);
1135         _ReadPROMContent(padapter);
1136         _InitOtherVariable(padapter);
1137
1138         if (!padapter->hw_init_completed) {
1139                 rtw_write8(padapter, 0x67, 0x00); /*  for BT, Switch Ant control to BT */
1140                 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue,  wifi ko module is loaded during booting, but wifi GUI is off */
1141         }
1142
1143         return _SUCCESS;
1144 }
1145
1146 static void ReadAdapterInfo8723BS(struct adapter *padapter)
1147 {
1148         /*  Read EEPROM size before call any EEPROM function */
1149         padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1150
1151         _ReadAdapterInfo8723BS(padapter);
1152 }
1153
1154 /*
1155  * If variable not handled here,
1156  * some variables will be processed in SetHwReg8723B()
1157  */
1158 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1159 {
1160         u8 val8;
1161
1162         switch (variable) {
1163         case HW_VAR_SET_RPWM:
1164                 /*  rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1165                 /*  BIT0 value - 1: 32k, 0:40MHz. */
1166                 /*  BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1167                 /*  BIT7 value - Toggle bit change. */
1168                 {
1169                         val8 = *val;
1170                         val8 &= 0xC1;
1171                         rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1172                 }
1173                 break;
1174         case HW_VAR_SET_REQ_FW_PS:
1175                 {
1176                         u8 req_fw_ps = 0;
1177                         req_fw_ps = rtw_read8(padapter, 0x8f);
1178                         req_fw_ps |= 0x10;
1179                         rtw_write8(padapter, 0x8f, req_fw_ps);
1180                 }
1181                 break;
1182         case HW_VAR_RXDMA_AGG_PG_TH:
1183                 val8 = *val;
1184                 break;
1185
1186         case HW_VAR_DM_IN_LPS:
1187                 rtl8723b_hal_dm_in_lps(padapter);
1188                 break;
1189         default:
1190                 SetHwReg8723B(padapter, variable, val);
1191                 break;
1192         }
1193 }
1194
1195 /*
1196  * If variable not handled here,
1197  * some variables will be processed in GetHwReg8723B()
1198  */
1199 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1200 {
1201         switch (variable) {
1202         case HW_VAR_CPWM:
1203                 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
1204                 break;
1205
1206         case HW_VAR_FW_PS_STATE:
1207                 {
1208                         /* 3. read dword 0x88               driver read fw ps state */
1209                         *((u16 *)val) = rtw_read16(padapter, 0x88);
1210                 }
1211                 break;
1212         default:
1213                 GetHwReg8723B(padapter, variable, val);
1214                 break;
1215         }
1216 }
1217
1218 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1219 {
1220         switch (variable) {
1221         case HW_VAR_C2H_HANDLE:
1222                 C2HPacketHandler_8723B(padapter, pbuf, len);
1223                 break;
1224         default:
1225                 break;
1226         }
1227 }
1228
1229 /*  */
1230 /*      Description: */
1231 /*              Query setting of specified variable. */
1232 /*  */
1233 static u8 GetHalDefVar8723BSDIO(
1234         struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue
1235 )
1236 {
1237         u8      bResult = _SUCCESS;
1238
1239         switch (eVariable) {
1240         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1241                 break;
1242         case HAL_DEF_CURRENT_ANTENNA:
1243                 break;
1244         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1245                 /*  Stanley@BB.SD3 suggests 16K can get stable performance */
1246                 /*  coding by Lucas@20130730 */
1247                 *(u32 *)pValue = IEEE80211_HT_MAX_AMPDU_16K;
1248                 break;
1249         default:
1250                 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1251                 break;
1252         }
1253
1254         return bResult;
1255 }
1256
1257 /*  */
1258 /*      Description: */
1259 /*              Change default setting of specified variable. */
1260 /*  */
1261 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter,
1262                                 enum hal_def_variable eVariable, void *pValue)
1263 {
1264         return SetHalDefVar8723B(Adapter, eVariable, pValue);
1265 }
1266
1267 void rtl8723bs_set_hal_ops(struct adapter *padapter)
1268 {
1269         struct hal_ops *pHalFunc = &padapter->HalFunc;
1270
1271         rtl8723b_set_hal_ops(pHalFunc);
1272
1273         pHalFunc->hal_init = &rtl8723bs_hal_init;
1274         pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1275
1276         pHalFunc->inirp_init = &rtl8723bs_inirp_init;
1277         pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
1278
1279         pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1280         pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1281
1282         pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1283         pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1284
1285         pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1286         pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1287         pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1288
1289         pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1290         pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1291         pHalFunc->check_ips_status = &CheckIPSStatus;
1292         pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
1293         pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1294         pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B;
1295         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
1296         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1297
1298         pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1299         pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1300         pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1301 }