1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
15 #define _RTL8723B_PHYCFG_C_
17 #include <drv_types.h>
18 #include <rtw_debug.h>
19 #include <rtl8723b_hal.h>
22 /*---------------------------Define Local Constant---------------------------*/
23 /* Channel switch:The size of command tables for switch channel*/
24 #define MAX_PRECMD_CNT 16
25 #define MAX_RFDEPENDCMD_CNT 16
26 #define MAX_POSTCMD_CNT 16
28 #define MAX_DOZE_WAITING_TIMES_9x 64
31 * Function: phy_CalculateBitShift
33 * OverView: Get shifted position of the BitMask
39 * Return: u32 Return the shift bit bit position of the mask
41 static u32 phy_CalculateBitShift(u32 BitMask)
45 for (i = 0; i <= 31; i++) {
46 if (((BitMask>>i) & 0x1) == 1)
54 * Function: PHY_QueryBBReg
56 * OverView: Read "sepcific bits" from BB register
59 * struct adapter * Adapter,
60 * u32 RegAddr, The target address to be readback
61 * u32 BitMask The target bit position in the target address
64 * Return: u32 Data The readback register value
65 * Note: This function is equal to "GetRegSetting" in PHY programming guide
67 u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
69 u32 ReturnValue = 0, OriginalValue, BitShift;
71 #if (DISABLE_BB_RF == 1)
75 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */
77 OriginalValue = rtw_read32(Adapter, RegAddr);
78 BitShift = phy_CalculateBitShift(BitMask);
79 ReturnValue = (OriginalValue & BitMask) >> BitShift;
87 * Function: PHY_SetBBReg
89 * OverView: Write "Specific bits" to BB register (page 8~)
92 * struct adapter * Adapter,
93 * u32 RegAddr, The target address to be modified
94 * u32 BitMask The target bit position in the target address
96 * u32 Data The new register value in the target bit position
97 * of the target address
101 * Note: This function is equal to "PutRegSetting" in PHY programming guide
104 void PHY_SetBBReg_8723B(
105 struct adapter *Adapter,
111 /* u16 BBWaitCounter = 0; */
112 u32 OriginalValue, BitShift;
114 #if (DISABLE_BB_RF == 1)
118 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
120 if (BitMask != bMaskDWord) { /* if not "double word" write */
121 OriginalValue = rtw_read32(Adapter, RegAddr);
122 BitShift = phy_CalculateBitShift(BitMask);
123 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
126 rtw_write32(Adapter, RegAddr, Data);
132 /* 2. RF register R/W API */
135 static u32 phy_RFSerialRead_8723B(
136 struct adapter *Adapter, enum RF_PATH eRFPath, u32 Offset
140 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
141 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
145 u32 MaskforPhySet = 0;
149 /* Make sure RF register offset is correct */
155 if (eRFPath == RF_PATH_A) {
156 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);;
157 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
158 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
160 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
161 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */
162 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
165 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
166 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
167 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
171 for (i = 0; i < 2; i++)
172 udelay(MAX_STALL_TIME);
175 if (eRFPath == RF_PATH_A)
176 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
177 else if (eRFPath == RF_PATH_B)
178 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
181 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
182 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
184 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
186 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
187 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
189 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-SI : 0x%x\n", retValue)); */
196 * Function: phy_RFSerialWrite_8723B
198 * OverView: Write data to RF register (page 8~)
201 * struct adapter * Adapter,
202 * RF_PATH eRFPath, Radio path of A/B/C/D
203 * u32 Offset, The target address to be read
204 * u32 Data The new register Data in the target bit position
205 * of the target to be read
209 * Note: Threre are three types of serial operations:
210 * 1. Software serial write
211 * 2. Hardware LSSI-Low Speed Serial Interface
212 * 3. Hardware HSSI-High speed
213 * serial write. Driver need to implement (1) and (2).
214 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
216 * Note: For RF8256 only
217 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
218 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
219 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
220 * programming guide" for more details.
221 * Thus, we define a sub-finction for RTL8526 register address conversion
222 * ===========================================================
223 * Register Mode RegCTL[1] RegCTL[0] Note
224 * (Reg00[12]) (Reg00[10])
225 * ===========================================================
226 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
227 * ------------------------------------------------------------------
228 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
229 * ------------------------------------------------------------------
230 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
231 * ------------------------------------------------------------------
233 *2008/09/02 MH Add 92S RF definition
238 static void phy_RFSerialWrite_8723B(
239 struct adapter *Adapter,
240 enum RF_PATH eRFPath,
246 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
247 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
253 /* Switch page for 8256 RF IC */
258 /* Put write addr in [5:0] and write data in [31:16] */
260 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
261 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */
264 /* Write Operation */
266 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
267 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
273 * Function: PHY_QueryRFReg
275 * OverView: Query "Specific bits" to RF register (page 8~)
278 * struct adapter * Adapter,
279 * RF_PATH eRFPath, Radio path of A/B/C/D
280 * u32 RegAddr, The target address to be read
281 * u32 BitMask The target bit position in the target address
285 * Return: u32 Readback value
286 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
288 u32 PHY_QueryRFReg_8723B(
289 struct adapter *Adapter,
295 u32 Original_Value, Readback_Value, BitShift;
297 #if (DISABLE_BB_RF == 1)
301 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
303 BitShift = phy_CalculateBitShift(BitMask);
304 Readback_Value = (Original_Value & BitMask) >> BitShift;
306 return Readback_Value;
310 * Function: PHY_SetRFReg
312 * OverView: Write "Specific bits" to RF register (page 8~)
315 * struct adapter * Adapter,
316 * RF_PATH eRFPath, Radio path of A/B/C/D
317 * u32 RegAddr, The target address to be modified
318 * u32 BitMask The target bit position in the target address
320 * u32 Data The new register Data in the target bit position
321 * of the target address
325 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
327 void PHY_SetRFReg_8723B(
328 struct adapter *Adapter,
335 u32 Original_Value, BitShift;
337 #if (DISABLE_BB_RF == 1)
341 /* RF data is 12 bits only */
342 if (BitMask != bRFRegOffsetMask) {
343 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
344 BitShift = phy_CalculateBitShift(BitMask);
345 Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
348 phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
353 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
357 /*-----------------------------------------------------------------------------
358 * Function: PHY_MACConfig8192C
360 * Overview: Condig MAC by header file or parameter file.
370 * 08/12/2008 MHC Create Version 0.
372 *---------------------------------------------------------------------------
374 s32 PHY_MACConfig8723B(struct adapter *Adapter)
376 int rtStatus = _SUCCESS;
377 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
379 s8 sz8723MACRegFile[] = RTL8723B_PHY_MACREG;
382 pszMACRegFile = sz8723MACRegFile;
387 rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
388 if (rtStatus == _FAIL) {
389 ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv);
397 * Function: phy_InitBBRFRegisterDefinition
399 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
402 * struct adapter * Adapter,
406 * Note: The initialization value is constant and it should never be changes
408 static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
410 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
412 /* RF Interface Sowrtware Control */
413 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */
414 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
416 /* RF Interface Output (and Enable) */
417 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */
418 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */
420 /* RF Interface (Output and) Enable */
421 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
422 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
424 pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
425 pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
427 pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */
428 pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */
430 /* Tranceiver Readback LSSI/HSPI mode */
431 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
432 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
433 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
434 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
438 static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
440 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
441 int rtStatus = _SUCCESS;
442 u8 sz8723BBRegFile[] = RTL8723B_PHY_REG;
443 u8 sz8723AGCTableFile[] = RTL8723B_AGC_TAB;
444 u8 sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG;
445 u8 sz8723BBRegMpFile[] = RTL8723B_PHY_REG_MP;
446 u8 sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT;
447 u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile = NULL, *pszRFTxPwrLmtFile = NULL;
449 pszBBRegFile = sz8723BBRegFile;
450 pszAGCTableFile = sz8723AGCTableFile;
451 pszBBRegPgFile = sz8723BBBRegPgFile;
452 pszBBRegMpFile = sz8723BBRegMpFile;
453 pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile;
455 /* Read Tx Power Limit File */
456 PHY_InitTxPowerLimit(Adapter);
458 Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
459 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
461 if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) {
462 if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))
466 if (rtStatus != _SUCCESS) {
467 DBG_871X("%s():Read Tx power limit fail\n", __func__);
468 goto phy_BB8190_Config_ParaFile_Fail;
473 /* 1. Read PHY_REG.TXT BB INIT!! */
475 if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) ==
477 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
481 if (rtStatus != _SUCCESS) {
482 DBG_8192C("%s():Write BB Reg Fail!!", __func__);
483 goto phy_BB8190_Config_ParaFile_Fail;
486 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
487 PHY_InitTxPowerByRate(Adapter);
489 Adapter->registrypriv.RegEnableTxPowerByRate == 1 ||
490 (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2)
492 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) ==
494 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
498 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE)
499 PHY_TxPowerByRateConfiguration(Adapter);
502 Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
503 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
505 PHY_ConvertTxPowerLimitToPowerIndex(Adapter);
507 if (rtStatus != _SUCCESS) {
508 DBG_8192C("%s():BB_PG Reg Fail!!\n", __func__);
513 /* 2. Read BB AGC table Initialization */
515 if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile,
516 CONFIG_BB_AGC_TAB) == _FAIL) {
517 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
521 if (rtStatus != _SUCCESS) {
522 DBG_8192C("%s():AGC Table Fail\n", __func__);
523 goto phy_BB8190_Config_ParaFile_Fail;
526 phy_BB8190_Config_ParaFile_Fail:
532 int PHY_BBConfig8723B(struct adapter *Adapter)
534 int rtStatus = _SUCCESS;
535 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
539 phy_InitBBRFRegisterDefinition(Adapter);
541 /* Enable BB and RF */
542 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
543 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
545 rtw_write32(Adapter, 0x948, 0x280); /* Others use Antenna S1 */
547 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
551 PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780);
553 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
555 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
558 /* Config BB and AGC */
560 rtStatus = phy_BB8723b_Config_ParaFile(Adapter);
562 /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
563 CrystalCap = pHalData->CrystalCap & 0x3F;
564 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
569 static void phy_LCK_8723B(struct adapter *Adapter)
571 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
572 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
574 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
577 int PHY_RFConfig8723B(struct adapter *Adapter)
579 int rtStatus = _SUCCESS;
584 rtStatus = PHY_RF6052_Config8723B(Adapter);
586 phy_LCK_8723B(Adapter);
587 /* PHY_BB8723B_Config_1T(Adapter); */
592 /**************************************************************************************************************
594 * The low-level interface to set TxAGC , called by both MP and Normal Driver.
597 **************************************************************************************************************/
599 void PHY_SetTxPowerIndex_8723B(
600 struct adapter *Adapter,
606 if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) {
609 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
612 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
615 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
618 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
622 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
625 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
628 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
631 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
635 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
638 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
641 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
644 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
648 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
651 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
654 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
657 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
661 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
664 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
667 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
670 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
674 DBG_871X("Invalid Rate!!\n");
678 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n"));
682 u8 PHY_GetTxPowerIndex_8723B(
683 struct adapter *padapter,
686 enum CHANNEL_WIDTH BandWidth,
690 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
691 s8 txPower = 0, powerDiffByRate = 0, limit = 0;
694 /* DBG_871X("===>%s\n", __func__); */
696 txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
697 powerDiffByRate = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
699 limit = PHY_GetTxPowerLimit(
701 padapter->registrypriv.RegPwrTblSel,
703 pHalData->CurrentChannelBW,
706 pHalData->CurrentChannel
709 powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate;
710 txPower += powerDiffByRate;
712 txPower += PHY_GetTxPowerTrackingOffset(padapter, RFPath, Rate);
714 if (txPower > MAX_POWER_INDEX)
715 txPower = MAX_POWER_INDEX;
717 /* DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath == 0)?'A':'B'), Channel, txPower, txPower)); */
721 void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)
723 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
724 PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
725 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
726 u8 RFPath = ODM_RF_PATH_A;
728 if (pHalData->AntDivCfg) {/* antenna diversity Enable */
729 RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
730 } else { /* antenna diversity disable */
731 RFPath = pHalData->ant_path;
734 RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8723B()\n"));
736 PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);
738 RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8723B()\n"));
741 void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel)
745 static void phy_SetRegBW_8723B(
746 struct adapter *Adapter, enum CHANNEL_WIDTH CurrentBW
749 u16 RegRfMod_BW, u2tmp = 0;
750 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B);
753 case CHANNEL_WIDTH_20:
754 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */
757 case CHANNEL_WIDTH_40:
758 u2tmp = RegRfMod_BW | BIT7;
759 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */
762 case CHANNEL_WIDTH_80:
763 u2tmp = RegRfMod_BW | BIT8;
764 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */
768 DBG_871X("phy_PostSetBWMode8723B(): unknown Bandwidth: %#X\n", CurrentBW);
773 static u8 phy_GetSecondaryChnl_8723B(struct adapter *Adapter)
775 u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
776 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
782 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",
783 pHalData->CurrentChannelBW,
784 pHalData->nCur80MhzPrimeSC,
785 pHalData->nCur40MhzPrimeSC
788 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
789 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
790 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
791 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
792 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
794 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
797 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
798 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
800 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
802 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
803 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
805 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
807 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
808 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
810 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
812 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
813 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
815 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
817 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
818 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
823 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n",
824 pHalData->CurrentChannelBW,
825 pHalData->nCur40MhzPrimeSC
829 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
830 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
831 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
832 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
834 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
837 RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20)));
838 return ((SCSettingOf40 << 4) | SCSettingOf20);
841 static void phy_PostSetBwMode8723B(struct adapter *Adapter)
844 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
847 /* 3 Set Reg668 Reg440 BW */
848 phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
851 SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter);
852 rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum);
855 /* 3<2>Set PHY related register */
857 switch (pHalData->CurrentChannelBW) {
859 case CHANNEL_WIDTH_20:
860 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
862 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
864 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
866 PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
870 case CHANNEL_WIDTH_40:
871 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
873 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
875 /* Set Control channel to upper or lower. These settings are required only for 40MHz */
876 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
878 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
880 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */
882 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
887 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\
888 , pHalData->CurrentChannelBW));*/
892 /* 3<3>Set RF related register */
893 PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW);
896 static void phy_SwChnl8723B(struct adapter *padapter)
898 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
899 u8 channelToSW = pHalData->CurrentChannel;
901 if (pHalData->rf_chip == RF_PSEUDO_11N) {
902 /* RT_TRACE(COMP_MLME, DBG_LOUD, ("phy_SwChnl8723B: return for PSEUDO\n")); */
905 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
906 PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
907 PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
909 DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW);
912 static void phy_SwChnlAndSetBwMode8723B(struct adapter *Adapter)
914 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
916 /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */
917 if (Adapter->bNotifyChannelChange) {
918 DBG_871X("[%s] bSwChnl =%d, ch =%d, bSetChnlBW =%d, bw =%d\n",
921 pHalData->CurrentChannel,
922 pHalData->bSetChnlBW,
923 pHalData->CurrentChannelBW);
926 if (Adapter->bDriverStopped || Adapter->bSurpriseRemoved)
929 if (pHalData->bSwChnl) {
930 phy_SwChnl8723B(Adapter);
931 pHalData->bSwChnl = false;
934 if (pHalData->bSetChnlBW) {
935 phy_PostSetBwMode8723B(Adapter);
936 pHalData->bSetChnlBW = false;
939 PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel);
942 static void PHY_HandleSwChnlAndSetBW8723B(
943 struct adapter *Adapter,
947 enum CHANNEL_WIDTH ChnlWidth,
948 enum EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
949 enum EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
950 u8 CenterFrequencyIndex1
953 /* static bool bInitialzed = false; */
954 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
955 u8 tmpChannel = pHalData->CurrentChannel;
956 enum CHANNEL_WIDTH tmpBW = pHalData->CurrentChannelBW;
957 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
958 u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
959 u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
961 /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */
963 /* check is swchnl or setbw */
964 if (!bSwitchChannel && !bSetBandWidth) {
965 DBG_871X("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth\n");
969 /* skip change for channel or bandwidth is the same */
970 if (bSwitchChannel) {
971 /* if (pHalData->CurrentChannel != ChannelNum) */
973 if (HAL_IsLegalChannel(Adapter, ChannelNum))
974 pHalData->bSwChnl = true;
979 pHalData->bSetChnlBW = true;
981 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
982 /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */
987 if (pHalData->bSwChnl) {
988 pHalData->CurrentChannel = ChannelNum;
989 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
993 if (pHalData->bSetChnlBW) {
994 pHalData->CurrentChannelBW = ChnlWidth;
995 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
996 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
997 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1000 /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1001 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
1002 phy_SwChnlAndSetBwMode8723B(Adapter);
1004 if (pHalData->bSwChnl) {
1005 pHalData->CurrentChannel = tmpChannel;
1006 pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1009 if (pHalData->bSetChnlBW) {
1010 pHalData->CurrentChannelBW = tmpBW;
1011 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1012 pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1013 pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1018 void PHY_SetBWMode8723B(
1019 struct adapter *Adapter,
1020 enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
1021 unsigned char Offset /* Upper, Lower, or Don't care */
1024 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1026 PHY_HandleSwChnlAndSetBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel);
1029 /* Call after initialization */
1030 void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel)
1032 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, false, channel, 0, 0, 0, channel);
1035 void PHY_SetSwChnlBWMode8723B(
1036 struct adapter *Adapter,
1038 enum CHANNEL_WIDTH Bandwidth,
1043 /* DBG_871X("%s() ===>\n", __func__); */
1045 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Offset40, Offset80, channel);
1047 /* DBG_871X("<==%s()\n", __func__); */