1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
7 #ifndef __ODM_TYPES_H__
8 #define __ODM_TYPES_H__
10 #include <drv_types.h>
12 /* Deifne HW endian support */
13 #define ODM_ENDIAN_BIG 0
14 #define ODM_ENDIAN_LITTLE 1
16 #define GET_ODM(__padapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__padapter))->odmpriv)))
18 typedef enum _HAL_STATUS {
23 RT_STATUS_INVALID_CONTEXT,
24 RT_STATUS_INVALID_PARAMETER,
25 RT_STATUS_NOT_SUPPORT,
26 RT_STATUS_OS_API_FAILED,*/
27 } HAL_STATUS, *PHAL_STATUS;
31 /* Declare for ODM spin lock defintion temporarily fro compile pass. */
33 typedef enum _RT_SPINLOCK_TYPE {
41 RT_CHNLOP_SPINLOCK = 9,
42 RT_RF_OPERATE_SPINLOCK = 10,
43 RT_INITIAL_SPINLOCK = 11,
44 RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */
45 /* Shall we define Ndis 6.2 SpinLock Here ? */
46 RT_PORT_SPINLOCK = 16,
47 RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
49 RT_BTData_SPINLOCK = 25,
51 RT_WAPI_OPTION_SPINLOCK = 26,
52 RT_WAPI_RX_SPINLOCK = 27,
54 /* add for 92D CCK control issue */
55 RT_CCK_PAGEA_SPINLOCK = 28,
56 RT_BUFFER_SPINLOCK = 29,
57 RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
58 RT_GEN_TEMP_BUF_SPINLOCK = 31,
60 RT_FW_PS_SPINLOCK = 33,
61 RT_HW_TIMER_SPIN_LOCK = 34,
62 RT_MPT_WI_SPINLOCK = 35,
63 RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
64 RT_DBG_SPIN_LOCK = 37,
66 RT_PENDED_OID_SPINLOCK = 39,
67 RT_CHNLLIST_SPINLOCK = 40,
68 RT_INDIC_SPINLOCK = 41, /* protect indication */
71 #if defined(__LITTLE_ENDIAN)
72 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
74 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
77 typedef struct timer_list RT_TIMER, *PRT_TIMER;
78 typedef void *RT_TIMER_CALL_BACK;
79 #define STA_INFO_T struct sta_info
80 #define PSTA_INFO_T struct sta_info *
82 #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
83 #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
84 #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
86 /* define useless flag to avoid compile warning */
87 #define USE_WORKITEM 0
88 #define FPGA_TWO_MAC_VERIFICATION 0
90 #define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0)
94 #endif /* __ODM_TYPES_H__ */