drivers/staging/rtl8723bs/hal/odm_reg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 /*  File Name: odm_reg.h */
   8 /*  Description: */
   9 /*  This file is for general register definition. */
  10 #ifndef __HAL_ODM_REG_H__
  11 #define __HAL_ODM_REG_H__
  12
  13 /*  Register Definition */
  14
  15 /* MAC REG */
  16 #define ODM_BB_RESET                            0x002
  17 #define ODM_DUMMY                               0x4fe
  18 #define RF_T_METER_OLD                          0x24
  19 #define RF_T_METER_NEW                          0x42
  20
  21 #define ODM_EDCA_VO_PARAM                       0x500
  22 #define ODM_EDCA_VI_PARAM                       0x504
  23 #define ODM_EDCA_BE_PARAM                       0x508
  24 #define ODM_EDCA_BK_PARAM                       0x50C
  25 #define ODM_TXPAUSE                             0x522
  26
  27 /* BB REG */
  28 #define ODM_FPGA_PHY0_PAGE8                     0x800
  29 #define ODM_PSD_SETTING                         0x808
  30 #define ODM_AFE_SETTING                         0x818
  31 #define ODM_TXAGC_B_24_54                       0x834
  32 #define ODM_TXAGC_B_MCS32_5                     0x838
  33 #define ODM_TXAGC_B_MCS0_MCS3                   0x83c
  34 #define ODM_TXAGC_B_MCS4_MCS7                   0x848
  35 #define ODM_ANALOG_REGISTER                     0x85c
  36 #define ODM_RF_INTERFACE_OUTPUT                 0x860
  37 #define ODM_TXAGC_B_11_A_2_11                   0x86c
  38 #define ODM_AD_DA_LSB_MASK                      0x874
  39 #define ODM_ENABLE_3_WIRE                       0x88c
  40 #define ODM_PSD_REPORT                          0x8b4
  41 #define ODM_R_ANT_SELECT                        0x90c
  42 #define ODM_CCK_ANT_SELECT                      0xa07
  43 #define ODM_CCK_PD_THRESH                       0xa0a
  44 #define ODM_CCK_RF_REG1                         0xa11
  45 #define ODM_CCK_MATCH_FILTER                    0xa20
  46 #define ODM_CCK_RAKE_MAC                        0xa2e
  47 #define ODM_CCK_CNT_RESET                       0xa2d
  48 #define ODM_CCK_TX_DIVERSITY                    0xa2f
  49 #define ODM_CCK_FA_CNT_MSB                      0xa5b
  50 #define ODM_CCK_FA_CNT_LSB                      0xa5c
  51 #define ODM_CCK_NEW_FUNCTION                    0xa75
  52 #define ODM_OFDM_PHY0_PAGE_C                    0xc00
  53 #define ODM_OFDM_RX_ANT                         0xc04
  54 #define ODM_R_A_RXIQI                           0xc14
  55 #define ODM_R_A_AGC_CORE1                       0xc50
  56 #define ODM_R_A_AGC_CORE2                       0xc54
  57 #define ODM_R_B_AGC_CORE1                       0xc58
  58 #define ODM_R_AGC_PAR                           0xc70
  59 #define ODM_R_HTSTF_AGC_PAR                     0xc7c
  60 #define ODM_TX_PWR_TRAINING_A                   0xc90
  61 #define ODM_TX_PWR_TRAINING_B                   0xc98
  62 #define ODM_OFDM_FA_CNT1                        0xcf0
  63 #define ODM_OFDM_PHY0_PAGE_D                    0xd00
  64 #define ODM_OFDM_FA_CNT2                        0xda0
  65 #define ODM_OFDM_FA_CNT3                        0xda4
  66 #define ODM_OFDM_FA_CNT4                        0xda8
  67 #define ODM_TXAGC_A_6_18                        0xe00
  68 #define ODM_TXAGC_A_24_54                       0xe04
  69 #define ODM_TXAGC_A_1_MCS32                     0xe08
  70 #define ODM_TXAGC_A_MCS0_MCS3                   0xe10
  71 #define ODM_TXAGC_A_MCS4_MCS7                   0xe14
  72
  73 /* RF REG */
  74 #define ODM_GAIN_SETTING                        0x00
  75 #define ODM_CHANNEL                             0x18
  76
  77 /* Ant Detect Reg */
  78 #define ODM_DPDT                                0x300
  79
  80 /* PSD Init */
  81 #define ODM_PSDREG                              0x808
  82
  83 /* 92D Path Div */
  84 #define PATHDIV_REG                             0xB30
  85 #define PATHDIV_TRI                             0xBA0
  86
  87 /*  Bitmap Definition */
  88
  89 #define BIT_FA_RESET                            BIT0
  90
  91 #endif