drivers/staging/rtl8723bs/hal/odm_RegConfig8723B.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include "odm_precomp.h"
  17
  18 void odm_ConfigRFReg_8723B(
  19         PDM_ODM_T pDM_Odm,
  20         u32 Addr,
  21         u32 Data,
  22         ODM_RF_RADIO_PATH_E RF_PATH,
  23         u32 RegAddr
  24 )
  25 {
  26         if (Addr == 0xfe || Addr == 0xffe)
  27                 msleep(50);
  28         else {
  29                 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  30                 /*  Add 1us delay between BB/RF register setting. */
  31                 udelay(1);
  32
  33                 /* For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. */
  34                 if (Addr == 0xb6) {
  35                         u32 getvalue = 0;
  36                         u8 count = 0;
  37
  38                         getvalue = PHY_QueryRFReg(
  39                                 pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
  40                         );
  41
  42                         udelay(1);
  43
  44                         while ((getvalue>>8) != (Data>>8)) {
  45                                 count++;
  46                                 PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
  47                                 udelay(1);
  48                                 getvalue = PHY_QueryRFReg(pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord);
  49                                 ODM_RT_TRACE(
  50                                         pDM_Odm,
  51                                         ODM_COMP_INIT,
  52                                         ODM_DBG_TRACE,
  53                                         (
  54                                                 "===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n",
  55                                                 getvalue,
  56                                                 Data,
  57                                                 count
  58                                         )
  59                                 );
  60                                 if (count > 5)
  61                                         break;
  62                         }
  63                 }
  64
  65                 if (Addr == 0xb2) {
  66                         u32 getvalue = 0;
  67                         u8 count = 0;
  68
  69                         getvalue = PHY_QueryRFReg(
  70                                 pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
  71                         );
  72
  73                         udelay(1);
  74
  75                         while (getvalue != Data) {
  76                                 count++;
  77                                 PHY_SetRFReg(
  78                                         pDM_Odm->Adapter,
  79                                         RF_PATH,
  80                                         RegAddr,
  81                                         bRFRegOffsetMask,
  82                                         Data
  83                                 );
  84                                 udelay(1);
  85                                 /* Do LCK againg */
  86                                 PHY_SetRFReg(
  87                                         pDM_Odm->Adapter,
  88                                         RF_PATH,
  89                                         0x18,
  90                                         bRFRegOffsetMask,
  91                                         0x0fc07
  92                                 );
  93                                 udelay(1);
  94                                 getvalue = PHY_QueryRFReg(
  95                                         pDM_Odm->Adapter, RF_PATH, Addr, bMaskDWord
  96                                 );
  97                                 ODM_RT_TRACE(
  98                                         pDM_Odm,
  99                                         ODM_COMP_INIT,
 100                                         ODM_DBG_TRACE,
 101                                         (
 102                                                 "===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n",
 103                                                 getvalue,
 104                                                 Data,
 105                                                 count
 106                                         )
 107                                 );
 108
 109                                 if (count > 5)
 110                                         break;
 111                         }
 112                 }
 113         }
 114 }
 115
 116
 117 void odm_ConfigRF_RadioA_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u32 Data)
 118 {
 119         u32  content = 0x1000; /*  RF_Content: radioa_txt */
 120         u32 maskforPhySet = (u32)(content&0xE000);
 121
 122         odm_ConfigRFReg_8723B(
 123                 pDM_Odm,
 124                 Addr,
 125                 Data,
 126                 ODM_RF_PATH_A,
 127                 Addr|maskforPhySet
 128         );
 129
 130         ODM_RT_TRACE(
 131                 pDM_Odm,
 132                 ODM_COMP_INIT,
 133                 ODM_DBG_TRACE,
 134                 (
 135                         "===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n",
 136                         Addr,
 137                         Data
 138                 )
 139         );
 140 }
 141
 142 void odm_ConfigMAC_8723B(PDM_ODM_T pDM_Odm, u32 Addr, u8 Data)
 143 {
 144         rtw_write8(pDM_Odm->Adapter, Addr, Data);
 145         ODM_RT_TRACE(
 146                 pDM_Odm,
 147                 ODM_COMP_INIT,
 148                 ODM_DBG_TRACE,
 149                 (
 150                         "===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n",
 151                         Addr,
 152                         Data
 153                 )
 154         );
 155 }
 156
 157 void odm_ConfigBB_AGC_8723B(
 158         PDM_ODM_T pDM_Odm,
 159         u32 Addr,
 160         u32 Bitmask,
 161         u32 Data
 162 )
 163 {
 164         PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
 165         /*  Add 1us delay between BB/RF register setting. */
 166         udelay(1);
 167
 168         ODM_RT_TRACE(
 169                 pDM_Odm,
 170                 ODM_COMP_INIT,
 171                 ODM_DBG_TRACE,
 172                 (
 173                         "===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n",
 174                         Addr,
 175                         Data
 176                 )
 177         );
 178 }
 179
 180 void odm_ConfigBB_PHY_REG_PG_8723B(
 181         PDM_ODM_T pDM_Odm,
 182         u32 Band,
 183         u32 RfPath,
 184         u32 TxNum,
 185         u32 Addr,
 186         u32 Bitmask,
 187         u32 Data
 188 )
 189 {
 190         if (Addr == 0xfe || Addr == 0xffe)
 191                 msleep(50);
 192         else {
 193                 PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
 194         }
 195         ODM_RT_TRACE(
 196                 pDM_Odm,
 197                 ODM_COMP_INIT,
 198                 ODM_DBG_LOUD,
 199                 (
 200                         "===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n",
 201                         Addr,
 202                         Bitmask,
 203                         Data
 204                 )
 205         );
 206 }
 207
 208 void odm_ConfigBB_PHY_8723B(
 209         PDM_ODM_T pDM_Odm,
 210         u32 Addr,
 211         u32 Bitmask,
 212         u32 Data
 213 )
 214 {
 215         if (Addr == 0xfe)
 216                 msleep(50);
 217         else if (Addr == 0xfd)
 218                 mdelay(5);
 219         else if (Addr == 0xfc)
 220                 mdelay(1);
 221         else if (Addr == 0xfb)
 222                 udelay(50);
 223         else if (Addr == 0xfa)
 224                 udelay(5);
 225         else if (Addr == 0xf9)
 226                 udelay(1);
 227         else {
 228                 PHY_SetBBReg(pDM_Odm->Adapter, Addr, Bitmask, Data);
 229         }
 230
 231         /*  Add 1us delay between BB/RF register setting. */
 232         udelay(1);
 233         ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
 234 }
 235
 236 void odm_ConfigBB_TXPWR_LMT_8723B(
 237         PDM_ODM_T pDM_Odm,
 238         u8 *Regulation,
 239         u8 *Band,
 240         u8 *Bandwidth,
 241         u8 *RateSection,
 242         u8 *RfPath,
 243         u8 *Channel,
 244         u8 *PowerLimit
 245 )
 246 {
 247         PHY_SetTxPowerLimit(
 248                 pDM_Odm->Adapter,
 249                 Regulation,
 250                 Band,
 251                 Bandwidth,
 252                 RateSection,
 253                 RfPath,
 254                 Channel,
 255                 PowerLimit
 256         );
 257 }