1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
9 #ifndef __HALHWOUTSRC_H__
10 #define __HALHWOUTSRC_H__
13 /*--------------------------Define -------------------------------------------*/
14 /* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
15 #define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
16 sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
17 #define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
18 sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
20 #define AGC_DIFF_CONFIG(ic, band)\
22 if (pDM_Odm->bIsMPChip)\
23 AGC_DIFF_CONFIG_MP(ic, band);\
25 AGC_DIFF_CONFIG_TC(ic, band);\
30 /* structure and define */
33 typedef struct _Phy_Rx_AGC_Info {
34 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
39 } PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
41 typedef struct _Phy_Status_Rpt_8192cd {
42 PHY_RX_AGC_INFO_T path_agc[2];
44 u8 cck_sig_qual_ofdm_pwdb_all;
45 u8 cck_agc_rpt_ofdm_cfosho_a;
46 u8 cck_rpt_b_ofdm_cfosho_b;
47 u8 rsvd_1;/* ch_corr_msb; */
48 u8 noise_power_db_msb;
53 u8 noise_power_db_lsb;
56 u8 stream_target_csi[2];
60 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
61 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
68 #else /* _BIG_ENDIAN_ */
75 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
77 } PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
80 typedef struct _Phy_Status_Rpt_8812 {
81 /* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
85 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
89 #else /* _BIG_ENDIAN_ */
97 u8 cfosho[4]; /* DW 1 byte 1 DW 2 byte 0 */
100 s8 cfotail[4]; /* DW 2 byte 1 DW 3 byte 0 */
103 s8 rxevm[2]; /* DW 3 byte 1 DW 3 byte 2 */
104 s8 rxsnr[2]; /* DW 3 byte 3 DW 4 byte 0 */
108 u8 pdsnr[2]; /* DW 4 byte 3 DW 5 Byte 0 */
121 } PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
124 void ODM_PhyStatusQuery(
126 struct odm_phy_info *pPhyInfo,
128 struct odm_packet_info *pPktinfo
131 HAL_STATUS ODM_ConfigRFWithTxPwrTrackHeaderFile(PDM_ODM_T pDM_Odm);
133 HAL_STATUS ODM_ConfigRFWithHeaderFile(
135 ODM_RF_Config_Type ConfigType,
136 ODM_RF_RADIO_PATH_E eRFPath
139 HAL_STATUS ODM_ConfigBBWithHeaderFile(
140 PDM_ODM_T pDM_Odm, ODM_BB_Config_Type ConfigType
143 HAL_STATUS ODM_ConfigFWWithHeaderFile(
145 ODM_FW_Config_Type ConfigType,
150 s32 odm_SignalScaleMapping(PDM_ODM_T pDM_Odm, s32 CurrSig);