1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
6 ******************************************************************************/
9 #ifndef __HALDMOUTSRC_H__
10 #define __HALDMOUTSRC_H__
12 #include "odm_EdcaTurboCheck.h"
14 #include "odm_DynamicBBPowerSaving.h"
15 #include "odm_DynamicTxPower.h"
16 #include "odm_CfoTracking.h"
17 #include "odm_NoiseMonitor.h"
22 #define TRAFFIC_HIGH 1
25 /* 3 Tx Power Tracking */
26 /* 3 ============================================================ */
27 #define DPK_DELTA_MAPPING_NUM 13
28 #define index_mapping_HP_NUM 15
29 #define OFDM_TABLE_SIZE 43
30 #define CCK_TABLE_SIZE 33
31 #define TXSCALE_TABLE_SIZE 37
32 #define TXPWR_TRACK_TABLE_SIZE 30
33 #define DELTA_SWINGIDX_SIZE 30
37 /* 3 ============================================================ */
39 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
40 #define MODE_40M 0 /* 0:20M, 1:40M */
42 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */
43 #define SIR_STEP_SIZE 3
44 #define Smooth_Size_1 5
46 #define Smooth_Size_2 10
48 #define Smooth_Size_3 20
50 #define Smooth_Step_Size 5
51 #define Adaptive_SIR 1
53 #define PSD_SCAN_INTERVAL 700 /* ms */
55 /* 8723A High Power IGI Setting */
56 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
57 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
58 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
59 #define DM_DIG_LOW_PWR_THRESHOLD 0x14
62 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
63 #define ANTTESTA 0x01 /* Ant A will be Testing */
64 #define ANTTESTB 0x02 /* Ant B will be testing */
66 #define PS_MODE_ACTIVE 0x01
68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
69 #define MAIN_ANT 1 /* Ant A or Ant Main */
70 #define AUX_ANT 2 /* AntB or Ant Aux */
71 #define MAX_ANT 3 /* 3 for AP using */
73 /* Antenna Diversity Type */
76 /* structure and define */
78 /* Remove DIG by Yuchen */
80 /* Remoce BB power saving by Yuchn */
82 /* Remove DIG by yuchen */
84 struct dynamic_primary_CCA {
101 u8 PSD_bitmap_RXHP[80];
106 bool First_time_enter;
109 struct timer_list PSDTimer;
112 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
113 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
115 /* This indicates two different the steps. */
116 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
117 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
118 /* with original RSSI to determine if it is necessary to switch antenna. */
119 #define SWAW_STEP_PEAK 0
120 #define SWAW_STEP_DETERMINE 1
124 #define TRAFFIC_LOW 0
125 #define TRAFFIC_HIGH 1
126 #define TRAFFIC_UltraLOW 2
128 struct swat_t { /* _SW_Antenna_Switch_ */
136 u8 bTriggerAntennaSwitch;
140 u16 Single_Ant_Counter;
141 u16 Dual_Ant_Counter;
142 u16 Aux_FailDetec_Counter;
145 /* Before link Antenna Switch check */
146 u8 SWAS_NoLink_State;
147 u32 SWAS_NoLink_BK_Reg860;
148 u32 SWAS_NoLink_BK_Reg92c;
149 u32 SWAS_NoLink_BK_Reg948;
150 bool ANTA_ON; /* To indicate Ant A is or not */
151 bool ANTB_ON; /* To indicate Ant B is on or not */
152 bool Pre_Aux_FailDetec;
153 bool RSSI_AntDect_bResult;
170 struct timer_list SwAntennaSwitchTimer;
171 struct timer_list SwAntennaSwitchTimer_8723B;
172 u32 PktCnt_SWAntDivByCtrlFrame;
173 bool bSWAntDivByCtrlFrame;
176 /* Remove Edca by YuChen */
179 struct odm_rate_adaptive {
180 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
181 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */
184 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
185 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
186 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
190 #define IQK_MAC_REG_NUM 4
191 #define IQK_ADDA_REG_NUM 16
192 #define IQK_BB_REG_NUM_MAX 10
193 #define IQK_BB_REG_NUM 9
194 #define HP_THERMAL_NUM 8
196 #define AVG_THERMAL_NUM 8
197 #define IQK_Matrix_REG_NUM 8
198 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */
200 #define DM_Type_ByFW 0
201 #define DM_Type_ByDriver 1
204 /* Declare for common info */
206 #define MAX_PATH_NUM_92CS 2
207 #define MAX_PATH_NUM_8188E 1
208 #define MAX_PATH_NUM_8192E 2
209 #define MAX_PATH_NUM_8723B 1
210 #define MAX_PATH_NUM_8812A 2
211 #define MAX_PATH_NUM_8821A 1
212 #define MAX_PATH_NUM_8814A 4
213 #define MAX_PATH_NUM_8822B 2
215 #define IQK_THRESHOLD 8
216 #define DPK_THRESHOLD 4
218 struct odm_phy_info {
220 * Be care, if you want to add any element, please insert it between
221 * rx_pwd_ball and signal_strength.
225 u8 signal_quality; /* in 0-100 index. */
226 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */
227 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */
229 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
231 u16 cfo_short[4]; /* per-path's Cfo_short */
232 u16 cfo_tail[4]; /* per-path's Cfo_tail */
234 s8 rx_power; /* in dBm Translate from PWdB */
237 * Real power in dBm for this packet, no beautification and
238 * aggregation. Keep this raw info to be used for the other procedures.
240 s8 recv_signal_power;
241 u8 bt_rx_rssi_percentage;
242 u8 signal_strength; /* in 0-100 index. */
244 s8 rx_pwr[4]; /* per-path's pwdb */
246 u8 rx_snr[4]; /* per-path's SNR */
248 u8 bt_coex_pwr_adjust;
251 struct odm_packet_info {
259 struct odm_phy_dbg_info {
260 /* ODM Write, debug info */
263 u32 NumQryPhyStatusCCK;
264 u32 NumQryPhyStatusOFDM;
271 struct odm_mac_status_info {
276 /* 2011/10/20 MH Define Common info enum for all team. */
281 /* HOOK BEFORE REG INIT----------- */
282 ODM_CMNINFO_PLATFORM = 0,
283 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
284 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
285 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
286 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
287 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
288 ODM_CMNINFO_RFE_TYPE,
289 ODM_CMNINFO_PACKAGE_TYPE,
290 ODM_CMNINFO_EXT_LNA, /* true */
296 ODM_CMNINFO_EXT_TRSW,
297 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
298 ODM_CMNINFO_BINHCT_TEST,
299 ODM_CMNINFO_BWIFI_TEST,
300 ODM_CMNINFO_SMART_CONCURRENT,
301 /* HOOK BEFORE REG INIT----------- */
304 /* POINTER REFERENCE----------- */
305 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
308 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
309 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
310 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
311 ODM_CMNINFO_BW, /* ODM_BW_E */
313 ODM_CMNINFO_FORCED_RATE,
315 ODM_CMNINFO_DMSP_GET_VALUE,
316 ODM_CMNINFO_BUDDY_ADAPTOR,
317 ODM_CMNINFO_DMSP_IS_MASTER,
319 ODM_CMNINFO_POWER_SAVING,
320 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
321 ODM_CMNINFO_DRV_STOP,
324 ODM_CMNINFO_ANT_TEST,
325 ODM_CMNINFO_NET_CLOSED,
327 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */
328 ODM_CMNINFO_FORCED_IGI_LB,
329 ODM_CMNINFO_IS1ANTENNA,
330 ODM_CMNINFO_RFDEFAULTPATH,
331 /* POINTER REFERENCE----------- */
333 /* CALL BY VALUE------------- */
334 ODM_CMNINFO_WIFI_DIRECT,
335 ODM_CMNINFO_WIFI_DISPLAY,
336 ODM_CMNINFO_LINK_IN_PROGRESS,
338 ODM_CMNINFO_STATION_STATE,
339 ODM_CMNINFO_RSSI_MIN,
340 ODM_CMNINFO_DBG_COMP, /* u64 */
341 ODM_CMNINFO_DBG_LEVEL, /* u32 */
342 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
343 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
344 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
345 ODM_CMNINFO_BT_ENABLED,
346 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
347 ODM_CMNINFO_BT_HS_RSSI,
348 ODM_CMNINFO_BT_OPERATION,
349 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */
350 ODM_CMNINFO_BT_DISABLE_EDCA,
351 /* CALL BY VALUE------------- */
353 /* Dynamic ptr array hook itms. */
354 ODM_CMNINFO_STA_STATUS,
355 ODM_CMNINFO_PHY_STATUS,
356 ODM_CMNINFO_MAC_STATUS,
361 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
362 enum { /* _ODM_Support_Ability_Definition */
364 /* BB ODM section BIT 0-15 */
367 ODM_BB_RA_MASK = BIT1,
368 ODM_BB_DYNAMIC_TXPWR = BIT2,
369 ODM_BB_FA_CNT = BIT3,
370 ODM_BB_RSSI_MONITOR = BIT4,
371 ODM_BB_CCK_PD = BIT5,
372 ODM_BB_ANT_DIV = BIT6,
373 ODM_BB_PWR_SAVE = BIT7,
374 ODM_BB_PWR_TRAIN = BIT8,
375 ODM_BB_RATE_ADAPTIVE = BIT9,
376 ODM_BB_PATH_DIV = BIT10,
379 ODM_BB_ADAPTIVITY = BIT13,
380 ODM_BB_CFO_TRACKING = BIT14,
382 /* MAC DM section BIT 16-23 */
383 ODM_MAC_EDCA_TURBO = BIT16,
384 ODM_MAC_EARLY_MODE = BIT17,
386 /* RF ODM section BIT 24-31 */
387 ODM_RF_TX_PWR_TRACK = BIT24,
388 ODM_RF_RX_GAIN_TRACK = BIT25,
389 ODM_RF_CALIBRATION = BIT26,
392 /* ODM_CMNINFO_INTERFACE */
393 enum { /* tag_ODM_Support_Interface_Definition */
398 /* ODM_CMNINFO_IC_TYPE */
399 enum { /* tag_ODM_Support_IC_Type_Definition */
403 /* ODM_CMNINFO_CUT_VER */
404 enum { /* tag_ODM_Cut_Version_Definition */
418 /* ODM_CMNINFO_FAB_VER */
419 enum { /* tag_ODM_Fab_Version_Definition */
425 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
427 enum { /* tag_ODM_RF_Type_Definition */
439 /* ODM Dynamic common info value definition */
442 /* ODM_CMNINFO_WM_MODE */
443 enum { /* tag_Wireless_Mode_Definition */
444 ODM_WM_UNKNOWN = 0x0,
452 enum { /* tag_Bandwidth_Definition */
457 /* For AC-series IC, external PA & LNA can be individually added on 2.4G */
459 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */
461 TYPE_GPA1 = BIT(1)|BIT(0)
464 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */
466 TYPE_APA1 = BIT(1)|BIT(0)
469 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */
471 TYPE_GLNA1 = BIT(2)|BIT(0),
472 TYPE_GLNA2 = BIT(3)|BIT(1),
473 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
476 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */
478 TYPE_ALNA1 = BIT(2)|BIT(0),
479 TYPE_ALNA2 = BIT(3)|BIT(1),
480 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
483 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */
485 s32 Value[3][IQK_Matrix_REG_NUM];
486 bool bBWIqkResultSaved[3];
489 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
491 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */
492 /* for tx power tracking */
494 u32 RegA24; /* for TempCCK */
501 bool bTXPowerTrackingInit;
502 bool bTXPowerTracking;
503 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
506 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
511 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
512 u8 ThermalValue_AVG_index;
513 u8 ThermalValue_RxGain;
514 u8 ThermalValue_Crystal;
515 u8 ThermalValue_DPKstore;
516 u8 ThermalValue_DPKtrack;
517 bool TxPowerTrackingInProgress;
519 bool bReloadtxpowerindex;
521 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
523 /* Tx power Tracking ------------------------- */
526 u8 OFDM_index[MAX_RF_PATH];
527 s8 PowerIndexOffset[MAX_RF_PATH];
528 s8 DeltaPowerIndex[MAX_RF_PATH];
529 s8 DeltaPowerIndexLast[MAX_RF_PATH];
530 bool bTxPowerChanged;
532 u8 ThermalValue_HP[HP_THERMAL_NUM];
533 u8 ThermalValue_HP_index;
534 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
539 s8 BBSwingDiff2G; /* Unit: dB */
540 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
541 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
542 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
543 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
544 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
545 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
546 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
547 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
548 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
549 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
563 bool bIQKInitialized;
565 bool bAntennaDetected;
566 u32 ADDA_backup[IQK_ADDA_REG_NUM];
567 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
568 u32 IQK_BB_backup_recover[9];
569 u32 IQK_BB_backup[IQK_BB_REG_NUM];
570 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
571 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
574 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
576 u8 bAPKThermalMeterIgnore;
588 /* ODM Dynamic common info value definition */
591 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */
602 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
603 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
604 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
605 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
606 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
607 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
608 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
612 u8 idx_AntDiv_counter_2G;
613 u32 CCK_counter_main;
615 u32 OFDM_counter_main;
616 u32 OFDM_counter_aux;
618 u32 CCK_CtrlFrame_Cnt_main;
619 u32 CCK_CtrlFrame_Cnt_aux;
620 u32 OFDM_CtrlFrame_Cnt_main;
621 u32 OFDM_CtrlFrame_Cnt_aux;
622 u32 MainAnt_CtrlFrame_Sum;
623 u32 AuxAnt_CtrlFrame_Sum;
624 u32 MainAnt_CtrlFrame_Cnt;
625 u32 AuxAnt_CtrlFrame_Cnt;
631 CG_TRX_HW_ANTDIV = 0x01,
632 CGCS_RX_HW_ANTDIV = 0x02,
633 FIXED_HW_ANTDIV = 0x03,
634 CG_TRX_SMART_ANTDIV = 0x04,
635 CGCS_RX_SW_ANTDIV = 0x05,
636 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */
639 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */
641 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
642 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
643 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
644 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
645 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
648 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */
649 PHY_REG_PG_RELATIVE_VALUE = 0,
650 PHY_REG_PG_EXACT_VALUE = 1
654 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
656 struct ant_detected_info {
664 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
666 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */
667 /* struct timer_list FastAntTrainingTimer; */
669 /* Add for different team use temporarily */
671 struct adapter *Adapter; /* For CE/NIC team */
672 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
675 enum phy_reg_pg_type PhyRegPgValueType;
678 u32 NumQryPhyStatusAll; /* CCK + OFDM */
679 u32 LastNumQryPhyStatusAll;
681 bool MPDIG_2G; /* off MPDIG */
684 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
686 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
688 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
690 /* REMOVED COMMON INFO---------- */
691 /* u8 PseudoMacPhyMode; */
692 /* bool *BTCoexist; */
693 /* bool PseudoBtCoexist; */
696 /* bool bClientMode; */
697 /* bool bAdHocMode; */
698 /* bool bSlaveOfDMSP; */
699 /* REMOVED COMMON INFO---------- */
701 /* 1 COMMON INFORMATION */
706 /* HOOK BEFORE REG INIT----------- */
707 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
709 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
711 /* ODM PCIE/USB/SDIO = 1/2/3 */
713 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
715 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
717 /* Fab Version TSMC/UMC = 0/1 */
719 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
721 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
728 /* with external LNA NO/Yes = 0/1 */
730 /* with external PA NO/Yes = 0/1 */
732 /* with external TRSW NO/Yes = 0/1 */
734 u8 PatchID; /* Customer ID */
738 bool bDualMacSmartConcurrent;
739 u32 BK_SupportAbility;
741 /* HOOK BEFORE REG INIT----------- */
746 /* POINTER REFERENCE----------- */
750 struct adapter *adapter_temp;
752 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
754 /* TX Unicast byte count */
755 u64 *pNumTxBytesUnicast;
756 /* RX Unicast byte count */
757 u64 *pNumRxBytesUnicast;
758 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
759 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
760 /* Secondary channel offset don't_care/below/above = 0/1/2 */
762 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
764 /* BW info 20M/40M/80M = 0/1/2 */
766 /* Central channel location Ch1/Ch2/.... */
767 u8 *pChannel; /* central channel number */
769 /* Common info for 92D DMSP */
771 bool *pbGetValueFromOtherMac;
772 struct adapter **pBuddyAdapter;
773 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
774 /* Common info for Status */
775 bool *pbScanInProcess;
777 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
779 /* pMgntInfo->AntennaTest */
785 /* For 8723B IQK----------- */
790 /* POINTER REFERENCE----------- */
791 u16 *pForcedDataRate;
792 /* CALL BY VALUE------------- */
800 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
802 /* Common info for BTDM */
803 bool bBtEnabled; /* BT is disabled */
804 bool bBtConnectProcess; /* BT HS is under connection progress. */
805 u8 btHsRssi; /* BT HS mode wifi rssi value. */
806 bool bBtHsOperation; /* BT HS mode is under progress */
807 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */
808 bool bBtLimitedDig; /* BT is busy. */
809 /* CALL BY VALUE------------- */
822 u32 TxagcOffsetValueA;
823 bool IsTxagcOffsetPositiveA;
824 u32 TxagcOffsetValueB;
825 bool IsTxagcOffsetPositiveB;
829 bool IsBbSwingOffsetPositiveA;
831 bool IsBbSwingOffsetPositiveB;
847 bool H2C_RARpt_connect;
849 /* add by Yu Cehn for adaptivtiy */
850 bool adaptivity_flag;
853 bool Carrier_Sense_enable;
863 u8 Adaptivity_IGI_upper;
866 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */
868 /* 2 Define STA info. */
870 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
871 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
874 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
875 /* We need to colelct all support abilit to a proper area. */
879 /* Define ........... */
881 /* Latest packet phy info (ODM write) */
882 struct odm_phy_dbg_info PhyDbgInfo;
883 /* PHY_INFO_88E PhyInfo; */
885 /* Latest packet phy info (ODM write) */
886 struct odm_mac_status_info *pMacInfo;
887 /* MAC_INFO_88E MacInfo; */
889 /* Different Team independt structure?? */
892 /* TX_RTP_CMN TX_retrpo; */
893 /* TX_RTP_88E TX_retrpo; */
894 /* TX_RTP_8195 TX_retrpo; */
899 struct fat_t DM_FatTable;
900 struct dig_t DM_DigTable;
901 struct ps_t DM_PSTable;
902 struct dynamic_primary_CCA DM_PriCCA;
903 struct rxhp_t dM_RXHP_Table;
904 struct ra_t DM_RA_Table;
905 struct false_ALARM_STATISTICS FalseAlmCnt;
906 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
907 struct swat_t DM_SWAT_Table;
909 struct cfo_tracking DM_CfoTrack;
911 struct edca_t DM_EDCA_Table;
913 struct pathdiv_t DM_PathDiv;
914 /* Copy from SD4 structure */
916 /* ================================================== */
921 /* u8 PSD_Report_RXHP[80]; Add By Gary */
922 /* u8 PSD_func_flag; Add By Gary */
924 /* u8 bDMInitialGainEnable; */
925 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */
926 /* for Antenna diversity */
927 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
928 /* PSTA_INFO_T RSSI_target; */
930 bool *pbDriverStopped;
931 bool *pbDriverIsGoingToPnpSetPowerSleep;
932 bool *pinit_adpt_in_progress;
935 bool bUserAssignLevel;
936 struct timer_list PSDTimer;
937 u8 RSSI_BT; /* come from BT */
940 bool bDMInitialGainEnable;
943 struct timer_list MPT_DIGTimer;
945 /* for rate adaptive, in fact, 88c/92c fw will handle this */
948 struct odm_rate_adaptive RateAdaptive;
950 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */
952 struct odm_rf_cal_t RFCalibrateInfo;
955 /* TX power tracking */
957 u8 BbSwingIdxOfdm[MAX_RF_PATH];
958 u8 BbSwingIdxOfdmCurrent;
959 u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
960 bool BbSwingFlagOfdm;
962 u8 BbSwingIdxCckCurrent;
963 u8 BbSwingIdxCckBase;
968 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
969 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
970 s8 Remnant_CCKSwingIdx;
971 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */
972 bool Modify_TxAGC_Flag_PathA;
973 bool Modify_TxAGC_Flag_PathB;
974 bool Modify_TxAGC_Flag_PathC;
975 bool Modify_TxAGC_Flag_PathD;
976 bool Modify_TxAGC_Flag_PathA_CCK;
978 s8 KfreeOffset[MAX_RF_PATH];
980 /* ODM system resource. */
983 /* ODM relative time. */
984 struct timer_list PathDivSwitchTimer;
985 /* 2011.09.27 add for Path Diversity */
986 struct timer_list CCKPathDiversityTimer;
987 struct timer_list FastAntTrainingTimer;
989 /* ODM relative workitem. */
991 #if (BEAMFORMING_SUPPORT == 1)
992 RT_BEAMFORMING_INFO BeamformingInfo;
996 enum odm_rf_content {
997 odm_radioa_txt = 0x1000,
998 odm_radiob_txt = 0x1001,
999 odm_radioc_txt = 0x1002,
1000 odm_radiod_txt = 0x1003
1003 enum ODM_BB_Config_Type {
1006 CONFIG_BB_AGC_TAB_2G,
1007 CONFIG_BB_PHY_REG_PG,
1008 CONFIG_BB_PHY_REG_MP,
1009 CONFIG_BB_AGC_TAB_DIFF,
1012 enum ODM_RF_Config_Type {
1014 CONFIG_RF_TXPWR_LMT,
1017 enum ODM_FW_Config_Type {
1023 CONFIG_FW_AP_WoWLAN,
1031 /* include "odm_function.h" */
1033 /* 3 =========================================================== */
1035 /* 3 =========================================================== */
1037 /* Remove DIG by Yuchen */
1039 /* 3 =========================================================== */
1040 /* 3 AGC RX High Power Mode */
1041 /* 3 =========================================================== */
1042 #define LNA_Low_Gain_1 0x64
1043 #define LNA_Low_Gain_2 0x5A
1044 #define LNA_Low_Gain_3 0x58
1046 #define FA_RXHP_TH1 5000
1047 #define FA_RXHP_TH2 1500
1048 #define FA_RXHP_TH3 800
1049 #define FA_RXHP_TH4 600
1050 #define FA_RXHP_TH5 500
1052 /* 3 =========================================================== */
1054 /* 3 =========================================================== */
1056 /* 3 =========================================================== */
1057 /* 3 Dynamic Tx Power */
1058 /* 3 =========================================================== */
1059 /* Dynamic Tx Power Control Threshold */
1061 /* 3 =========================================================== */
1062 /* 3 Rate Adaptive */
1063 /* 3 =========================================================== */
1064 #define DM_RATR_STA_INIT 0
1065 #define DM_RATR_STA_HIGH 1
1066 #define DM_RATR_STA_MIDDLE 2
1067 #define DM_RATR_STA_LOW 3
1069 /* 3 =========================================================== */
1070 /* 3 BB Power Save */
1071 /* 3 =========================================================== */
1073 enum { /* tag_1R_CCA_Type_Definition */
1079 enum { /* tag_RF_Type_Definition */
1085 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1086 #define MAX_ANTENNA_DETECTION_CNT 10
1089 /* Extern Global Variables. */
1091 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1092 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1093 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1095 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1096 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1097 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1099 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1102 /* check Sta pointer valid or not */
1104 #define IS_STA_VALID(pSta) (pSta)
1105 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1106 /* This indicates two different the steps. */
1107 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1108 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1109 /* with original RSSI to determine if it is necessary to switch antenna. */
1110 #define SWAW_STEP_PEAK 0
1111 #define SWAW_STEP_DETERMINE 1
1113 /* Remove BB power saving by Yuchen */
1115 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1116 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm);
1118 bool ODM_RAStateCheck(
1119 struct dm_odm_t *pDM_Odm,
1125 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
1126 void ODM_SwAntDivChkPerPktRssi(
1127 struct dm_odm_t *pDM_Odm,
1129 struct odm_phy_info *pPhyInfo
1132 u32 ODM_Get_Rate_Bitmap(
1133 struct dm_odm_t *pDM_Odm,
1139 #if (BEAMFORMING_SUPPORT == 1)
1140 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1143 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm);
1145 void ODM_DMInit(struct dm_odm_t *pDM_Odm);
1147 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */
1149 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value);
1151 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue);
1153 void ODM_CmnInfoPtrArrayHook(
1154 struct dm_odm_t *pDM_Odm,
1155 enum odm_cmninfo_e CmnInfo,
1160 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value);
1162 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm);
1164 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm);
1166 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm);
1168 void ODM_AntselStatistics_88C(
1169 struct dm_odm_t *pDM_Odm,
1175 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State);